2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.
24 #ifndef __NEHALEM_MSR_H__
25 #define __NEHALEM_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Package. Model Specific Platform ID (R).
32 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
40 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
45 #define MSR_NEHALEM_PLATFORM_ID 0x00000017
48 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
52 /// Individual bit fields
58 /// [Bits 52:50] See Table 35-2.
64 /// All bit fields as a 64-bit value
67 } MSR_NEHALEM_PLATFORM_ID_REGISTER
;
71 Thread. SMI Counter (R/O).
73 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)
74 @param EAX Lower 32-bits of MSR value.
75 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
76 @param EDX Upper 32-bits of MSR value.
77 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
81 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;
83 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
86 #define MSR_NEHALEM_SMI_COUNT 0x00000034
89 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
93 /// Individual bit fields
97 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
104 /// All bit fields as a 32-bit value
108 /// All bit fields as a 64-bit value
111 } MSR_NEHALEM_SMI_COUNT_REGISTER
;
115 Package. see http://biosbits.org.
117 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
118 @param EAX Lower 32-bits of MSR value.
119 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
120 @param EDX Upper 32-bits of MSR value.
121 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
125 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;
127 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
128 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
131 #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE
134 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
138 /// Individual bit fields
143 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
144 /// of the frequency that invariant TSC runs at. The invariant TSC
145 /// frequency can be computed by multiplying this ratio by 133.33 MHz.
147 UINT32 MaximumNonTurboRatio
:8;
150 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
151 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
152 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
153 /// Turbo mode is disabled.
157 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
158 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
159 /// programmable, and when set to 0, indicates TDC and TDP Limits for
160 /// Turbo mode are not programmable.
162 UINT32 TDC_TDPLimit
:1;
166 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
167 /// minimum ratio (maximum efficiency) that the processor can operates, in
168 /// units of 133.33MHz.
170 UINT32 MaximumEfficiencyRatio
:8;
174 /// All bit fields as a 64-bit value
177 } MSR_NEHALEM_PLATFORM_INFO_REGISTER
;
181 Core. C-State Configuration Control (R/W) Note: C-state values are
182 processor specific C-state code names, unrelated to MWAIT extension C-state
183 parameters or ACPI CStates. See http://biosbits.org.
185 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
186 @param EAX Lower 32-bits of MSR value.
187 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
188 @param EDX Upper 32-bits of MSR value.
189 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
193 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
195 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
196 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
199 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2
202 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
206 /// Individual bit fields
210 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
211 /// processor-specific C-state code name (consuming the least power). for
212 /// the package. The default is set as factory-configured package C-state
213 /// limit. The following C-state code name encodings are supported: 000b:
214 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
215 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
216 /// C-state limit. Note: This field cannot be used to limit package
222 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
223 /// IO_read instructions sent to IO register specified by
224 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
229 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
230 /// until next reset.
235 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores
236 /// in a deep C-State will wake only when the event message is destined
237 /// for that core. When 0, all processor cores in a deep C-State will wake
238 /// for an event message.
240 UINT32 InterruptFiltering
:1;
242 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
243 /// will conditionally demote C6/C7 requests to C3 based on uncore
244 /// auto-demote information.
246 UINT32 C3AutoDemotion
:1;
248 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
249 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
250 /// auto-demote information.
252 UINT32 C1AutoDemotion
:1;
257 /// All bit fields as a 32-bit value
261 /// All bit fields as a 64-bit value
264 } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
;
268 Core. Power Management IO Redirection in C-state (R/W) See
271 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
272 @param EAX Lower 32-bits of MSR value.
273 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
274 @param EDX Upper 32-bits of MSR value.
275 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
279 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;
281 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
282 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
285 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4
288 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
292 /// Individual bit fields
296 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
297 /// visible to software for IO redirection. If IO MWAIT Redirection is
298 /// enabled, reads to this address will be consumed by the power
299 /// management logic and decoded to MWAIT instructions. When IO port
300 /// address redirection is enabled, this is the IO port address reported
301 /// to the OS/software.
305 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
306 /// maximum C-State code name to be included when IO read to MWAIT
307 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
308 /// is the max C-State to include 001b - C6 is the max C-State to include
309 /// 010b - C7 is the max C-State to include.
311 UINT32 CStateRange
:3;
316 /// All bit fields as a 32-bit value
320 /// All bit fields as a 64-bit value
323 } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
;
327 Enable Misc. Processor Features (R/W) Allows a variety of processor
328 functions to be enabled and disabled.
330 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
331 @param EAX Lower 32-bits of MSR value.
332 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
333 @param EDX Upper 32-bits of MSR value.
334 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
338 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;
340 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
341 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
344 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0
347 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
351 /// Individual bit fields
355 /// [Bit 0] Thread. Fast-Strings Enable See Table 35-2.
357 UINT32 FastStrings
:1;
360 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
363 UINT32 AutomaticThermalControlCircuit
:1;
366 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 35-2.
368 UINT32 PerformanceMonitoring
:1;
371 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 35-2.
375 /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
381 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
387 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 35-2.
392 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 35-2.
394 UINT32 LimitCpuidMaxval
:1;
396 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 35-2.
398 UINT32 xTPR_Message_Disable
:1;
402 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 35-2.
407 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
408 /// that support Intel Turbo Boost Technology, the turbo mode feature is
409 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
410 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
411 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
412 /// the power-on default value is used by BIOS to detect hardware support
413 /// of turbo mode. If power-on default value is 1, turbo mode is available
414 /// in the processor. If power-on default value is 0, turbo mode is not
417 UINT32 TurboModeDisable
:1;
418 UINT32 Reserved10
:25;
421 /// All bit fields as a 64-bit value
424 } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
;
430 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
431 @param EAX Lower 32-bits of MSR value.
432 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
433 @param EDX Upper 32-bits of MSR value.
434 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
438 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;
440 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
441 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
444 #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2
447 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
451 /// Individual bit fields
456 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
457 /// PROCHOT# will be asserted. The value is degree C.
459 UINT32 TemperatureTarget
:8;
464 /// All bit fields as a 32-bit value
468 /// All bit fields as a 64-bit value
471 } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
;
475 Miscellaneous Feature Control (R/W).
477 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
478 @param EAX Lower 32-bits of MSR value.
479 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
480 @param EDX Upper 32-bits of MSR value.
481 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
485 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;
487 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
488 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
491 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4
494 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
498 /// Individual bit fields
502 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
503 /// L2 hardware prefetcher, which fetches additional lines of code or data
504 /// into the L2 cache.
506 UINT32 L2HardwarePrefetcherDisable
:1;
508 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
509 /// disables the adjacent cache line prefetcher, which fetches the cache
510 /// line that comprises a cache line pair (128 bytes).
512 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
514 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
515 /// the L1 data cache prefetcher, which fetches the next cache line into
518 UINT32 DCUHardwarePrefetcherDisable
:1;
520 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
521 /// data cache IP prefetcher, which uses sequential load history (based on
522 /// instruction Pointer of previous loads) to determine whether to
523 /// prefetch additional lines.
525 UINT32 DCUIPPrefetcherDisable
:1;
530 /// All bit fields as a 32-bit value
534 /// All bit fields as a 64-bit value
537 } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
;
541 Thread. Offcore Response Event Select Register (R/W).
543 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
544 @param EAX Lower 32-bits of MSR value.
545 @param EDX Upper 32-bits of MSR value.
551 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
552 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
555 #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6
559 See http://biosbits.org.
561 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
562 @param EAX Lower 32-bits of MSR value.
563 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
564 @param EDX Upper 32-bits of MSR value.
565 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
569 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;
571 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
572 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
575 #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA
578 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
582 /// Individual bit fields
586 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
587 /// enables hardware coordination of Enhanced Intel Speedstep Technology
588 /// request from processor cores; When 1, disables hardware coordination
589 /// of Enhanced Intel Speedstep Technology requests.
591 UINT32 EISTHardwareCoordinationDisable
:1;
593 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes
594 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
595 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
596 /// CPUID.(EAX=06h):ECX[3].
598 UINT32 EnergyPerformanceBiasEnable
:1;
603 /// All bit fields as a 32-bit value
607 /// All bit fields as a 64-bit value
610 } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
;
614 See http://biosbits.org.
616 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
617 @param EAX Lower 32-bits of MSR value.
618 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
619 @param EDX Upper 32-bits of MSR value.
620 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
624 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;
626 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
627 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
630 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC
633 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
637 /// Individual bit fields
641 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt
646 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0
647 /// indicates override is not active, and a value = 1 indicates active.
649 UINT32 TDPLimitOverrideEnable
:1;
651 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp
656 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0
657 /// indicates override is not active, and a value = 1 indicates active.
659 UINT32 TDCLimitOverrideEnable
:1;
663 /// All bit fields as a 32-bit value
667 /// All bit fields as a 64-bit value
670 } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
;
674 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
675 RW if MSR_PLATFORM_INFO.[28] = 1.
677 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
678 @param EAX Lower 32-bits of MSR value.
679 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
680 @param EDX Upper 32-bits of MSR value.
681 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
685 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;
687 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
690 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD
693 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
697 /// Individual bit fields
701 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
702 /// limit of 1 core active.
706 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
707 /// limit of 2 core active.
711 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
712 /// limit of 3 core active.
716 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
717 /// limit of 4 core active.
723 /// All bit fields as a 32-bit value
727 /// All bit fields as a 64-bit value
730 } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
;
734 Core. Last Branch Record Filtering Select Register (R/W) See Section
735 17.6.2, "Filtering of Last Branch Records.".
737 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
738 @param EAX Lower 32-bits of MSR value.
739 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
740 @param EDX Upper 32-bits of MSR value.
741 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
745 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;
747 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
748 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
751 #define MSR_NEHALEM_LBR_SELECT 0x000001C8
754 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
758 /// Individual bit fields
762 /// [Bit 0] CPL_EQ_0.
766 /// [Bit 1] CPL_NEQ_0.
774 /// [Bit 3] NEAR_REL_CALL.
776 UINT32 NEAR_REL_CALL
:1;
778 /// [Bit 4] NEAR_IND_CALL.
780 UINT32 NEAR_IND_CALL
:1;
782 /// [Bit 5] NEAR_RET.
786 /// [Bit 6] NEAR_IND_JMP.
788 UINT32 NEAR_IND_JMP
:1;
790 /// [Bit 7] NEAR_REL_JMP.
792 UINT32 NEAR_REL_JMP
:1;
794 /// [Bit 8] FAR_BRANCH.
801 /// All bit fields as a 32-bit value
805 /// All bit fields as a 64-bit value
808 } MSR_NEHALEM_LBR_SELECT_REGISTER
;
812 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
813 that points to the MSR containing the most recent branch record. See
814 MSR_LASTBRANCH_0_FROM_IP (at 680H).
816 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
817 @param EAX Lower 32-bits of MSR value.
818 @param EDX Upper 32-bits of MSR value.
824 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
825 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
828 #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9
832 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
833 last branch instruction that the processor executed prior to the last
834 exception that was generated or the last interrupt that was handled.
836 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
837 @param EAX Lower 32-bits of MSR value.
838 @param EDX Upper 32-bits of MSR value.
844 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
847 #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD
851 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
852 to the target of the last branch instruction that the processor executed
853 prior to the last exception that was generated or the last interrupt that
856 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)
857 @param EAX Lower 32-bits of MSR value.
858 @param EDX Upper 32-bits of MSR value.
864 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
867 #define MSR_NEHALEM_LER_TO_LIP 0x000001DE
871 Core. Power Control Register. See http://biosbits.org.
873 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)
874 @param EAX Lower 32-bits of MSR value.
875 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
876 @param EDX Upper 32-bits of MSR value.
877 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
881 MSR_NEHALEM_POWER_CTL_REGISTER Msr;
883 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
884 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
887 #define MSR_NEHALEM_POWER_CTL 0x000001FC
890 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
894 /// Individual bit fields
899 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
900 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
901 /// operating point when all execution cores enter MWAIT (C1).
908 /// All bit fields as a 32-bit value
912 /// All bit fields as a 64-bit value
915 } MSR_NEHALEM_POWER_CTL_REGISTER
;
919 Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
922 @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
923 @param EAX Lower 32-bits of MSR value.
924 @param EDX Upper 32-bits of MSR value.
930 Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);
931 AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);
934 #define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E
940 @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)
941 @param EAX Lower 32-bits of MSR value.
942 Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
943 @param EDX Upper 32-bits of MSR value.
944 Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
948 MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;
950 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);
953 #define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E
956 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS
960 /// Individual bit fields
966 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
972 /// All bit fields as a 64-bit value
975 } MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER
;
981 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
982 @param EAX Lower 32-bits of MSR value.
983 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
984 @param EDX Upper 32-bits of MSR value.
985 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
989 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
991 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
992 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
995 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390
998 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
1002 /// Individual bit fields
1005 UINT32 Reserved1
:32;
1006 UINT32 Reserved2
:29;
1008 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
1010 UINT32 Ovf_Uncore
:1;
1014 /// All bit fields as a 64-bit value
1017 } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1021 Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
1023 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
1024 @param EAX Lower 32-bits of MSR value.
1025 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1026 @param EDX Upper 32-bits of MSR value.
1027 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1029 <b>Example usage</b>
1031 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;
1033 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
1034 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
1037 #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1
1040 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
1044 /// Individual bit fields
1048 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1050 UINT32 PEBS_EN_PMC0
:1;
1052 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1054 UINT32 PEBS_EN_PMC1
:1;
1056 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1058 UINT32 PEBS_EN_PMC2
:1;
1060 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1062 UINT32 PEBS_EN_PMC3
:1;
1063 UINT32 Reserved1
:28;
1065 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1067 UINT32 LL_EN_PMC0
:1;
1069 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1071 UINT32 LL_EN_PMC1
:1;
1073 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1075 UINT32 LL_EN_PMC2
:1;
1077 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1079 UINT32 LL_EN_PMC3
:1;
1080 UINT32 Reserved2
:28;
1083 /// All bit fields as a 64-bit value
1086 } MSR_NEHALEM_PEBS_ENABLE_REGISTER
;
1090 Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring
1093 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
1094 @param EAX Lower 32-bits of MSR value.
1095 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1096 @param EDX Upper 32-bits of MSR value.
1097 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1099 <b>Example usage</b>
1101 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;
1103 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
1104 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
1107 #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6
1110 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
1114 /// Individual bit fields
1118 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1119 /// that will be counted. (R/W).
1121 UINT32 MinimumThreshold
:16;
1122 UINT32 Reserved1
:16;
1123 UINT32 Reserved2
:32;
1126 /// All bit fields as a 32-bit value
1130 /// All bit fields as a 64-bit value
1133 } MSR_NEHALEM_PEBS_LD_LAT_REGISTER
;
1137 Package. Note: C-state values are processor specific C-state code names,
1138 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1139 Residency Counter. (R/O) Value since last reset that this package is in
1140 processor-specific C3 states. Count at the same frequency as the TSC.
1142 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
1143 @param EAX Lower 32-bits of MSR value.
1144 @param EDX Upper 32-bits of MSR value.
1146 <b>Example usage</b>
1150 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
1151 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
1154 #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8
1158 Package. Note: C-state values are processor specific C-state code names,
1159 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1160 Residency Counter. (R/O) Value since last reset that this package is in
1161 processor-specific C6 states. Count at the same frequency as the TSC.
1163 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
1164 @param EAX Lower 32-bits of MSR value.
1165 @param EDX Upper 32-bits of MSR value.
1167 <b>Example usage</b>
1171 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
1172 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
1175 #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9
1179 Package. Note: C-state values are processor specific C-state code names,
1180 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1181 Residency Counter. (R/O) Value since last reset that this package is in
1182 processor-specific C7 states. Count at the same frequency as the TSC.
1184 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
1185 @param EAX Lower 32-bits of MSR value.
1186 @param EDX Upper 32-bits of MSR value.
1188 <b>Example usage</b>
1192 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
1193 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
1196 #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA
1200 Core. Note: C-state values are processor specific C-state code names,
1201 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1202 Residency Counter. (R/O) Value since last reset that this core is in
1203 processor-specific C3 states. Count at the same frequency as the TSC.
1205 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
1206 @param EAX Lower 32-bits of MSR value.
1207 @param EDX Upper 32-bits of MSR value.
1209 <b>Example usage</b>
1213 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
1214 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
1217 #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC
1221 Core. Note: C-state values are processor specific C-state code names,
1222 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1223 Residency Counter. (R/O) Value since last reset that this core is in
1224 processor-specific C6 states. Count at the same frequency as the TSC.
1226 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
1227 @param EAX Lower 32-bits of MSR value.
1228 @param EDX Upper 32-bits of MSR value.
1230 <b>Example usage</b>
1234 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
1235 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
1238 #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD
1242 See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
1244 @param ECX MSR_NEHALEM_MCi_MISC
1245 @param EAX Lower 32-bits of MSR value.
1246 @param EDX Upper 32-bits of MSR value.
1248 <b>Example usage</b>
1252 Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);
1253 AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);
1257 #define MSR_NEHALEM_MC0_MISC 0x00000403
1258 #define MSR_NEHALEM_MC1_MISC 0x00000407
1259 #define MSR_NEHALEM_MC2_MISC 0x0000040B
1260 #define MSR_NEHALEM_MC3_MISC 0x0000040F
1261 #define MSR_NEHALEM_MC4_MISC 0x00000413
1262 #define MSR_NEHALEM_MC5_MISC 0x00000417
1263 #define MSR_NEHALEM_MC6_MISC 0x0000041B
1264 #define MSR_NEHALEM_MC7_MISC 0x0000041F
1265 #define MSR_NEHALEM_MC8_MISC 0x00000423
1266 #define MSR_NEHALEM_MC9_MISC 0x00000427
1267 #define MSR_NEHALEM_MC10_MISC 0x0000042B
1268 #define MSR_NEHALEM_MC11_MISC 0x0000042F
1269 #define MSR_NEHALEM_MC12_MISC 0x00000433
1270 #define MSR_NEHALEM_MC13_MISC 0x00000437
1271 #define MSR_NEHALEM_MC14_MISC 0x0000043B
1272 #define MSR_NEHALEM_MC15_MISC 0x0000043F
1273 #define MSR_NEHALEM_MC16_MISC 0x00000443
1274 #define MSR_NEHALEM_MC17_MISC 0x00000447
1275 #define MSR_NEHALEM_MC18_MISC 0x0000044B
1276 #define MSR_NEHALEM_MC19_MISC 0x0000044F
1277 #define MSR_NEHALEM_MC20_MISC 0x00000453
1278 #define MSR_NEHALEM_MC21_MISC 0x00000457
1283 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1285 @param ECX MSR_NEHALEM_MCi_CTL
1286 @param EAX Lower 32-bits of MSR value.
1287 @param EDX Upper 32-bits of MSR value.
1289 <b>Example usage</b>
1293 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);
1294 AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);
1298 #define MSR_NEHALEM_MC3_CTL 0x0000040C
1299 #define MSR_NEHALEM_MC4_CTL 0x00000410
1300 #define MSR_NEHALEM_MC5_CTL 0x00000414
1301 #define MSR_NEHALEM_MC6_CTL 0x00000418
1302 #define MSR_NEHALEM_MC7_CTL 0x0000041C
1303 #define MSR_NEHALEM_MC8_CTL 0x00000420
1304 #define MSR_NEHALEM_MC9_CTL 0x00000424
1305 #define MSR_NEHALEM_MC10_CTL 0x00000428
1306 #define MSR_NEHALEM_MC11_CTL 0x0000042C
1307 #define MSR_NEHALEM_MC12_CTL 0x00000430
1308 #define MSR_NEHALEM_MC13_CTL 0x00000434
1309 #define MSR_NEHALEM_MC14_CTL 0x00000438
1310 #define MSR_NEHALEM_MC15_CTL 0x0000043C
1311 #define MSR_NEHALEM_MC16_CTL 0x00000440
1312 #define MSR_NEHALEM_MC17_CTL 0x00000444
1313 #define MSR_NEHALEM_MC18_CTL 0x00000448
1314 #define MSR_NEHALEM_MC19_CTL 0x0000044C
1315 #define MSR_NEHALEM_MC20_CTL 0x00000450
1316 #define MSR_NEHALEM_MC21_CTL 0x00000454
1321 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
1323 @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)
1324 @param EAX Lower 32-bits of MSR value.
1325 @param EDX Upper 32-bits of MSR value.
1327 <b>Example usage</b>
1331 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);
1332 AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);
1336 #define MSR_NEHALEM_MC3_STATUS 0x0000040D
1337 #define MSR_NEHALEM_MC4_STATUS 0x00000411
1338 #define MSR_NEHALEM_MC5_STATUS 0x00000415
1339 #define MSR_NEHALEM_MC6_STATUS 0x00000419
1340 #define MSR_NEHALEM_MC7_STATUS 0x0000041D
1341 #define MSR_NEHALEM_MC8_STATUS 0x00000421
1342 #define MSR_NEHALEM_MC9_STATUS 0x00000425
1343 #define MSR_NEHALEM_MC10_STATUS 0x00000429
1344 #define MSR_NEHALEM_MC11_STATUS 0x0000042D
1345 #define MSR_NEHALEM_MC12_STATUS 0x00000431
1346 #define MSR_NEHALEM_MC13_STATUS 0x00000435
1347 #define MSR_NEHALEM_MC14_STATUS 0x00000439
1348 #define MSR_NEHALEM_MC15_STATUS 0x0000043D
1349 #define MSR_NEHALEM_MC16_STATUS 0x00000441
1350 #define MSR_NEHALEM_MC17_STATUS 0x00000445
1351 #define MSR_NEHALEM_MC18_STATUS 0x00000449
1352 #define MSR_NEHALEM_MC19_STATUS 0x0000044D
1353 #define MSR_NEHALEM_MC20_STATUS 0x00000451
1354 #define MSR_NEHALEM_MC21_STATUS 0x00000455
1359 Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."
1361 The MSR_MC3_ADDR register is either not implemented or contains no address
1362 if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not
1363 implemented in the processor, all reads and writes to this MSR will cause a
1364 general-protection exception.
1366 The MSR_MC4_ADDR register is either not implemented or contains no address
1367 if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not
1368 implemented in the processor, all reads and writes to this MSR will cause a
1369 general-protection exception.
1371 @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)
1372 @param EAX Lower 32-bits of MSR value.
1373 @param EDX Upper 32-bits of MSR value.
1375 <b>Example usage</b>
1379 Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);
1380 AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);
1384 #define MSR_NEHALEM_MC3_ADDR 0x0000040E
1385 #define MSR_NEHALEM_MC4_ADDR 0x00000412
1386 #define MSR_NEHALEM_MC5_ADDR 0x00000416
1387 #define MSR_NEHALEM_MC6_ADDR 0x0000041A
1388 #define MSR_NEHALEM_MC7_ADDR 0x0000041E
1389 #define MSR_NEHALEM_MC8_ADDR 0x00000422
1390 #define MSR_NEHALEM_MC9_ADDR 0x00000426
1391 #define MSR_NEHALEM_MC10_ADDR 0x0000042A
1392 #define MSR_NEHALEM_MC11_ADDR 0x0000042E
1393 #define MSR_NEHALEM_MC12_ADDR 0x00000432
1394 #define MSR_NEHALEM_MC13_ADDR 0x00000436
1395 #define MSR_NEHALEM_MC14_ADDR 0x0000043A
1396 #define MSR_NEHALEM_MC15_ADDR 0x0000043E
1397 #define MSR_NEHALEM_MC16_ADDR 0x00000442
1398 #define MSR_NEHALEM_MC17_ADDR 0x00000446
1399 #define MSR_NEHALEM_MC18_ADDR 0x0000044A
1400 #define MSR_NEHALEM_MC19_ADDR 0x0000044E
1401 #define MSR_NEHALEM_MC20_ADDR 0x00000452
1402 #define MSR_NEHALEM_MC21_ADDR 0x00000456
1407 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1408 branch record registers on the last branch record stack. This part of the
1409 stack contains pointers to the source instruction for one of the last
1410 sixteen branches, exceptions, or interrupts taken by the processor. See
1411 also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
1414 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
1415 @param EAX Lower 32-bits of MSR value.
1416 @param EDX Upper 32-bits of MSR value.
1418 <b>Example usage</b>
1422 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
1423 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
1427 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680
1428 #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681
1429 #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682
1430 #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683
1431 #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684
1432 #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685
1433 #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686
1434 #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687
1435 #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688
1436 #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689
1437 #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A
1438 #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B
1439 #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C
1440 #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D
1441 #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E
1442 #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F
1447 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1448 record registers on the last branch record stack. This part of the stack
1449 contains pointers to the destination instruction for one of the last sixteen
1450 branches, exceptions, or interrupts taken by the processor.
1452 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
1453 @param EAX Lower 32-bits of MSR value.
1454 @param EDX Upper 32-bits of MSR value.
1456 <b>Example usage</b>
1460 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
1461 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
1465 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0
1466 #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1
1467 #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2
1468 #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3
1469 #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4
1470 #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5
1471 #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6
1472 #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7
1473 #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8
1474 #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9
1475 #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA
1476 #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB
1477 #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC
1478 #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD
1479 #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE
1480 #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF
1487 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
1488 @param EAX Lower 32-bits of MSR value.
1489 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1490 @param EDX Upper 32-bits of MSR value.
1491 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1493 <b>Example usage</b>
1495 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;
1497 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
1498 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
1501 #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301
1504 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
1508 /// Individual bit fields
1512 /// [Bit 0] From M to S (R/W).
1516 /// [Bit 1] From E to S (R/W).
1520 /// [Bit 2] From S to S (R/W).
1524 /// [Bit 3] From F to S (R/W).
1528 /// [Bit 4] From M to I (R/W).
1532 /// [Bit 5] From E to I (R/W).
1536 /// [Bit 6] From S to I (R/W).
1540 /// [Bit 7] From F to I (R/W).
1543 UINT32 Reserved1
:24;
1544 UINT32 Reserved2
:32;
1547 /// All bit fields as a 32-bit value
1551 /// All bit fields as a 64-bit value
1554 } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
;
1558 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1561 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
1562 @param EAX Lower 32-bits of MSR value.
1563 @param EDX Upper 32-bits of MSR value.
1565 <b>Example usage</b>
1569 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
1570 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
1573 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
1577 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1580 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
1581 @param EAX Lower 32-bits of MSR value.
1582 @param EDX Upper 32-bits of MSR value.
1584 <b>Example usage</b>
1588 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
1589 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
1592 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
1596 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1599 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
1600 @param EAX Lower 32-bits of MSR value.
1601 @param EDX Upper 32-bits of MSR value.
1603 <b>Example usage</b>
1607 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
1608 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
1611 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
1615 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1618 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
1619 @param EAX Lower 32-bits of MSR value.
1620 @param EDX Upper 32-bits of MSR value.
1622 <b>Example usage</b>
1626 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
1627 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
1630 #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394
1634 Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
1637 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
1638 @param EAX Lower 32-bits of MSR value.
1639 @param EDX Upper 32-bits of MSR value.
1641 <b>Example usage</b>
1645 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
1646 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
1649 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395
1653 Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".
1655 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
1656 @param EAX Lower 32-bits of MSR value.
1657 @param EDX Upper 32-bits of MSR value.
1659 <b>Example usage</b>
1663 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
1664 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
1667 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396
1671 Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
1674 @param ECX MSR_NEHALEM_UNCORE_PMCi
1675 @param EAX Lower 32-bits of MSR value.
1676 @param EDX Upper 32-bits of MSR value.
1678 <b>Example usage</b>
1682 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
1683 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
1687 #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0
1688 #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1
1689 #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2
1690 #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3
1691 #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4
1692 #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5
1693 #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6
1694 #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7
1698 Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
1701 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
1702 @param EAX Lower 32-bits of MSR value.
1703 @param EDX Upper 32-bits of MSR value.
1705 <b>Example usage</b>
1709 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
1710 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
1714 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0
1715 #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1
1716 #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2
1717 #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3
1718 #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4
1719 #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5
1720 #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6
1721 #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7
1726 Package. Uncore W-box perfmon fixed counter.
1728 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
1729 @param EAX Lower 32-bits of MSR value.
1730 @param EDX Upper 32-bits of MSR value.
1732 <b>Example usage</b>
1736 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
1737 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
1740 #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394
1744 Package. Uncore U-box perfmon fixed counter control MSR.
1746 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
1747 @param EAX Lower 32-bits of MSR value.
1748 @param EDX Upper 32-bits of MSR value.
1750 <b>Example usage</b>
1754 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
1755 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
1758 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395
1762 Package. Uncore U-box perfmon global control MSR.
1764 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
1765 @param EAX Lower 32-bits of MSR value.
1766 @param EDX Upper 32-bits of MSR value.
1768 <b>Example usage</b>
1772 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
1773 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
1776 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00
1780 Package. Uncore U-box perfmon global status MSR.
1782 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
1783 @param EAX Lower 32-bits of MSR value.
1784 @param EDX Upper 32-bits of MSR value.
1786 <b>Example usage</b>
1790 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
1791 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
1794 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01
1798 Package. Uncore U-box perfmon global overflow control MSR.
1800 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
1801 @param EAX Lower 32-bits of MSR value.
1802 @param EDX Upper 32-bits of MSR value.
1804 <b>Example usage</b>
1808 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
1809 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
1812 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02
1816 Package. Uncore U-box perfmon event select MSR.
1818 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
1819 @param EAX Lower 32-bits of MSR value.
1820 @param EDX Upper 32-bits of MSR value.
1822 <b>Example usage</b>
1826 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
1827 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
1830 #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10
1834 Package. Uncore U-box perfmon counter MSR.
1836 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)
1837 @param EAX Lower 32-bits of MSR value.
1838 @param EDX Upper 32-bits of MSR value.
1840 <b>Example usage</b>
1844 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
1845 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
1848 #define MSR_NEHALEM_U_PMON_CTR 0x00000C11
1852 Package. Uncore B-box 0 perfmon local box control MSR.
1854 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
1855 @param EAX Lower 32-bits of MSR value.
1856 @param EDX Upper 32-bits of MSR value.
1858 <b>Example usage</b>
1862 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
1863 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
1866 #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20
1870 Package. Uncore B-box 0 perfmon local box status MSR.
1872 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
1873 @param EAX Lower 32-bits of MSR value.
1874 @param EDX Upper 32-bits of MSR value.
1876 <b>Example usage</b>
1880 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
1881 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
1884 #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21
1888 Package. Uncore B-box 0 perfmon local box overflow control MSR.
1890 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
1891 @param EAX Lower 32-bits of MSR value.
1892 @param EDX Upper 32-bits of MSR value.
1894 <b>Example usage</b>
1898 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
1899 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
1902 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22
1906 Package. Uncore B-box 0 perfmon event select MSR.
1908 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
1909 @param EAX Lower 32-bits of MSR value.
1910 @param EDX Upper 32-bits of MSR value.
1912 <b>Example usage</b>
1916 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
1917 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
1920 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30
1924 Package. Uncore B-box 0 perfmon counter MSR.
1926 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
1927 @param EAX Lower 32-bits of MSR value.
1928 @param EDX Upper 32-bits of MSR value.
1930 <b>Example usage</b>
1934 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
1935 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
1938 #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31
1942 Package. Uncore B-box 0 perfmon event select MSR.
1944 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
1945 @param EAX Lower 32-bits of MSR value.
1946 @param EDX Upper 32-bits of MSR value.
1948 <b>Example usage</b>
1952 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
1953 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
1956 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32
1960 Package. Uncore B-box 0 perfmon counter MSR.
1962 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
1963 @param EAX Lower 32-bits of MSR value.
1964 @param EDX Upper 32-bits of MSR value.
1966 <b>Example usage</b>
1970 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
1971 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
1974 #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33
1978 Package. Uncore B-box 0 perfmon event select MSR.
1980 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
1981 @param EAX Lower 32-bits of MSR value.
1982 @param EDX Upper 32-bits of MSR value.
1984 <b>Example usage</b>
1988 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
1989 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
1992 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34
1996 Package. Uncore B-box 0 perfmon counter MSR.
1998 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
1999 @param EAX Lower 32-bits of MSR value.
2000 @param EDX Upper 32-bits of MSR value.
2002 <b>Example usage</b>
2006 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
2007 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
2010 #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35
2014 Package. Uncore B-box 0 perfmon event select MSR.
2016 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
2017 @param EAX Lower 32-bits of MSR value.
2018 @param EDX Upper 32-bits of MSR value.
2020 <b>Example usage</b>
2024 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
2025 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
2028 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36
2032 Package. Uncore B-box 0 perfmon counter MSR.
2034 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
2035 @param EAX Lower 32-bits of MSR value.
2036 @param EDX Upper 32-bits of MSR value.
2038 <b>Example usage</b>
2042 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
2043 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
2046 #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37
2050 Package. Uncore S-box 0 perfmon local box control MSR.
2052 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
2053 @param EAX Lower 32-bits of MSR value.
2054 @param EDX Upper 32-bits of MSR value.
2056 <b>Example usage</b>
2060 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
2061 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
2064 #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40
2068 Package. Uncore S-box 0 perfmon local box status MSR.
2070 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
2071 @param EAX Lower 32-bits of MSR value.
2072 @param EDX Upper 32-bits of MSR value.
2074 <b>Example usage</b>
2078 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
2079 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
2082 #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41
2086 Package. Uncore S-box 0 perfmon local box overflow control MSR.
2088 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
2089 @param EAX Lower 32-bits of MSR value.
2090 @param EDX Upper 32-bits of MSR value.
2092 <b>Example usage</b>
2096 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
2097 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
2100 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42
2104 Package. Uncore S-box 0 perfmon event select MSR.
2106 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
2107 @param EAX Lower 32-bits of MSR value.
2108 @param EDX Upper 32-bits of MSR value.
2110 <b>Example usage</b>
2114 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
2115 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
2118 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50
2122 Package. Uncore S-box 0 perfmon counter MSR.
2124 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
2125 @param EAX Lower 32-bits of MSR value.
2126 @param EDX Upper 32-bits of MSR value.
2128 <b>Example usage</b>
2132 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
2133 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
2136 #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51
2140 Package. Uncore S-box 0 perfmon event select MSR.
2142 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
2143 @param EAX Lower 32-bits of MSR value.
2144 @param EDX Upper 32-bits of MSR value.
2146 <b>Example usage</b>
2150 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
2151 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
2154 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52
2158 Package. Uncore S-box 0 perfmon counter MSR.
2160 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
2161 @param EAX Lower 32-bits of MSR value.
2162 @param EDX Upper 32-bits of MSR value.
2164 <b>Example usage</b>
2168 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
2169 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
2172 #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53
2176 Package. Uncore S-box 0 perfmon event select MSR.
2178 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
2179 @param EAX Lower 32-bits of MSR value.
2180 @param EDX Upper 32-bits of MSR value.
2182 <b>Example usage</b>
2186 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
2187 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
2190 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54
2194 Package. Uncore S-box 0 perfmon counter MSR.
2196 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
2197 @param EAX Lower 32-bits of MSR value.
2198 @param EDX Upper 32-bits of MSR value.
2200 <b>Example usage</b>
2204 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
2205 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
2208 #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55
2212 Package. Uncore S-box 0 perfmon event select MSR.
2214 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
2215 @param EAX Lower 32-bits of MSR value.
2216 @param EDX Upper 32-bits of MSR value.
2218 <b>Example usage</b>
2222 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
2223 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
2226 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56
2230 Package. Uncore S-box 0 perfmon counter MSR.
2232 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
2233 @param EAX Lower 32-bits of MSR value.
2234 @param EDX Upper 32-bits of MSR value.
2236 <b>Example usage</b>
2240 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
2241 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
2244 #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57
2248 Package. Uncore B-box 1 perfmon local box control MSR.
2250 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
2251 @param EAX Lower 32-bits of MSR value.
2252 @param EDX Upper 32-bits of MSR value.
2254 <b>Example usage</b>
2258 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
2259 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
2262 #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60
2266 Package. Uncore B-box 1 perfmon local box status MSR.
2268 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
2269 @param EAX Lower 32-bits of MSR value.
2270 @param EDX Upper 32-bits of MSR value.
2272 <b>Example usage</b>
2276 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
2277 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
2280 #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61
2284 Package. Uncore B-box 1 perfmon local box overflow control MSR.
2286 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
2287 @param EAX Lower 32-bits of MSR value.
2288 @param EDX Upper 32-bits of MSR value.
2290 <b>Example usage</b>
2294 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
2295 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
2298 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62
2302 Package. Uncore B-box 1 perfmon event select MSR.
2304 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
2305 @param EAX Lower 32-bits of MSR value.
2306 @param EDX Upper 32-bits of MSR value.
2308 <b>Example usage</b>
2312 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
2313 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
2316 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70
2320 Package. Uncore B-box 1 perfmon counter MSR.
2322 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
2323 @param EAX Lower 32-bits of MSR value.
2324 @param EDX Upper 32-bits of MSR value.
2326 <b>Example usage</b>
2330 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
2331 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
2334 #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71
2338 Package. Uncore B-box 1 perfmon event select MSR.
2340 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
2341 @param EAX Lower 32-bits of MSR value.
2342 @param EDX Upper 32-bits of MSR value.
2344 <b>Example usage</b>
2348 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
2349 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
2352 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72
2356 Package. Uncore B-box 1 perfmon counter MSR.
2358 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
2359 @param EAX Lower 32-bits of MSR value.
2360 @param EDX Upper 32-bits of MSR value.
2362 <b>Example usage</b>
2366 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
2367 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
2370 #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73
2374 Package. Uncore B-box 1 perfmon event select MSR.
2376 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
2377 @param EAX Lower 32-bits of MSR value.
2378 @param EDX Upper 32-bits of MSR value.
2380 <b>Example usage</b>
2384 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
2385 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
2388 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74
2392 Package. Uncore B-box 1 perfmon counter MSR.
2394 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
2395 @param EAX Lower 32-bits of MSR value.
2396 @param EDX Upper 32-bits of MSR value.
2398 <b>Example usage</b>
2402 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
2403 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
2406 #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75
2410 Package. Uncore B-box 1vperfmon event select MSR.
2412 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
2413 @param EAX Lower 32-bits of MSR value.
2414 @param EDX Upper 32-bits of MSR value.
2416 <b>Example usage</b>
2420 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
2421 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
2424 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76
2428 Package. Uncore B-box 1 perfmon counter MSR.
2430 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
2431 @param EAX Lower 32-bits of MSR value.
2432 @param EDX Upper 32-bits of MSR value.
2434 <b>Example usage</b>
2438 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
2439 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
2442 #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77
2446 Package. Uncore W-box perfmon local box control MSR.
2448 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
2449 @param EAX Lower 32-bits of MSR value.
2450 @param EDX Upper 32-bits of MSR value.
2452 <b>Example usage</b>
2456 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
2457 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
2460 #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80
2464 Package. Uncore W-box perfmon local box status MSR.
2466 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
2467 @param EAX Lower 32-bits of MSR value.
2468 @param EDX Upper 32-bits of MSR value.
2470 <b>Example usage</b>
2474 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
2475 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
2478 #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81
2482 Package. Uncore W-box perfmon local box overflow control MSR.
2484 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
2485 @param EAX Lower 32-bits of MSR value.
2486 @param EDX Upper 32-bits of MSR value.
2488 <b>Example usage</b>
2492 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
2493 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
2496 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82
2500 Package. Uncore W-box perfmon event select MSR.
2502 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
2503 @param EAX Lower 32-bits of MSR value.
2504 @param EDX Upper 32-bits of MSR value.
2506 <b>Example usage</b>
2510 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
2511 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
2514 #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90
2518 Package. Uncore W-box perfmon counter MSR.
2520 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
2521 @param EAX Lower 32-bits of MSR value.
2522 @param EDX Upper 32-bits of MSR value.
2524 <b>Example usage</b>
2528 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
2529 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
2532 #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91
2536 Package. Uncore W-box perfmon event select MSR.
2538 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
2539 @param EAX Lower 32-bits of MSR value.
2540 @param EDX Upper 32-bits of MSR value.
2542 <b>Example usage</b>
2546 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
2547 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
2550 #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92
2554 Package. Uncore W-box perfmon counter MSR.
2556 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
2557 @param EAX Lower 32-bits of MSR value.
2558 @param EDX Upper 32-bits of MSR value.
2560 <b>Example usage</b>
2564 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
2565 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
2568 #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93
2572 Package. Uncore W-box perfmon event select MSR.
2574 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
2575 @param EAX Lower 32-bits of MSR value.
2576 @param EDX Upper 32-bits of MSR value.
2578 <b>Example usage</b>
2582 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
2583 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
2586 #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94
2590 Package. Uncore W-box perfmon counter MSR.
2592 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
2593 @param EAX Lower 32-bits of MSR value.
2594 @param EDX Upper 32-bits of MSR value.
2596 <b>Example usage</b>
2600 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
2601 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
2604 #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95
2608 Package. Uncore W-box perfmon event select MSR.
2610 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
2611 @param EAX Lower 32-bits of MSR value.
2612 @param EDX Upper 32-bits of MSR value.
2614 <b>Example usage</b>
2618 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
2619 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
2622 #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96
2626 Package. Uncore W-box perfmon counter MSR.
2628 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
2629 @param EAX Lower 32-bits of MSR value.
2630 @param EDX Upper 32-bits of MSR value.
2632 <b>Example usage</b>
2636 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
2637 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
2640 #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97
2644 Package. Uncore M-box 0 perfmon local box control MSR.
2646 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
2647 @param EAX Lower 32-bits of MSR value.
2648 @param EDX Upper 32-bits of MSR value.
2650 <b>Example usage</b>
2654 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
2655 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
2658 #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0
2662 Package. Uncore M-box 0 perfmon local box status MSR.
2664 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
2665 @param EAX Lower 32-bits of MSR value.
2666 @param EDX Upper 32-bits of MSR value.
2668 <b>Example usage</b>
2672 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
2673 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
2676 #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1
2680 Package. Uncore M-box 0 perfmon local box overflow control MSR.
2682 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
2683 @param EAX Lower 32-bits of MSR value.
2684 @param EDX Upper 32-bits of MSR value.
2686 <b>Example usage</b>
2690 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
2691 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
2694 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2
2698 Package. Uncore M-box 0 perfmon time stamp unit select MSR.
2700 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
2701 @param EAX Lower 32-bits of MSR value.
2702 @param EDX Upper 32-bits of MSR value.
2704 <b>Example usage</b>
2708 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
2709 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
2712 #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4
2716 Package. Uncore M-box 0 perfmon DSP unit select MSR.
2718 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
2719 @param EAX Lower 32-bits of MSR value.
2720 @param EDX Upper 32-bits of MSR value.
2722 <b>Example usage</b>
2726 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
2727 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
2730 #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5
2734 Package. Uncore M-box 0 perfmon ISS unit select MSR.
2736 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
2737 @param EAX Lower 32-bits of MSR value.
2738 @param EDX Upper 32-bits of MSR value.
2740 <b>Example usage</b>
2744 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
2745 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
2748 #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6
2752 Package. Uncore M-box 0 perfmon MAP unit select MSR.
2754 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
2755 @param EAX Lower 32-bits of MSR value.
2756 @param EDX Upper 32-bits of MSR value.
2758 <b>Example usage</b>
2762 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
2763 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
2766 #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7
2770 Package. Uncore M-box 0 perfmon MIC THR select MSR.
2772 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
2773 @param EAX Lower 32-bits of MSR value.
2774 @param EDX Upper 32-bits of MSR value.
2776 <b>Example usage</b>
2780 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
2781 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
2784 #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8
2788 Package. Uncore M-box 0 perfmon PGT unit select MSR.
2790 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
2791 @param EAX Lower 32-bits of MSR value.
2792 @param EDX Upper 32-bits of MSR value.
2794 <b>Example usage</b>
2798 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
2799 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
2802 #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9
2806 Package. Uncore M-box 0 perfmon PLD unit select MSR.
2808 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
2809 @param EAX Lower 32-bits of MSR value.
2810 @param EDX Upper 32-bits of MSR value.
2812 <b>Example usage</b>
2816 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
2817 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
2820 #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA
2824 Package. Uncore M-box 0 perfmon ZDP unit select MSR.
2826 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
2827 @param EAX Lower 32-bits of MSR value.
2828 @param EDX Upper 32-bits of MSR value.
2830 <b>Example usage</b>
2834 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
2835 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
2838 #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB
2842 Package. Uncore M-box 0 perfmon event select MSR.
2844 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
2845 @param EAX Lower 32-bits of MSR value.
2846 @param EDX Upper 32-bits of MSR value.
2848 <b>Example usage</b>
2852 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
2853 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
2856 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0
2860 Package. Uncore M-box 0 perfmon counter MSR.
2862 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
2863 @param EAX Lower 32-bits of MSR value.
2864 @param EDX Upper 32-bits of MSR value.
2866 <b>Example usage</b>
2870 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
2871 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
2874 #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1
2878 Package. Uncore M-box 0 perfmon event select MSR.
2880 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
2881 @param EAX Lower 32-bits of MSR value.
2882 @param EDX Upper 32-bits of MSR value.
2884 <b>Example usage</b>
2888 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
2889 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
2892 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2
2896 Package. Uncore M-box 0 perfmon counter MSR.
2898 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
2899 @param EAX Lower 32-bits of MSR value.
2900 @param EDX Upper 32-bits of MSR value.
2902 <b>Example usage</b>
2906 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
2907 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
2910 #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3
2914 Package. Uncore M-box 0 perfmon event select MSR.
2916 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
2917 @param EAX Lower 32-bits of MSR value.
2918 @param EDX Upper 32-bits of MSR value.
2920 <b>Example usage</b>
2924 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
2925 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
2928 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4
2932 Package. Uncore M-box 0 perfmon counter MSR.
2934 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
2935 @param EAX Lower 32-bits of MSR value.
2936 @param EDX Upper 32-bits of MSR value.
2938 <b>Example usage</b>
2942 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
2943 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
2946 #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5
2950 Package. Uncore M-box 0 perfmon event select MSR.
2952 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
2953 @param EAX Lower 32-bits of MSR value.
2954 @param EDX Upper 32-bits of MSR value.
2956 <b>Example usage</b>
2960 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
2961 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
2964 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6
2968 Package. Uncore M-box 0 perfmon counter MSR.
2970 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
2971 @param EAX Lower 32-bits of MSR value.
2972 @param EDX Upper 32-bits of MSR value.
2974 <b>Example usage</b>
2978 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
2979 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
2982 #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7
2986 Package. Uncore M-box 0 perfmon event select MSR.
2988 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
2989 @param EAX Lower 32-bits of MSR value.
2990 @param EDX Upper 32-bits of MSR value.
2992 <b>Example usage</b>
2996 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
2997 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
3000 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8
3004 Package. Uncore M-box 0 perfmon counter MSR.
3006 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
3007 @param EAX Lower 32-bits of MSR value.
3008 @param EDX Upper 32-bits of MSR value.
3010 <b>Example usage</b>
3014 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
3015 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
3018 #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9
3022 Package. Uncore M-box 0 perfmon event select MSR.
3024 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
3025 @param EAX Lower 32-bits of MSR value.
3026 @param EDX Upper 32-bits of MSR value.
3028 <b>Example usage</b>
3032 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
3033 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
3036 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA
3040 Package. Uncore M-box 0 perfmon counter MSR.
3042 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
3043 @param EAX Lower 32-bits of MSR value.
3044 @param EDX Upper 32-bits of MSR value.
3046 <b>Example usage</b>
3050 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
3051 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
3054 #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB
3058 Package. Uncore S-box 1 perfmon local box control MSR.
3060 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
3061 @param EAX Lower 32-bits of MSR value.
3062 @param EDX Upper 32-bits of MSR value.
3064 <b>Example usage</b>
3068 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
3069 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
3072 #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0
3076 Package. Uncore S-box 1 perfmon local box status MSR.
3078 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
3079 @param EAX Lower 32-bits of MSR value.
3080 @param EDX Upper 32-bits of MSR value.
3082 <b>Example usage</b>
3086 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
3087 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
3090 #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1
3094 Package. Uncore S-box 1 perfmon local box overflow control MSR.
3096 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
3097 @param EAX Lower 32-bits of MSR value.
3098 @param EDX Upper 32-bits of MSR value.
3100 <b>Example usage</b>
3104 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
3105 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
3108 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2
3112 Package. Uncore S-box 1 perfmon event select MSR.
3114 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
3115 @param EAX Lower 32-bits of MSR value.
3116 @param EDX Upper 32-bits of MSR value.
3118 <b>Example usage</b>
3122 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
3123 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
3126 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0
3130 Package. Uncore S-box 1 perfmon counter MSR.
3132 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
3133 @param EAX Lower 32-bits of MSR value.
3134 @param EDX Upper 32-bits of MSR value.
3136 <b>Example usage</b>
3140 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
3141 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
3144 #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1
3148 Package. Uncore S-box 1 perfmon event select MSR.
3150 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
3151 @param EAX Lower 32-bits of MSR value.
3152 @param EDX Upper 32-bits of MSR value.
3154 <b>Example usage</b>
3158 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
3159 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
3162 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2
3166 Package. Uncore S-box 1 perfmon counter MSR.
3168 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
3169 @param EAX Lower 32-bits of MSR value.
3170 @param EDX Upper 32-bits of MSR value.
3172 <b>Example usage</b>
3176 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
3177 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
3180 #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3
3184 Package. Uncore S-box 1 perfmon event select MSR.
3186 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
3187 @param EAX Lower 32-bits of MSR value.
3188 @param EDX Upper 32-bits of MSR value.
3190 <b>Example usage</b>
3194 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
3195 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
3198 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4
3202 Package. Uncore S-box 1 perfmon counter MSR.
3204 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
3205 @param EAX Lower 32-bits of MSR value.
3206 @param EDX Upper 32-bits of MSR value.
3208 <b>Example usage</b>
3212 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
3213 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
3216 #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5
3220 Package. Uncore S-box 1 perfmon event select MSR.
3222 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
3223 @param EAX Lower 32-bits of MSR value.
3224 @param EDX Upper 32-bits of MSR value.
3226 <b>Example usage</b>
3230 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
3231 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
3234 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6
3238 Package. Uncore S-box 1 perfmon counter MSR.
3240 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
3241 @param EAX Lower 32-bits of MSR value.
3242 @param EDX Upper 32-bits of MSR value.
3244 <b>Example usage</b>
3248 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
3249 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
3252 #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7
3256 Package. Uncore M-box 1 perfmon local box control MSR.
3258 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
3259 @param EAX Lower 32-bits of MSR value.
3260 @param EDX Upper 32-bits of MSR value.
3262 <b>Example usage</b>
3266 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
3267 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
3270 #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0
3274 Package. Uncore M-box 1 perfmon local box status MSR.
3276 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
3277 @param EAX Lower 32-bits of MSR value.
3278 @param EDX Upper 32-bits of MSR value.
3280 <b>Example usage</b>
3284 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
3285 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
3288 #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1
3292 Package. Uncore M-box 1 perfmon local box overflow control MSR.
3294 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
3295 @param EAX Lower 32-bits of MSR value.
3296 @param EDX Upper 32-bits of MSR value.
3298 <b>Example usage</b>
3302 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
3303 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
3306 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2
3310 Package. Uncore M-box 1 perfmon time stamp unit select MSR.
3312 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
3313 @param EAX Lower 32-bits of MSR value.
3314 @param EDX Upper 32-bits of MSR value.
3316 <b>Example usage</b>
3320 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
3321 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
3324 #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4
3328 Package. Uncore M-box 1 perfmon DSP unit select MSR.
3330 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
3331 @param EAX Lower 32-bits of MSR value.
3332 @param EDX Upper 32-bits of MSR value.
3334 <b>Example usage</b>
3338 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
3339 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
3342 #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5
3346 Package. Uncore M-box 1 perfmon ISS unit select MSR.
3348 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
3349 @param EAX Lower 32-bits of MSR value.
3350 @param EDX Upper 32-bits of MSR value.
3352 <b>Example usage</b>
3356 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
3357 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
3360 #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6
3364 Package. Uncore M-box 1 perfmon MAP unit select MSR.
3366 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
3367 @param EAX Lower 32-bits of MSR value.
3368 @param EDX Upper 32-bits of MSR value.
3370 <b>Example usage</b>
3374 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
3375 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
3378 #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7
3382 Package. Uncore M-box 1 perfmon MIC THR select MSR.
3384 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
3385 @param EAX Lower 32-bits of MSR value.
3386 @param EDX Upper 32-bits of MSR value.
3388 <b>Example usage</b>
3392 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
3393 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
3396 #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8
3400 Package. Uncore M-box 1 perfmon PGT unit select MSR.
3402 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
3403 @param EAX Lower 32-bits of MSR value.
3404 @param EDX Upper 32-bits of MSR value.
3406 <b>Example usage</b>
3410 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
3411 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
3414 #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9
3418 Package. Uncore M-box 1 perfmon PLD unit select MSR.
3420 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
3421 @param EAX Lower 32-bits of MSR value.
3422 @param EDX Upper 32-bits of MSR value.
3424 <b>Example usage</b>
3428 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
3429 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
3432 #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA
3436 Package. Uncore M-box 1 perfmon ZDP unit select MSR.
3438 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
3439 @param EAX Lower 32-bits of MSR value.
3440 @param EDX Upper 32-bits of MSR value.
3442 <b>Example usage</b>
3446 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
3447 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
3450 #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB
3454 Package. Uncore M-box 1 perfmon event select MSR.
3456 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
3457 @param EAX Lower 32-bits of MSR value.
3458 @param EDX Upper 32-bits of MSR value.
3460 <b>Example usage</b>
3464 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
3465 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
3468 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0
3472 Package. Uncore M-box 1 perfmon counter MSR.
3474 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
3475 @param EAX Lower 32-bits of MSR value.
3476 @param EDX Upper 32-bits of MSR value.
3478 <b>Example usage</b>
3482 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
3483 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
3486 #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1
3490 Package. Uncore M-box 1 perfmon event select MSR.
3492 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
3493 @param EAX Lower 32-bits of MSR value.
3494 @param EDX Upper 32-bits of MSR value.
3496 <b>Example usage</b>
3500 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
3501 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
3504 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2
3508 Package. Uncore M-box 1 perfmon counter MSR.
3510 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
3511 @param EAX Lower 32-bits of MSR value.
3512 @param EDX Upper 32-bits of MSR value.
3514 <b>Example usage</b>
3518 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
3519 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
3522 #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3
3526 Package. Uncore M-box 1 perfmon event select MSR.
3528 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
3529 @param EAX Lower 32-bits of MSR value.
3530 @param EDX Upper 32-bits of MSR value.
3532 <b>Example usage</b>
3536 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
3537 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
3540 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4
3544 Package. Uncore M-box 1 perfmon counter MSR.
3546 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
3547 @param EAX Lower 32-bits of MSR value.
3548 @param EDX Upper 32-bits of MSR value.
3550 <b>Example usage</b>
3554 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
3555 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
3558 #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5
3562 Package. Uncore M-box 1 perfmon event select MSR.
3564 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
3565 @param EAX Lower 32-bits of MSR value.
3566 @param EDX Upper 32-bits of MSR value.
3568 <b>Example usage</b>
3572 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
3573 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
3576 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6
3580 Package. Uncore M-box 1 perfmon counter MSR.
3582 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
3583 @param EAX Lower 32-bits of MSR value.
3584 @param EDX Upper 32-bits of MSR value.
3586 <b>Example usage</b>
3590 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
3591 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
3594 #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7
3598 Package. Uncore M-box 1 perfmon event select MSR.
3600 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
3601 @param EAX Lower 32-bits of MSR value.
3602 @param EDX Upper 32-bits of MSR value.
3604 <b>Example usage</b>
3608 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
3609 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
3612 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8
3616 Package. Uncore M-box 1 perfmon counter MSR.
3618 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
3619 @param EAX Lower 32-bits of MSR value.
3620 @param EDX Upper 32-bits of MSR value.
3622 <b>Example usage</b>
3626 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
3627 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
3630 #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9
3634 Package. Uncore M-box 1 perfmon event select MSR.
3636 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
3637 @param EAX Lower 32-bits of MSR value.
3638 @param EDX Upper 32-bits of MSR value.
3640 <b>Example usage</b>
3644 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
3645 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
3648 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA
3652 Package. Uncore M-box 1 perfmon counter MSR.
3654 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
3655 @param EAX Lower 32-bits of MSR value.
3656 @param EDX Upper 32-bits of MSR value.
3658 <b>Example usage</b>
3662 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
3663 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
3666 #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB
3670 Package. Uncore C-box 0 perfmon local box control MSR.
3672 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
3673 @param EAX Lower 32-bits of MSR value.
3674 @param EDX Upper 32-bits of MSR value.
3676 <b>Example usage</b>
3680 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
3681 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
3684 #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00
3688 Package. Uncore C-box 0 perfmon local box status MSR.
3690 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
3691 @param EAX Lower 32-bits of MSR value.
3692 @param EDX Upper 32-bits of MSR value.
3694 <b>Example usage</b>
3698 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
3699 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
3702 #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01
3706 Package. Uncore C-box 0 perfmon local box overflow control MSR.
3708 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
3709 @param EAX Lower 32-bits of MSR value.
3710 @param EDX Upper 32-bits of MSR value.
3712 <b>Example usage</b>
3716 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
3717 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
3720 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02
3724 Package. Uncore C-box 0 perfmon event select MSR.
3726 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
3727 @param EAX Lower 32-bits of MSR value.
3728 @param EDX Upper 32-bits of MSR value.
3730 <b>Example usage</b>
3734 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
3735 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
3738 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10
3742 Package. Uncore C-box 0 perfmon counter MSR.
3744 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
3745 @param EAX Lower 32-bits of MSR value.
3746 @param EDX Upper 32-bits of MSR value.
3748 <b>Example usage</b>
3752 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
3753 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
3756 #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11
3760 Package. Uncore C-box 0 perfmon event select MSR.
3762 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
3763 @param EAX Lower 32-bits of MSR value.
3764 @param EDX Upper 32-bits of MSR value.
3766 <b>Example usage</b>
3770 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
3771 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
3774 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12
3778 Package. Uncore C-box 0 perfmon counter MSR.
3780 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
3781 @param EAX Lower 32-bits of MSR value.
3782 @param EDX Upper 32-bits of MSR value.
3784 <b>Example usage</b>
3788 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
3789 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
3792 #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13
3796 Package. Uncore C-box 0 perfmon event select MSR.
3798 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
3799 @param EAX Lower 32-bits of MSR value.
3800 @param EDX Upper 32-bits of MSR value.
3802 <b>Example usage</b>
3806 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
3807 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
3810 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14
3814 Package. Uncore C-box 0 perfmon counter MSR.
3816 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
3817 @param EAX Lower 32-bits of MSR value.
3818 @param EDX Upper 32-bits of MSR value.
3820 <b>Example usage</b>
3824 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
3825 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
3828 #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15
3832 Package. Uncore C-box 0 perfmon event select MSR.
3834 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
3835 @param EAX Lower 32-bits of MSR value.
3836 @param EDX Upper 32-bits of MSR value.
3838 <b>Example usage</b>
3842 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
3843 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
3846 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16
3850 Package. Uncore C-box 0 perfmon counter MSR.
3852 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
3853 @param EAX Lower 32-bits of MSR value.
3854 @param EDX Upper 32-bits of MSR value.
3856 <b>Example usage</b>
3860 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
3861 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
3864 #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17
3868 Package. Uncore C-box 0 perfmon event select MSR.
3870 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
3871 @param EAX Lower 32-bits of MSR value.
3872 @param EDX Upper 32-bits of MSR value.
3874 <b>Example usage</b>
3878 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
3879 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
3882 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18
3886 Package. Uncore C-box 0 perfmon counter MSR.
3888 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
3889 @param EAX Lower 32-bits of MSR value.
3890 @param EDX Upper 32-bits of MSR value.
3892 <b>Example usage</b>
3896 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
3897 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
3900 #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19
3904 Package. Uncore C-box 0 perfmon event select MSR.
3906 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
3907 @param EAX Lower 32-bits of MSR value.
3908 @param EDX Upper 32-bits of MSR value.
3910 <b>Example usage</b>
3914 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
3915 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
3918 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A
3922 Package. Uncore C-box 0 perfmon counter MSR.
3924 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
3925 @param EAX Lower 32-bits of MSR value.
3926 @param EDX Upper 32-bits of MSR value.
3928 <b>Example usage</b>
3932 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
3933 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
3936 #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B
3940 Package. Uncore C-box 4 perfmon local box control MSR.
3942 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
3943 @param EAX Lower 32-bits of MSR value.
3944 @param EDX Upper 32-bits of MSR value.
3946 <b>Example usage</b>
3950 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
3951 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
3954 #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20
3958 Package. Uncore C-box 4 perfmon local box status MSR.
3960 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
3961 @param EAX Lower 32-bits of MSR value.
3962 @param EDX Upper 32-bits of MSR value.
3964 <b>Example usage</b>
3968 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
3969 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
3972 #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21
3976 Package. Uncore C-box 4 perfmon local box overflow control MSR.
3978 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
3979 @param EAX Lower 32-bits of MSR value.
3980 @param EDX Upper 32-bits of MSR value.
3982 <b>Example usage</b>
3986 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
3987 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
3990 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22
3994 Package. Uncore C-box 4 perfmon event select MSR.
3996 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
3997 @param EAX Lower 32-bits of MSR value.
3998 @param EDX Upper 32-bits of MSR value.
4000 <b>Example usage</b>
4004 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
4005 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
4008 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30
4012 Package. Uncore C-box 4 perfmon counter MSR.
4014 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
4015 @param EAX Lower 32-bits of MSR value.
4016 @param EDX Upper 32-bits of MSR value.
4018 <b>Example usage</b>
4022 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
4023 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
4026 #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31
4030 Package. Uncore C-box 4 perfmon event select MSR.
4032 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
4033 @param EAX Lower 32-bits of MSR value.
4034 @param EDX Upper 32-bits of MSR value.
4036 <b>Example usage</b>
4040 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
4041 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
4044 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32
4048 Package. Uncore C-box 4 perfmon counter MSR.
4050 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
4051 @param EAX Lower 32-bits of MSR value.
4052 @param EDX Upper 32-bits of MSR value.
4054 <b>Example usage</b>
4058 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
4059 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
4062 #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33
4066 Package. Uncore C-box 4 perfmon event select MSR.
4068 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
4069 @param EAX Lower 32-bits of MSR value.
4070 @param EDX Upper 32-bits of MSR value.
4072 <b>Example usage</b>
4076 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
4077 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
4080 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34
4084 Package. Uncore C-box 4 perfmon counter MSR.
4086 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
4087 @param EAX Lower 32-bits of MSR value.
4088 @param EDX Upper 32-bits of MSR value.
4090 <b>Example usage</b>
4094 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
4095 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
4098 #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35
4102 Package. Uncore C-box 4 perfmon event select MSR.
4104 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
4105 @param EAX Lower 32-bits of MSR value.
4106 @param EDX Upper 32-bits of MSR value.
4108 <b>Example usage</b>
4112 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
4113 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
4116 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36
4120 Package. Uncore C-box 4 perfmon counter MSR.
4122 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
4123 @param EAX Lower 32-bits of MSR value.
4124 @param EDX Upper 32-bits of MSR value.
4126 <b>Example usage</b>
4130 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
4131 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
4134 #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37
4138 Package. Uncore C-box 4 perfmon event select MSR.
4140 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
4141 @param EAX Lower 32-bits of MSR value.
4142 @param EDX Upper 32-bits of MSR value.
4144 <b>Example usage</b>
4148 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
4149 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
4152 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38
4156 Package. Uncore C-box 4 perfmon counter MSR.
4158 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
4159 @param EAX Lower 32-bits of MSR value.
4160 @param EDX Upper 32-bits of MSR value.
4162 <b>Example usage</b>
4166 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
4167 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
4170 #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39
4174 Package. Uncore C-box 4 perfmon event select MSR.
4176 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
4177 @param EAX Lower 32-bits of MSR value.
4178 @param EDX Upper 32-bits of MSR value.
4180 <b>Example usage</b>
4184 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
4185 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
4188 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A
4192 Package. Uncore C-box 4 perfmon counter MSR.
4194 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
4195 @param EAX Lower 32-bits of MSR value.
4196 @param EDX Upper 32-bits of MSR value.
4198 <b>Example usage</b>
4202 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
4203 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
4206 #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B
4210 Package. Uncore C-box 2 perfmon local box control MSR.
4212 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
4213 @param EAX Lower 32-bits of MSR value.
4214 @param EDX Upper 32-bits of MSR value.
4216 <b>Example usage</b>
4220 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
4221 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
4224 #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40
4228 Package. Uncore C-box 2 perfmon local box status MSR.
4230 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
4231 @param EAX Lower 32-bits of MSR value.
4232 @param EDX Upper 32-bits of MSR value.
4234 <b>Example usage</b>
4238 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
4239 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
4242 #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41
4246 Package. Uncore C-box 2 perfmon local box overflow control MSR.
4248 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
4249 @param EAX Lower 32-bits of MSR value.
4250 @param EDX Upper 32-bits of MSR value.
4252 <b>Example usage</b>
4256 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
4257 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
4260 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42
4264 Package. Uncore C-box 2 perfmon event select MSR.
4266 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
4267 @param EAX Lower 32-bits of MSR value.
4268 @param EDX Upper 32-bits of MSR value.
4270 <b>Example usage</b>
4274 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
4275 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
4278 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50
4282 Package. Uncore C-box 2 perfmon counter MSR.
4284 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
4285 @param EAX Lower 32-bits of MSR value.
4286 @param EDX Upper 32-bits of MSR value.
4288 <b>Example usage</b>
4292 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
4293 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
4296 #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51
4300 Package. Uncore C-box 2 perfmon event select MSR.
4302 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
4303 @param EAX Lower 32-bits of MSR value.
4304 @param EDX Upper 32-bits of MSR value.
4306 <b>Example usage</b>
4310 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
4311 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
4314 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52
4318 Package. Uncore C-box 2 perfmon counter MSR.
4320 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
4321 @param EAX Lower 32-bits of MSR value.
4322 @param EDX Upper 32-bits of MSR value.
4324 <b>Example usage</b>
4328 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
4329 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
4332 #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53
4336 Package. Uncore C-box 2 perfmon event select MSR.
4338 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
4339 @param EAX Lower 32-bits of MSR value.
4340 @param EDX Upper 32-bits of MSR value.
4342 <b>Example usage</b>
4346 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
4347 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
4350 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54
4354 Package. Uncore C-box 2 perfmon counter MSR.
4356 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
4357 @param EAX Lower 32-bits of MSR value.
4358 @param EDX Upper 32-bits of MSR value.
4360 <b>Example usage</b>
4364 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
4365 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
4368 #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55
4372 Package. Uncore C-box 2 perfmon event select MSR.
4374 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
4375 @param EAX Lower 32-bits of MSR value.
4376 @param EDX Upper 32-bits of MSR value.
4378 <b>Example usage</b>
4382 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
4383 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
4386 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56
4390 Package. Uncore C-box 2 perfmon counter MSR.
4392 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
4393 @param EAX Lower 32-bits of MSR value.
4394 @param EDX Upper 32-bits of MSR value.
4396 <b>Example usage</b>
4400 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
4401 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
4404 #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57
4408 Package. Uncore C-box 2 perfmon event select MSR.
4410 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
4411 @param EAX Lower 32-bits of MSR value.
4412 @param EDX Upper 32-bits of MSR value.
4414 <b>Example usage</b>
4418 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
4419 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
4422 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58
4426 Package. Uncore C-box 2 perfmon counter MSR.
4428 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
4429 @param EAX Lower 32-bits of MSR value.
4430 @param EDX Upper 32-bits of MSR value.
4432 <b>Example usage</b>
4436 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
4437 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
4440 #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59
4444 Package. Uncore C-box 2 perfmon event select MSR.
4446 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
4447 @param EAX Lower 32-bits of MSR value.
4448 @param EDX Upper 32-bits of MSR value.
4450 <b>Example usage</b>
4454 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
4455 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
4458 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A
4462 Package. Uncore C-box 2 perfmon counter MSR.
4464 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
4465 @param EAX Lower 32-bits of MSR value.
4466 @param EDX Upper 32-bits of MSR value.
4468 <b>Example usage</b>
4472 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
4473 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
4476 #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B
4480 Package. Uncore C-box 6 perfmon local box control MSR.
4482 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
4483 @param EAX Lower 32-bits of MSR value.
4484 @param EDX Upper 32-bits of MSR value.
4486 <b>Example usage</b>
4490 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
4491 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
4494 #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60
4498 Package. Uncore C-box 6 perfmon local box status MSR.
4500 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
4501 @param EAX Lower 32-bits of MSR value.
4502 @param EDX Upper 32-bits of MSR value.
4504 <b>Example usage</b>
4508 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
4509 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
4512 #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61
4516 Package. Uncore C-box 6 perfmon local box overflow control MSR.
4518 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
4519 @param EAX Lower 32-bits of MSR value.
4520 @param EDX Upper 32-bits of MSR value.
4522 <b>Example usage</b>
4526 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
4527 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
4530 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62
4534 Package. Uncore C-box 6 perfmon event select MSR.
4536 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
4537 @param EAX Lower 32-bits of MSR value.
4538 @param EDX Upper 32-bits of MSR value.
4540 <b>Example usage</b>
4544 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
4545 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
4548 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70
4552 Package. Uncore C-box 6 perfmon counter MSR.
4554 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
4555 @param EAX Lower 32-bits of MSR value.
4556 @param EDX Upper 32-bits of MSR value.
4558 <b>Example usage</b>
4562 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
4563 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
4566 #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71
4570 Package. Uncore C-box 6 perfmon event select MSR.
4572 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
4573 @param EAX Lower 32-bits of MSR value.
4574 @param EDX Upper 32-bits of MSR value.
4576 <b>Example usage</b>
4580 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
4581 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
4584 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72
4588 Package. Uncore C-box 6 perfmon counter MSR.
4590 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
4591 @param EAX Lower 32-bits of MSR value.
4592 @param EDX Upper 32-bits of MSR value.
4594 <b>Example usage</b>
4598 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
4599 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
4602 #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73
4606 Package. Uncore C-box 6 perfmon event select MSR.
4608 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
4609 @param EAX Lower 32-bits of MSR value.
4610 @param EDX Upper 32-bits of MSR value.
4612 <b>Example usage</b>
4616 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
4617 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
4620 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74
4624 Package. Uncore C-box 6 perfmon counter MSR.
4626 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
4627 @param EAX Lower 32-bits of MSR value.
4628 @param EDX Upper 32-bits of MSR value.
4630 <b>Example usage</b>
4634 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
4635 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
4638 #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75
4642 Package. Uncore C-box 6 perfmon event select MSR.
4644 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
4645 @param EAX Lower 32-bits of MSR value.
4646 @param EDX Upper 32-bits of MSR value.
4648 <b>Example usage</b>
4652 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
4653 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
4656 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76
4660 Package. Uncore C-box 6 perfmon counter MSR.
4662 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
4663 @param EAX Lower 32-bits of MSR value.
4664 @param EDX Upper 32-bits of MSR value.
4666 <b>Example usage</b>
4670 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
4671 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
4674 #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77
4678 Package. Uncore C-box 6 perfmon event select MSR.
4680 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
4681 @param EAX Lower 32-bits of MSR value.
4682 @param EDX Upper 32-bits of MSR value.
4684 <b>Example usage</b>
4688 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
4689 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
4692 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78
4696 Package. Uncore C-box 6 perfmon counter MSR.
4698 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
4699 @param EAX Lower 32-bits of MSR value.
4700 @param EDX Upper 32-bits of MSR value.
4702 <b>Example usage</b>
4706 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
4707 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
4710 #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79
4714 Package. Uncore C-box 6 perfmon event select MSR.
4716 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
4717 @param EAX Lower 32-bits of MSR value.
4718 @param EDX Upper 32-bits of MSR value.
4720 <b>Example usage</b>
4724 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
4725 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
4728 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A
4732 Package. Uncore C-box 6 perfmon counter MSR.
4734 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
4735 @param EAX Lower 32-bits of MSR value.
4736 @param EDX Upper 32-bits of MSR value.
4738 <b>Example usage</b>
4742 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
4743 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
4746 #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B
4750 Package. Uncore C-box 1 perfmon local box control MSR.
4752 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
4753 @param EAX Lower 32-bits of MSR value.
4754 @param EDX Upper 32-bits of MSR value.
4756 <b>Example usage</b>
4760 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
4761 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
4764 #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80
4768 Package. Uncore C-box 1 perfmon local box status MSR.
4770 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
4771 @param EAX Lower 32-bits of MSR value.
4772 @param EDX Upper 32-bits of MSR value.
4774 <b>Example usage</b>
4778 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
4779 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
4782 #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81
4786 Package. Uncore C-box 1 perfmon local box overflow control MSR.
4788 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
4789 @param EAX Lower 32-bits of MSR value.
4790 @param EDX Upper 32-bits of MSR value.
4792 <b>Example usage</b>
4796 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
4797 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
4800 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82
4804 Package. Uncore C-box 1 perfmon event select MSR.
4806 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
4807 @param EAX Lower 32-bits of MSR value.
4808 @param EDX Upper 32-bits of MSR value.
4810 <b>Example usage</b>
4814 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
4815 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
4818 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90
4822 Package. Uncore C-box 1 perfmon counter MSR.
4824 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
4825 @param EAX Lower 32-bits of MSR value.
4826 @param EDX Upper 32-bits of MSR value.
4828 <b>Example usage</b>
4832 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
4833 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
4836 #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91
4840 Package. Uncore C-box 1 perfmon event select MSR.
4842 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
4843 @param EAX Lower 32-bits of MSR value.
4844 @param EDX Upper 32-bits of MSR value.
4846 <b>Example usage</b>
4850 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
4851 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
4854 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92
4858 Package. Uncore C-box 1 perfmon counter MSR.
4860 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
4861 @param EAX Lower 32-bits of MSR value.
4862 @param EDX Upper 32-bits of MSR value.
4864 <b>Example usage</b>
4868 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
4869 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
4872 #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93
4876 Package. Uncore C-box 1 perfmon event select MSR.
4878 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
4879 @param EAX Lower 32-bits of MSR value.
4880 @param EDX Upper 32-bits of MSR value.
4882 <b>Example usage</b>
4886 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
4887 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
4890 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94
4894 Package. Uncore C-box 1 perfmon counter MSR.
4896 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
4897 @param EAX Lower 32-bits of MSR value.
4898 @param EDX Upper 32-bits of MSR value.
4900 <b>Example usage</b>
4904 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
4905 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
4908 #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95
4912 Package. Uncore C-box 1 perfmon event select MSR.
4914 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
4915 @param EAX Lower 32-bits of MSR value.
4916 @param EDX Upper 32-bits of MSR value.
4918 <b>Example usage</b>
4922 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
4923 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
4926 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96
4930 Package. Uncore C-box 1 perfmon counter MSR.
4932 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
4933 @param EAX Lower 32-bits of MSR value.
4934 @param EDX Upper 32-bits of MSR value.
4936 <b>Example usage</b>
4940 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
4941 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
4944 #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97
4948 Package. Uncore C-box 1 perfmon event select MSR.
4950 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
4951 @param EAX Lower 32-bits of MSR value.
4952 @param EDX Upper 32-bits of MSR value.
4954 <b>Example usage</b>
4958 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
4959 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
4962 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98
4966 Package. Uncore C-box 1 perfmon counter MSR.
4968 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
4969 @param EAX Lower 32-bits of MSR value.
4970 @param EDX Upper 32-bits of MSR value.
4972 <b>Example usage</b>
4976 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
4977 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
4980 #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99
4984 Package. Uncore C-box 1 perfmon event select MSR.
4986 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
4987 @param EAX Lower 32-bits of MSR value.
4988 @param EDX Upper 32-bits of MSR value.
4990 <b>Example usage</b>
4994 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
4995 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
4998 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A
5002 Package. Uncore C-box 1 perfmon counter MSR.
5004 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
5005 @param EAX Lower 32-bits of MSR value.
5006 @param EDX Upper 32-bits of MSR value.
5008 <b>Example usage</b>
5012 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
5013 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
5016 #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B
5020 Package. Uncore C-box 5 perfmon local box control MSR.
5022 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
5023 @param EAX Lower 32-bits of MSR value.
5024 @param EDX Upper 32-bits of MSR value.
5026 <b>Example usage</b>
5030 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
5031 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
5034 #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0
5038 Package. Uncore C-box 5 perfmon local box status MSR.
5040 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
5041 @param EAX Lower 32-bits of MSR value.
5042 @param EDX Upper 32-bits of MSR value.
5044 <b>Example usage</b>
5048 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
5049 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
5052 #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1
5056 Package. Uncore C-box 5 perfmon local box overflow control MSR.
5058 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
5059 @param EAX Lower 32-bits of MSR value.
5060 @param EDX Upper 32-bits of MSR value.
5062 <b>Example usage</b>
5066 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
5067 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
5070 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2
5074 Package. Uncore C-box 5 perfmon event select MSR.
5076 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
5077 @param EAX Lower 32-bits of MSR value.
5078 @param EDX Upper 32-bits of MSR value.
5080 <b>Example usage</b>
5084 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
5085 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
5088 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0
5092 Package. Uncore C-box 5 perfmon counter MSR.
5094 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
5095 @param EAX Lower 32-bits of MSR value.
5096 @param EDX Upper 32-bits of MSR value.
5098 <b>Example usage</b>
5102 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
5103 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
5106 #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1
5110 Package. Uncore C-box 5 perfmon event select MSR.
5112 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
5113 @param EAX Lower 32-bits of MSR value.
5114 @param EDX Upper 32-bits of MSR value.
5116 <b>Example usage</b>
5120 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
5121 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
5124 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2
5128 Package. Uncore C-box 5 perfmon counter MSR.
5130 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
5131 @param EAX Lower 32-bits of MSR value.
5132 @param EDX Upper 32-bits of MSR value.
5134 <b>Example usage</b>
5138 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
5139 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
5142 #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3
5146 Package. Uncore C-box 5 perfmon event select MSR.
5148 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
5149 @param EAX Lower 32-bits of MSR value.
5150 @param EDX Upper 32-bits of MSR value.
5152 <b>Example usage</b>
5156 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
5157 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
5160 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4
5164 Package. Uncore C-box 5 perfmon counter MSR.
5166 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
5167 @param EAX Lower 32-bits of MSR value.
5168 @param EDX Upper 32-bits of MSR value.
5170 <b>Example usage</b>
5174 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
5175 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
5178 #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5
5182 Package. Uncore C-box 5 perfmon event select MSR.
5184 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
5185 @param EAX Lower 32-bits of MSR value.
5186 @param EDX Upper 32-bits of MSR value.
5188 <b>Example usage</b>
5192 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
5193 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
5196 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6
5200 Package. Uncore C-box 5 perfmon counter MSR.
5202 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
5203 @param EAX Lower 32-bits of MSR value.
5204 @param EDX Upper 32-bits of MSR value.
5206 <b>Example usage</b>
5210 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
5211 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
5214 #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7
5218 Package. Uncore C-box 5 perfmon event select MSR.
5220 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
5221 @param EAX Lower 32-bits of MSR value.
5222 @param EDX Upper 32-bits of MSR value.
5224 <b>Example usage</b>
5228 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
5229 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
5232 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8
5236 Package. Uncore C-box 5 perfmon counter MSR.
5238 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
5239 @param EAX Lower 32-bits of MSR value.
5240 @param EDX Upper 32-bits of MSR value.
5242 <b>Example usage</b>
5246 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
5247 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
5250 #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9
5254 Package. Uncore C-box 5 perfmon event select MSR.
5256 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
5257 @param EAX Lower 32-bits of MSR value.
5258 @param EDX Upper 32-bits of MSR value.
5260 <b>Example usage</b>
5264 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
5265 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
5268 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA
5272 Package. Uncore C-box 5 perfmon counter MSR.
5274 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
5275 @param EAX Lower 32-bits of MSR value.
5276 @param EDX Upper 32-bits of MSR value.
5278 <b>Example usage</b>
5282 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
5283 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
5286 #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB
5290 Package. Uncore C-box 3 perfmon local box control MSR.
5292 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
5293 @param EAX Lower 32-bits of MSR value.
5294 @param EDX Upper 32-bits of MSR value.
5296 <b>Example usage</b>
5300 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
5301 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
5304 #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0
5308 Package. Uncore C-box 3 perfmon local box status MSR.
5310 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
5311 @param EAX Lower 32-bits of MSR value.
5312 @param EDX Upper 32-bits of MSR value.
5314 <b>Example usage</b>
5318 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
5319 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
5322 #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1
5326 Package. Uncore C-box 3 perfmon local box overflow control MSR.
5328 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
5329 @param EAX Lower 32-bits of MSR value.
5330 @param EDX Upper 32-bits of MSR value.
5332 <b>Example usage</b>
5336 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
5337 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
5340 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2
5344 Package. Uncore C-box 3 perfmon event select MSR.
5346 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
5347 @param EAX Lower 32-bits of MSR value.
5348 @param EDX Upper 32-bits of MSR value.
5350 <b>Example usage</b>
5354 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
5355 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
5358 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0
5362 Package. Uncore C-box 3 perfmon counter MSR.
5364 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
5365 @param EAX Lower 32-bits of MSR value.
5366 @param EDX Upper 32-bits of MSR value.
5368 <b>Example usage</b>
5372 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
5373 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
5376 #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1
5380 Package. Uncore C-box 3 perfmon event select MSR.
5382 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
5383 @param EAX Lower 32-bits of MSR value.
5384 @param EDX Upper 32-bits of MSR value.
5386 <b>Example usage</b>
5390 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
5391 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
5394 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2
5398 Package. Uncore C-box 3 perfmon counter MSR.
5400 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
5401 @param EAX Lower 32-bits of MSR value.
5402 @param EDX Upper 32-bits of MSR value.
5404 <b>Example usage</b>
5408 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
5409 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
5412 #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3
5416 Package. Uncore C-box 3 perfmon event select MSR.
5418 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
5419 @param EAX Lower 32-bits of MSR value.
5420 @param EDX Upper 32-bits of MSR value.
5422 <b>Example usage</b>
5426 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
5427 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
5430 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4
5434 Package. Uncore C-box 3 perfmon counter MSR.
5436 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
5437 @param EAX Lower 32-bits of MSR value.
5438 @param EDX Upper 32-bits of MSR value.
5440 <b>Example usage</b>
5444 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
5445 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
5448 #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5
5452 Package. Uncore C-box 3 perfmon event select MSR.
5454 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
5455 @param EAX Lower 32-bits of MSR value.
5456 @param EDX Upper 32-bits of MSR value.
5458 <b>Example usage</b>
5462 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
5463 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
5466 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6
5470 Package. Uncore C-box 3 perfmon counter MSR.
5472 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
5473 @param EAX Lower 32-bits of MSR value.
5474 @param EDX Upper 32-bits of MSR value.
5476 <b>Example usage</b>
5480 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
5481 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
5484 #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7
5488 Package. Uncore C-box 3 perfmon event select MSR.
5490 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
5491 @param EAX Lower 32-bits of MSR value.
5492 @param EDX Upper 32-bits of MSR value.
5494 <b>Example usage</b>
5498 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
5499 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
5502 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8
5506 Package. Uncore C-box 3 perfmon counter MSR.
5508 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
5509 @param EAX Lower 32-bits of MSR value.
5510 @param EDX Upper 32-bits of MSR value.
5512 <b>Example usage</b>
5516 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
5517 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
5520 #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9
5524 Package. Uncore C-box 3 perfmon event select MSR.
5526 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
5527 @param EAX Lower 32-bits of MSR value.
5528 @param EDX Upper 32-bits of MSR value.
5530 <b>Example usage</b>
5534 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
5535 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
5538 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA
5542 Package. Uncore C-box 3 perfmon counter MSR.
5544 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
5545 @param EAX Lower 32-bits of MSR value.
5546 @param EDX Upper 32-bits of MSR value.
5548 <b>Example usage</b>
5552 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
5553 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
5556 #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB
5560 Package. Uncore C-box 7 perfmon local box control MSR.
5562 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
5563 @param EAX Lower 32-bits of MSR value.
5564 @param EDX Upper 32-bits of MSR value.
5566 <b>Example usage</b>
5570 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
5571 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
5574 #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0
5578 Package. Uncore C-box 7 perfmon local box status MSR.
5580 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
5581 @param EAX Lower 32-bits of MSR value.
5582 @param EDX Upper 32-bits of MSR value.
5584 <b>Example usage</b>
5588 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
5589 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
5592 #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1
5596 Package. Uncore C-box 7 perfmon local box overflow control MSR.
5598 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
5599 @param EAX Lower 32-bits of MSR value.
5600 @param EDX Upper 32-bits of MSR value.
5602 <b>Example usage</b>
5606 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
5607 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
5610 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2
5614 Package. Uncore C-box 7 perfmon event select MSR.
5616 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
5617 @param EAX Lower 32-bits of MSR value.
5618 @param EDX Upper 32-bits of MSR value.
5620 <b>Example usage</b>
5624 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
5625 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
5628 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0
5632 Package. Uncore C-box 7 perfmon counter MSR.
5634 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
5635 @param EAX Lower 32-bits of MSR value.
5636 @param EDX Upper 32-bits of MSR value.
5638 <b>Example usage</b>
5642 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
5643 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
5646 #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1
5650 Package. Uncore C-box 7 perfmon event select MSR.
5652 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
5653 @param EAX Lower 32-bits of MSR value.
5654 @param EDX Upper 32-bits of MSR value.
5656 <b>Example usage</b>
5660 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
5661 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
5664 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2
5668 Package. Uncore C-box 7 perfmon counter MSR.
5670 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
5671 @param EAX Lower 32-bits of MSR value.
5672 @param EDX Upper 32-bits of MSR value.
5674 <b>Example usage</b>
5678 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
5679 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
5682 #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3
5686 Package. Uncore C-box 7 perfmon event select MSR.
5688 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
5689 @param EAX Lower 32-bits of MSR value.
5690 @param EDX Upper 32-bits of MSR value.
5692 <b>Example usage</b>
5696 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
5697 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
5700 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4
5704 Package. Uncore C-box 7 perfmon counter MSR.
5706 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
5707 @param EAX Lower 32-bits of MSR value.
5708 @param EDX Upper 32-bits of MSR value.
5710 <b>Example usage</b>
5714 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
5715 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
5718 #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5
5722 Package. Uncore C-box 7 perfmon event select MSR.
5724 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
5725 @param EAX Lower 32-bits of MSR value.
5726 @param EDX Upper 32-bits of MSR value.
5728 <b>Example usage</b>
5732 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
5733 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
5736 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6
5740 Package. Uncore C-box 7 perfmon counter MSR.
5742 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
5743 @param EAX Lower 32-bits of MSR value.
5744 @param EDX Upper 32-bits of MSR value.
5746 <b>Example usage</b>
5750 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
5751 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
5754 #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7
5758 Package. Uncore C-box 7 perfmon event select MSR.
5760 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
5761 @param EAX Lower 32-bits of MSR value.
5762 @param EDX Upper 32-bits of MSR value.
5764 <b>Example usage</b>
5768 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
5769 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
5772 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8
5776 Package. Uncore C-box 7 perfmon counter MSR.
5778 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
5779 @param EAX Lower 32-bits of MSR value.
5780 @param EDX Upper 32-bits of MSR value.
5782 <b>Example usage</b>
5786 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
5787 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
5790 #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9
5794 Package. Uncore C-box 7 perfmon event select MSR.
5796 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
5797 @param EAX Lower 32-bits of MSR value.
5798 @param EDX Upper 32-bits of MSR value.
5800 <b>Example usage</b>
5804 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
5805 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
5808 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA
5812 Package. Uncore C-box 7 perfmon counter MSR.
5814 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
5815 @param EAX Lower 32-bits of MSR value.
5816 @param EDX Upper 32-bits of MSR value.
5818 <b>Example usage</b>
5822 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
5823 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
5826 #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB
5830 Package. Uncore R-box 0 perfmon local box control MSR.
5832 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
5833 @param EAX Lower 32-bits of MSR value.
5834 @param EDX Upper 32-bits of MSR value.
5836 <b>Example usage</b>
5840 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
5841 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
5844 #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00
5848 Package. Uncore R-box 0 perfmon local box status MSR.
5850 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
5851 @param EAX Lower 32-bits of MSR value.
5852 @param EDX Upper 32-bits of MSR value.
5854 <b>Example usage</b>
5858 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
5859 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
5862 #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01
5866 Package. Uncore R-box 0 perfmon local box overflow control MSR.
5868 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
5869 @param EAX Lower 32-bits of MSR value.
5870 @param EDX Upper 32-bits of MSR value.
5872 <b>Example usage</b>
5876 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
5877 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
5880 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02
5884 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
5886 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
5887 @param EAX Lower 32-bits of MSR value.
5888 @param EDX Upper 32-bits of MSR value.
5890 <b>Example usage</b>
5894 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
5895 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
5898 #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04
5902 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
5904 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
5905 @param EAX Lower 32-bits of MSR value.
5906 @param EDX Upper 32-bits of MSR value.
5908 <b>Example usage</b>
5912 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
5913 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
5916 #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05
5920 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
5922 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
5923 @param EAX Lower 32-bits of MSR value.
5924 @param EDX Upper 32-bits of MSR value.
5926 <b>Example usage</b>
5930 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
5931 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
5934 #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06
5938 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
5940 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
5941 @param EAX Lower 32-bits of MSR value.
5942 @param EDX Upper 32-bits of MSR value.
5944 <b>Example usage</b>
5948 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
5949 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
5952 #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07
5956 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
5958 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
5959 @param EAX Lower 32-bits of MSR value.
5960 @param EDX Upper 32-bits of MSR value.
5962 <b>Example usage</b>
5966 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
5967 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
5970 #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08
5974 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
5976 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
5977 @param EAX Lower 32-bits of MSR value.
5978 @param EDX Upper 32-bits of MSR value.
5980 <b>Example usage</b>
5984 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
5985 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
5988 #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09
5992 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
5994 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
5995 @param EAX Lower 32-bits of MSR value.
5996 @param EDX Upper 32-bits of MSR value.
5998 <b>Example usage</b>
6002 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
6003 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
6006 #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A
6010 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
6012 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
6013 @param EAX Lower 32-bits of MSR value.
6014 @param EDX Upper 32-bits of MSR value.
6016 <b>Example usage</b>
6020 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
6021 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
6024 #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B
6028 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
6030 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
6031 @param EAX Lower 32-bits of MSR value.
6032 @param EDX Upper 32-bits of MSR value.
6034 <b>Example usage</b>
6038 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
6039 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
6042 #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C
6046 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
6048 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
6049 @param EAX Lower 32-bits of MSR value.
6050 @param EDX Upper 32-bits of MSR value.
6052 <b>Example usage</b>
6056 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
6057 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
6060 #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D
6064 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
6066 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
6067 @param EAX Lower 32-bits of MSR value.
6068 @param EDX Upper 32-bits of MSR value.
6070 <b>Example usage</b>
6074 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
6075 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
6078 #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E
6082 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
6084 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
6085 @param EAX Lower 32-bits of MSR value.
6086 @param EDX Upper 32-bits of MSR value.
6088 <b>Example usage</b>
6092 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
6093 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
6096 #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F
6100 Package. Uncore R-box 0 perfmon event select MSR.
6102 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
6103 @param EAX Lower 32-bits of MSR value.
6104 @param EDX Upper 32-bits of MSR value.
6106 <b>Example usage</b>
6110 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
6111 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
6114 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10
6118 Package. Uncore R-box 0 perfmon counter MSR.
6120 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
6121 @param EAX Lower 32-bits of MSR value.
6122 @param EDX Upper 32-bits of MSR value.
6124 <b>Example usage</b>
6128 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
6129 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
6132 #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11
6136 Package. Uncore R-box 0 perfmon event select MSR.
6138 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
6139 @param EAX Lower 32-bits of MSR value.
6140 @param EDX Upper 32-bits of MSR value.
6142 <b>Example usage</b>
6146 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
6147 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
6150 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12
6154 Package. Uncore R-box 0 perfmon counter MSR.
6156 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
6157 @param EAX Lower 32-bits of MSR value.
6158 @param EDX Upper 32-bits of MSR value.
6160 <b>Example usage</b>
6164 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
6165 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
6168 #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13
6172 Package. Uncore R-box 0 perfmon event select MSR.
6174 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
6175 @param EAX Lower 32-bits of MSR value.
6176 @param EDX Upper 32-bits of MSR value.
6178 <b>Example usage</b>
6182 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
6183 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
6186 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14
6190 Package. Uncore R-box 0 perfmon counter MSR.
6192 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
6193 @param EAX Lower 32-bits of MSR value.
6194 @param EDX Upper 32-bits of MSR value.
6196 <b>Example usage</b>
6200 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
6201 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
6204 #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15
6208 Package. Uncore R-box 0 perfmon event select MSR.
6210 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
6211 @param EAX Lower 32-bits of MSR value.
6212 @param EDX Upper 32-bits of MSR value.
6214 <b>Example usage</b>
6218 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
6219 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
6222 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16
6226 Package. Uncore R-box 0 perfmon counter MSR.
6228 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
6229 @param EAX Lower 32-bits of MSR value.
6230 @param EDX Upper 32-bits of MSR value.
6232 <b>Example usage</b>
6236 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
6237 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
6240 #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17
6244 Package. Uncore R-box 0 perfmon event select MSR.
6246 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
6247 @param EAX Lower 32-bits of MSR value.
6248 @param EDX Upper 32-bits of MSR value.
6250 <b>Example usage</b>
6254 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
6255 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
6258 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18
6262 Package. Uncore R-box 0 perfmon counter MSR.
6264 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
6265 @param EAX Lower 32-bits of MSR value.
6266 @param EDX Upper 32-bits of MSR value.
6268 <b>Example usage</b>
6272 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
6273 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
6276 #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19
6280 Package. Uncore R-box 0 perfmon event select MSR.
6282 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
6283 @param EAX Lower 32-bits of MSR value.
6284 @param EDX Upper 32-bits of MSR value.
6286 <b>Example usage</b>
6290 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
6291 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
6294 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A
6298 Package. Uncore R-box 0 perfmon counter MSR.
6300 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
6301 @param EAX Lower 32-bits of MSR value.
6302 @param EDX Upper 32-bits of MSR value.
6304 <b>Example usage</b>
6308 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
6309 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
6312 #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B
6316 Package. Uncore R-box 0 perfmon event select MSR.
6318 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
6319 @param EAX Lower 32-bits of MSR value.
6320 @param EDX Upper 32-bits of MSR value.
6322 <b>Example usage</b>
6326 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
6327 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
6330 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C
6334 Package. Uncore R-box 0 perfmon counter MSR.
6336 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
6337 @param EAX Lower 32-bits of MSR value.
6338 @param EDX Upper 32-bits of MSR value.
6340 <b>Example usage</b>
6344 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
6345 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
6348 #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D
6352 Package. Uncore R-box 0 perfmon event select MSR.
6354 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
6355 @param EAX Lower 32-bits of MSR value.
6356 @param EDX Upper 32-bits of MSR value.
6358 <b>Example usage</b>
6362 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
6363 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
6366 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E
6370 Package. Uncore R-box 0 perfmon counter MSR.
6372 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
6373 @param EAX Lower 32-bits of MSR value.
6374 @param EDX Upper 32-bits of MSR value.
6376 <b>Example usage</b>
6380 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
6381 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
6384 #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F
6388 Package. Uncore R-box 1 perfmon local box control MSR.
6390 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
6391 @param EAX Lower 32-bits of MSR value.
6392 @param EDX Upper 32-bits of MSR value.
6394 <b>Example usage</b>
6398 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
6399 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
6402 #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20
6406 Package. Uncore R-box 1 perfmon local box status MSR.
6408 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
6409 @param EAX Lower 32-bits of MSR value.
6410 @param EDX Upper 32-bits of MSR value.
6412 <b>Example usage</b>
6416 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
6417 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
6420 #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21
6424 Package. Uncore R-box 1 perfmon local box overflow control MSR.
6426 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
6427 @param EAX Lower 32-bits of MSR value.
6428 @param EDX Upper 32-bits of MSR value.
6430 <b>Example usage</b>
6434 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
6435 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
6438 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22
6442 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
6444 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
6445 @param EAX Lower 32-bits of MSR value.
6446 @param EDX Upper 32-bits of MSR value.
6448 <b>Example usage</b>
6452 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
6453 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
6456 #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24
6460 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
6462 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
6463 @param EAX Lower 32-bits of MSR value.
6464 @param EDX Upper 32-bits of MSR value.
6466 <b>Example usage</b>
6470 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
6471 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
6474 #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25
6478 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
6480 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
6481 @param EAX Lower 32-bits of MSR value.
6482 @param EDX Upper 32-bits of MSR value.
6484 <b>Example usage</b>
6488 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
6489 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
6492 #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26
6496 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
6498 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
6499 @param EAX Lower 32-bits of MSR value.
6500 @param EDX Upper 32-bits of MSR value.
6502 <b>Example usage</b>
6506 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
6507 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
6510 #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27
6514 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
6516 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
6517 @param EAX Lower 32-bits of MSR value.
6518 @param EDX Upper 32-bits of MSR value.
6520 <b>Example usage</b>
6524 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
6525 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
6528 #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28
6532 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
6534 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
6535 @param EAX Lower 32-bits of MSR value.
6536 @param EDX Upper 32-bits of MSR value.
6538 <b>Example usage</b>
6542 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
6543 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
6546 #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29
6550 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
6552 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
6553 @param EAX Lower 32-bits of MSR value.
6554 @param EDX Upper 32-bits of MSR value.
6556 <b>Example usage</b>
6560 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
6561 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
6564 #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A
6568 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
6570 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
6571 @param EAX Lower 32-bits of MSR value.
6572 @param EDX Upper 32-bits of MSR value.
6574 <b>Example usage</b>
6578 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
6579 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
6582 #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B
6586 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
6588 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
6589 @param EAX Lower 32-bits of MSR value.
6590 @param EDX Upper 32-bits of MSR value.
6592 <b>Example usage</b>
6596 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
6597 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
6600 #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C
6604 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
6606 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
6607 @param EAX Lower 32-bits of MSR value.
6608 @param EDX Upper 32-bits of MSR value.
6610 <b>Example usage</b>
6614 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
6615 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
6618 #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D
6622 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
6624 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
6625 @param EAX Lower 32-bits of MSR value.
6626 @param EDX Upper 32-bits of MSR value.
6628 <b>Example usage</b>
6632 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
6633 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
6636 #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E
6640 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
6642 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
6643 @param EAX Lower 32-bits of MSR value.
6644 @param EDX Upper 32-bits of MSR value.
6646 <b>Example usage</b>
6650 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
6651 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
6654 #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F
6658 Package. Uncore R-box 1 perfmon event select MSR.
6660 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
6661 @param EAX Lower 32-bits of MSR value.
6662 @param EDX Upper 32-bits of MSR value.
6664 <b>Example usage</b>
6668 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
6669 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
6672 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30
6676 Package. Uncore R-box 1 perfmon counter MSR.
6678 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
6679 @param EAX Lower 32-bits of MSR value.
6680 @param EDX Upper 32-bits of MSR value.
6682 <b>Example usage</b>
6686 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
6687 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
6690 #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31
6694 Package. Uncore R-box 1 perfmon event select MSR.
6696 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
6697 @param EAX Lower 32-bits of MSR value.
6698 @param EDX Upper 32-bits of MSR value.
6700 <b>Example usage</b>
6704 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
6705 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
6708 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32
6712 Package. Uncore R-box 1 perfmon counter MSR.
6714 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
6715 @param EAX Lower 32-bits of MSR value.
6716 @param EDX Upper 32-bits of MSR value.
6718 <b>Example usage</b>
6722 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
6723 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
6726 #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33
6730 Package. Uncore R-box 1 perfmon event select MSR.
6732 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
6733 @param EAX Lower 32-bits of MSR value.
6734 @param EDX Upper 32-bits of MSR value.
6736 <b>Example usage</b>
6740 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
6741 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
6744 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34
6748 Package. Uncore R-box 1 perfmon counter MSR.
6750 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
6751 @param EAX Lower 32-bits of MSR value.
6752 @param EDX Upper 32-bits of MSR value.
6754 <b>Example usage</b>
6758 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
6759 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
6762 #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35
6766 Package. Uncore R-box 1 perfmon event select MSR.
6768 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
6769 @param EAX Lower 32-bits of MSR value.
6770 @param EDX Upper 32-bits of MSR value.
6772 <b>Example usage</b>
6776 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
6777 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
6780 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36
6784 Package. Uncore R-box 1 perfmon counter MSR.
6786 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
6787 @param EAX Lower 32-bits of MSR value.
6788 @param EDX Upper 32-bits of MSR value.
6790 <b>Example usage</b>
6794 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
6795 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
6798 #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37
6802 Package. Uncore R-box 1 perfmon event select MSR.
6804 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
6805 @param EAX Lower 32-bits of MSR value.
6806 @param EDX Upper 32-bits of MSR value.
6808 <b>Example usage</b>
6812 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
6813 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
6816 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38
6820 Package. Uncore R-box 1 perfmon counter MSR.
6822 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
6823 @param EAX Lower 32-bits of MSR value.
6824 @param EDX Upper 32-bits of MSR value.
6826 <b>Example usage</b>
6830 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
6831 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
6834 #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39
6838 Package. Uncore R-box 1 perfmon event select MSR.
6840 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
6841 @param EAX Lower 32-bits of MSR value.
6842 @param EDX Upper 32-bits of MSR value.
6844 <b>Example usage</b>
6848 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
6849 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
6852 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A
6856 Package. Uncore R-box 1perfmon counter MSR.
6858 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
6859 @param EAX Lower 32-bits of MSR value.
6860 @param EDX Upper 32-bits of MSR value.
6862 <b>Example usage</b>
6866 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
6867 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
6870 #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B
6874 Package. Uncore R-box 1 perfmon event select MSR.
6876 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
6877 @param EAX Lower 32-bits of MSR value.
6878 @param EDX Upper 32-bits of MSR value.
6880 <b>Example usage</b>
6884 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
6885 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
6888 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C
6892 Package. Uncore R-box 1 perfmon counter MSR.
6894 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
6895 @param EAX Lower 32-bits of MSR value.
6896 @param EDX Upper 32-bits of MSR value.
6898 <b>Example usage</b>
6902 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
6903 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
6906 #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D
6910 Package. Uncore R-box 1 perfmon event select MSR.
6912 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
6913 @param EAX Lower 32-bits of MSR value.
6914 @param EDX Upper 32-bits of MSR value.
6916 <b>Example usage</b>
6920 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
6921 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
6924 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E
6928 Package. Uncore R-box 1 perfmon counter MSR.
6930 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
6931 @param EAX Lower 32-bits of MSR value.
6932 @param EDX Upper 32-bits of MSR value.
6934 <b>Example usage</b>
6938 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
6939 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
6942 #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F
6946 Package. Uncore B-box 0 perfmon local box match MSR.
6948 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
6949 @param EAX Lower 32-bits of MSR value.
6950 @param EDX Upper 32-bits of MSR value.
6952 <b>Example usage</b>
6956 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
6957 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
6960 #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45
6964 Package. Uncore B-box 0 perfmon local box mask MSR.
6966 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
6967 @param EAX Lower 32-bits of MSR value.
6968 @param EDX Upper 32-bits of MSR value.
6970 <b>Example usage</b>
6974 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
6975 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
6978 #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46
6982 Package. Uncore S-box 0 perfmon local box match MSR.
6984 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
6985 @param EAX Lower 32-bits of MSR value.
6986 @param EDX Upper 32-bits of MSR value.
6988 <b>Example usage</b>
6992 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
6993 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
6996 #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49
7000 Package. Uncore S-box 0 perfmon local box mask MSR.
7002 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
7003 @param EAX Lower 32-bits of MSR value.
7004 @param EDX Upper 32-bits of MSR value.
7006 <b>Example usage</b>
7010 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
7011 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
7014 #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A
7018 Package. Uncore B-box 1 perfmon local box match MSR.
7020 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
7021 @param EAX Lower 32-bits of MSR value.
7022 @param EDX Upper 32-bits of MSR value.
7024 <b>Example usage</b>
7028 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
7029 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
7032 #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D
7036 Package. Uncore B-box 1 perfmon local box mask MSR.
7038 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
7039 @param EAX Lower 32-bits of MSR value.
7040 @param EDX Upper 32-bits of MSR value.
7042 <b>Example usage</b>
7046 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
7047 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
7050 #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E
7054 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
7056 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
7057 @param EAX Lower 32-bits of MSR value.
7058 @param EDX Upper 32-bits of MSR value.
7060 <b>Example usage</b>
7064 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
7065 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
7068 #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54
7072 Package. Uncore M-box 0 perfmon local box address match MSR.
7074 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
7075 @param EAX Lower 32-bits of MSR value.
7076 @param EDX Upper 32-bits of MSR value.
7078 <b>Example usage</b>
7082 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
7083 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
7086 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55
7090 Package. Uncore M-box 0 perfmon local box address mask MSR.
7092 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
7093 @param EAX Lower 32-bits of MSR value.
7094 @param EDX Upper 32-bits of MSR value.
7096 <b>Example usage</b>
7100 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
7101 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
7104 #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56
7108 Package. Uncore S-box 1 perfmon local box match MSR.
7110 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
7111 @param EAX Lower 32-bits of MSR value.
7112 @param EDX Upper 32-bits of MSR value.
7114 <b>Example usage</b>
7118 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
7119 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
7122 #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59
7126 Package. Uncore S-box 1 perfmon local box mask MSR.
7128 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
7129 @param EAX Lower 32-bits of MSR value.
7130 @param EDX Upper 32-bits of MSR value.
7132 <b>Example usage</b>
7136 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
7137 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
7140 #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A
7144 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
7146 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
7147 @param EAX Lower 32-bits of MSR value.
7148 @param EDX Upper 32-bits of MSR value.
7150 <b>Example usage</b>
7154 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
7155 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
7158 #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C
7162 Package. Uncore M-box 1 perfmon local box address match MSR.
7164 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
7165 @param EAX Lower 32-bits of MSR value.
7166 @param EDX Upper 32-bits of MSR value.
7168 <b>Example usage</b>
7172 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
7173 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
7176 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D
7180 Package. Uncore M-box 1 perfmon local box address mask MSR.
7182 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
7183 @param EAX Lower 32-bits of MSR value.
7184 @param EDX Upper 32-bits of MSR value.
7186 <b>Example usage</b>
7190 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
7191 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
7194 #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E