]> git.proxmox.com Git - mirror_edk2.git/blob - UefiCpuPkg/Include/Register/Msr/P6Msr.h
projects / mirror_edk2.git / blob
? search:


9cef72b2394e0899f4b48eeed0282380c904a399
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / P6Msr.h
1 /** @file
2 MSR Definitions for P6 Family Processors.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
21
22 **/
23
24 #ifndef __P6_MSR_H__
25 #define __P6_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Is P6 Family Processors?
31
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
34
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
37 **/
38 #define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
40 ( \
41 DisplayModel == 0x03 || \
42 DisplayModel == 0x05 || \
43 DisplayModel == 0x07 || \
44 DisplayModel == 0x08 || \
45 DisplayModel == 0x0A || \
46 DisplayModel == 0x0B \
47 ) \
48 )
49
50 /**
51 See Section 2.22, "MSRs in Pentium Processors.".
52
53 @param ECX MSR_P6_P5_MC_ADDR (0x00000000)
54 @param EAX Lower 32-bits of MSR value.
55 @param EDX Upper 32-bits of MSR value.
56
57 <b>Example usage</b>
58 @code
59 UINT64 Msr;
60
61 Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
62 AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
63 @endcode
64 @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
65 **/
66 #define MSR_P6_P5_MC_ADDR 0x00000000
67
68
69 /**
70 See Section 2.22, "MSRs in Pentium Processors.".
71
72 @param ECX MSR_P6_P5_MC_TYPE (0x00000001)
73 @param EAX Lower 32-bits of MSR value.
74 @param EDX Upper 32-bits of MSR value.
75
76 <b>Example usage</b>
77 @code
78 UINT64 Msr;
79
80 Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
81 AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
82 @endcode
83 @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
84 **/
85 #define MSR_P6_P5_MC_TYPE 0x00000001
86
87
88 /**
89 See Section 17.17, "Time-Stamp Counter.".
90
91 @param ECX MSR_P6_TSC (0x00000010)
92 @param EAX Lower 32-bits of MSR value.
93 @param EDX Upper 32-bits of MSR value.
94
95 <b>Example usage</b>
96 @code
97 UINT64 Msr;
98
99 Msr = AsmReadMsr64 (MSR_P6_TSC);
100 AsmWriteMsr64 (MSR_P6_TSC, Msr);
101 @endcode
102 @note MSR_P6_TSC is defined as TSC in SDM.
103 **/
104 #define MSR_P6_TSC 0x00000010
105
106
107 /**
108 Platform ID (R) The operating system can use this MSR to determine "slot"
109 information for the processor and the proper microcode update to load.
110
111 @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)
112 @param EAX Lower 32-bits of MSR value.
113 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
114 @param EDX Upper 32-bits of MSR value.
115 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
116
117 <b>Example usage</b>
118 @code
119 MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;
120
121 Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
122 @endcode
123 @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
124 **/
125 #define MSR_P6_IA32_PLATFORM_ID 0x00000017
126
127 /**
128 MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
129 **/
130 typedef union {
131 ///
132 /// Individual bit fields
133 ///
134 struct {
135 UINT32 Reserved1:32;
136 UINT32 Reserved2:18;
137 ///
138 /// [Bits 52:50] Platform Id (R) Contains information concerning the
139 /// intended platform for the processor.
140 ///
141 /// 52 51 50
142 /// 0 0 0 Processor Flag 0.
143 /// 0 0 1 Processor Flag 1
144 /// 0 1 0 Processor Flag 2
145 /// 0 1 1 Processor Flag 3
146 /// 1 0 0 Processor Flag 4
147 /// 1 0 1 Processor Flag 5
148 /// 1 1 0 Processor Flag 6
149 /// 1 1 1 Processor Flag 7
150 ///
151 UINT32 PlatformId:3;
152 ///
153 /// [Bits 56:53] L2 Cache Latency Read.
154 ///
155 UINT32 L2CacheLatencyRead:4;
156 UINT32 Reserved3:3;
157 ///
158 /// [Bit 60] Clock Frequency Ratio Read.
159 ///
160 UINT32 ClockFrequencyRatioRead:1;
161 UINT32 Reserved4:3;
162 } Bits;
163 ///
164 /// All bit fields as a 64-bit value
165 ///
166 UINT64 Uint64;
167 } MSR_P6_IA32_PLATFORM_ID_REGISTER;
168
169
170 /**
171 Section 10.4.4, "Local APIC Status and Location.".
172
173 @param ECX MSR_P6_APIC_BASE (0x0000001B)
174 @param EAX Lower 32-bits of MSR value.
175 Described by the type MSR_P6_APIC_BASE_REGISTER.
176 @param EDX Upper 32-bits of MSR value.
177 Described by the type MSR_P6_APIC_BASE_REGISTER.
178
179 <b>Example usage</b>
180 @code
181 MSR_P6_APIC_BASE_REGISTER Msr;
182
183 Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
184 AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
185 @endcode
186 @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
187 **/
188 #define MSR_P6_APIC_BASE 0x0000001B
189
190 /**
191 MSR information returned for MSR index #MSR_P6_APIC_BASE
192 **/
193 typedef union {
194 ///
195 /// Individual bit fields
196 ///
197 struct {
198 UINT32 Reserved1:8;
199 ///
200 /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
201 ///
202 UINT32 BSP:1;
203 UINT32 Reserved2:2;
204 ///
205 /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
206 /// Disabled.
207 ///
208 UINT32 EN:1;
209 ///
210 /// [Bits 31:12] APIC Base Address.
211 ///
212 UINT32 ApicBase:20;
213 UINT32 Reserved3:32;
214 } Bits;
215 ///
216 /// All bit fields as a 32-bit value
217 ///
218 UINT32 Uint32;
219 ///
220 /// All bit fields as a 64-bit value
221 ///
222 UINT64 Uint64;
223 } MSR_P6_APIC_BASE_REGISTER;
224
225
226 /**
227 Processor Hard Power-On Configuration (R/W) Enables and disables processor
228 features; (R) indicates current processor configuration.
229
230 @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)
231 @param EAX Lower 32-bits of MSR value.
232 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
233 @param EDX Upper 32-bits of MSR value.
234 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
235
236 <b>Example usage</b>
237 @code
238 MSR_P6_EBL_CR_POWERON_REGISTER Msr;
239
240 Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
241 AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
242 @endcode
243 @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
244 **/
245 #define MSR_P6_EBL_CR_POWERON 0x0000002A
246
247 /**
248 MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
249 **/
250 typedef union {
251 ///
252 /// Individual bit fields
253 ///
254 struct {
255 UINT32 Reserved1:1;
256 ///
257 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
258 ///
259 UINT32 DataErrorCheckingEnable:1;
260 ///
261 /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
262 /// 1 = Enabled 0 = Disabled.
263 ///
264 UINT32 ResponseErrorCheckingEnable:1;
265 ///
266 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
267 ///
268 UINT32 AERR_DriveEnable:1;
269 ///
270 /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
271 /// Disabled.
272 ///
273 UINT32 BERR_Enable:1;
274 UINT32 Reserved2:1;
275 ///
276 /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
277 /// Enabled 0 = Disabled.
278 ///
279 UINT32 BERR_DriverEnable:1;
280 ///
281 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
282 ///
283 UINT32 BINIT_DriverEnable:1;
284 ///
285 /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
286 ///
287 UINT32 OutputTriStateEnable:1;
288 ///
289 /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
290 ///
291 UINT32 ExecuteBIST:1;
292 ///
293 /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
294 ///
295 UINT32 AERR_ObservationEnabled:1;
296 UINT32 Reserved3:1;
297 ///
298 /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
299 ///
300 UINT32 BINIT_ObservationEnabled:1;
301 ///
302 /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
303 ///
304 UINT32 InOrderQueueDepth:1;
305 ///
306 /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
307 ///
308 UINT32 ResetVector:1;
309 ///
310 /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
311 ///
312 UINT32 FRCModeEnable:1;
313 ///
314 /// [Bits 17:16] APIC Cluster ID (R).
315 ///
316 UINT32 APICClusterID:2;
317 ///
318 /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
319 /// 133MHz 11 = Reserved.
320 ///
321 UINT32 SystemBusFrequency:2;
322 ///
323 /// [Bits 21:20] Symmetric Arbitration ID (R).
324 ///
325 UINT32 SymmetricArbitrationID:2;
326 ///
327 /// [Bits 25:22] Clock Frequency Ratio (R).
328 ///
329 UINT32 ClockFrequencyRatio:4;
330 ///
331 /// [Bit 26] Low Power Mode Enable (R/W).
332 ///
333 UINT32 LowPowerModeEnable:1;
334 ///
335 /// [Bit 27] Clock Frequency Ratio.
336 ///
337 UINT32 ClockFrequencyRatio1:1;
338 UINT32 Reserved4:4;
339 UINT32 Reserved5:32;
340 } Bits;
341 ///
342 /// All bit fields as a 32-bit value
343 ///
344 UINT32 Uint32;
345 ///
346 /// All bit fields as a 64-bit value
347 ///
348 UINT64 Uint64;
349 } MSR_P6_EBL_CR_POWERON_REGISTER;
350
351
352 /**
353 Test Control Register.
354
355 @param ECX MSR_P6_TEST_CTL (0x00000033)
356 @param EAX Lower 32-bits of MSR value.
357 Described by the type MSR_P6_TEST_CTL_REGISTER.
358 @param EDX Upper 32-bits of MSR value.
359 Described by the type MSR_P6_TEST_CTL_REGISTER.
360
361 <b>Example usage</b>
362 @code
363 MSR_P6_TEST_CTL_REGISTER Msr;
364
365 Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
366 AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
367 @endcode
368 @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
369 **/
370 #define MSR_P6_TEST_CTL 0x00000033
371
372 /**
373 MSR information returned for MSR index #MSR_P6_TEST_CTL
374 **/
375 typedef union {
376 ///
377 /// Individual bit fields
378 ///
379 struct {
380 UINT32 Reserved1:30;
381 ///
382 /// [Bit 30] Streaming Buffer Disable.
383 ///
384 UINT32 StreamingBufferDisable:1;
385 ///
386 /// [Bit 31] Disable LOCK# Assertion for split locked access.
387 ///
388 UINT32 Disable_LOCK:1;
389 UINT32 Reserved2:32;
390 } Bits;
391 ///
392 /// All bit fields as a 32-bit value
393 ///
394 UINT32 Uint32;
395 ///
396 /// All bit fields as a 64-bit value
397 ///
398 UINT64 Uint64;
399 } MSR_P6_TEST_CTL_REGISTER;
400
401
402 /**
403 BIOS Update Trigger Register.
404
405 @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)
406 @param EAX Lower 32-bits of MSR value.
407 @param EDX Upper 32-bits of MSR value.
408
409 <b>Example usage</b>
410 @code
411 UINT64 Msr;
412
413 Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
414 AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
415 @endcode
416 @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
417 **/
418 #define MSR_P6_BIOS_UPDT_TRIG 0x00000079
419
420
421 /**
422 Chunk n data register D[63:0]: used to write to and read from the L2.
423
424 @param ECX MSR_P6_BBL_CR_Dn
425 @param EAX Lower 32-bits of MSR value.
426 @param EDX Upper 32-bits of MSR value.
427
428 <b>Example usage</b>
429 @code
430 UINT64 Msr;
431
432 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
433 AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
434 @endcode
435 @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
436 MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
437 MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
438 @{
439 **/
440 #define MSR_P6_BBL_CR_D0 0x00000088
441 #define MSR_P6_BBL_CR_D1 0x00000089
442 #define MSR_P6_BBL_CR_D2 0x0000008A
443 /// @}
444
445
446 /**
447 BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
448 write to and read from the L2 depending on the usage model.
449
450 @param ECX MSR_P6_BIOS_SIGN (0x0000008B)
451 @param EAX Lower 32-bits of MSR value.
452 @param EDX Upper 32-bits of MSR value.
453
454 <b>Example usage</b>
455 @code
456 UINT64 Msr;
457
458 Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
459 AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
460 @endcode
461 @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
462 **/
463 #define MSR_P6_BIOS_SIGN 0x0000008B
464
465
466 /**
467
468
469 @param ECX MSR_P6_PERFCTR0 (0x000000C1)
470 @param EAX Lower 32-bits of MSR value.
471 @param EDX Upper 32-bits of MSR value.
472
473 <b>Example usage</b>
474 @code
475 UINT64 Msr;
476
477 Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
478 AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
479 @endcode
480 @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
481 MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
482 @{
483 **/
484 #define MSR_P6_PERFCTR0 0x000000C1
485 #define MSR_P6_PERFCTR1 0x000000C2
486 /// @}
487
488
489 /**
490
491
492 @param ECX MSR_P6_MTRRCAP (0x000000FE)
493 @param EAX Lower 32-bits of MSR value.
494 @param EDX Upper 32-bits of MSR value.
495
496 <b>Example usage</b>
497 @code
498 UINT64 Msr;
499
500 Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
501 AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
502 @endcode
503 @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
504 **/
505 #define MSR_P6_MTRRCAP 0x000000FE
506
507
508 /**
509 Address register: used to send specified address (A31-A3) to L2 during cache
510 initialization accesses.
511
512 @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)
513 @param EAX Lower 32-bits of MSR value.
514 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
515 @param EDX Upper 32-bits of MSR value.
516 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
517
518 <b>Example usage</b>
519 @code
520 MSR_P6_BBL_CR_ADDR_REGISTER Msr;
521
522 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
523 AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
524 @endcode
525 @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
526 **/
527 #define MSR_P6_BBL_CR_ADDR 0x00000116
528
529 /**
530 MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
531 **/
532 typedef union {
533 ///
534 /// Individual bit fields
535 ///
536 struct {
537 UINT32 Reserved1:3;
538 ///
539 /// [Bits 31:3] Address bits
540 ///
541 UINT32 Address:29;
542 UINT32 Reserved2:32;
543 } Bits;
544 ///
545 /// All bit fields as a 32-bit value
546 ///
547 UINT32 Uint32;
548 ///
549 /// All bit fields as a 64-bit value
550 ///
551 UINT64 Uint64;
552 } MSR_P6_BBL_CR_ADDR_REGISTER;
553
554
555 /**
556 Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
557
558 @param ECX MSR_P6_BBL_CR_DECC (0x00000118)
559 @param EAX Lower 32-bits of MSR value.
560 @param EDX Upper 32-bits of MSR value.
561
562 <b>Example usage</b>
563 @code
564 UINT64 Msr;
565
566 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
567 AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
568 @endcode
569 @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
570 **/
571 #define MSR_P6_BBL_CR_DECC 0x00000118
572
573
574 /**
575 Control register: used to program L2 commands to be issued via cache
576 configuration accesses mechanism. Also receives L2 lookup response.
577
578 @param ECX MSR_P6_BBL_CR_CTL (0x00000119)
579 @param EAX Lower 32-bits of MSR value.
580 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
581 @param EDX Upper 32-bits of MSR value.
582 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
583
584 <b>Example usage</b>
585 @code
586 MSR_P6_BBL_CR_CTL_REGISTER Msr;
587
588 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
589 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
590 @endcode
591 @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
592 **/
593 #define MSR_P6_BBL_CR_CTL 0x00000119
594
595 /**
596 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
597 **/
598 typedef union {
599 ///
600 /// Individual bit fields
601 ///
602 struct {
603 ///
604 /// [Bits 4:0] L2 Command
605 /// Data Read w/ LRU update (RLU)
606 /// Tag Read w/ Data Read (TRR)
607 /// Tag Inquire (TI)
608 /// L2 Control Register Read (CR)
609 /// L2 Control Register Write (CW)
610 /// Tag Write w/ Data Read (TWR)
611 /// Tag Write w/ Data Write (TWW)
612 /// Tag Write (TW).
613 ///
614 UINT32 L2Command:5;
615 ///
616 /// [Bits 6:5] State to L2
617 ///
618 UINT32 StateToL2:2;
619 UINT32 Reserved:1;
620 ///
621 /// [Bits 9:8] Way to L2.
622 ///
623 UINT32 WayToL2:2;
624 ///
625 /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
626 ///
627 UINT32 Way:2;
628 ///
629 /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
630 ///
631 UINT32 MESI:2;
632 ///
633 /// [Bits 15:14] State from L2.
634 ///
635 UINT32 StateFromL2:2;
636 UINT32 Reserved2:1;
637 ///
638 /// [Bit 17] L2 Hit.
639 ///
640 UINT32 L2Hit:1;
641 UINT32 Reserved3:1;
642 ///
643 /// [Bits 20:19] User supplied ECC.
644 ///
645 UINT32 UserEcc:2;
646 ///
647 /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
648 ///
649 UINT32 ProcessorNumber:1;
650 UINT32 Reserved4:10;
651 UINT32 Reserved5:32;
652 } Bits;
653 ///
654 /// All bit fields as a 32-bit value
655 ///
656 UINT32 Uint32;
657 ///
658 /// All bit fields as a 64-bit value
659 ///
660 UINT64 Uint64;
661 } MSR_P6_BBL_CR_CTL_REGISTER;
662
663
664 /**
665 Trigger register: used to initiate a cache configuration accesses access,
666 Write only with Data = 0.
667
668 @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)
669 @param EAX Lower 32-bits of MSR value.
670 @param EDX Upper 32-bits of MSR value.
671
672 <b>Example usage</b>
673 @code
674 UINT64 Msr;
675
676 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
677 AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
678 @endcode
679 @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
680 **/
681 #define MSR_P6_BBL_CR_TRIG 0x0000011A
682
683
684 /**
685 Busy register: indicates when a cache configuration accesses L2 command is
686 in progress. D[0] = 1 = BUSY.
687
688 @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)
689 @param EAX Lower 32-bits of MSR value.
690 @param EDX Upper 32-bits of MSR value.
691
692 <b>Example usage</b>
693 @code
694 UINT64 Msr;
695
696 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
697 AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
698 @endcode
699 @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.
700 **/
701 #define MSR_P6_BBL_CR_BUSY 0x0000011B
702
703
704 /**
705 Control register 3: used to configure the L2 Cache.
706
707 @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)
708 @param EAX Lower 32-bits of MSR value.
709 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
710 @param EDX Upper 32-bits of MSR value.
711 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
712
713 <b>Example usage</b>
714 @code
715 MSR_P6_BBL_CR_CTL3_REGISTER Msr;
716
717 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
718 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
719 @endcode
720 @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.
721 **/
722 #define MSR_P6_BBL_CR_CTL3 0x0000011E
723
724 /**
725 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
726 **/
727 typedef union {
728 ///
729 /// Individual bit fields
730 ///
731 struct {
732 ///
733 /// [Bit 0] L2 Configured (read/write ).
734 ///
735 UINT32 L2Configured:1;
736 ///
737 /// [Bits 4:1] L2 Cache Latency (read/write).
738 ///
739 UINT32 L2CacheLatency:4;
740 ///
741 /// [Bit 5] ECC Check Enable (read/write).
742 ///
743 UINT32 ECCCheckEnable:1;
744 ///
745 /// [Bit 6] Address Parity Check Enable (read/write).
746 ///
747 UINT32 AddressParityCheckEnable:1;
748 ///
749 /// [Bit 7] CRTN Parity Check Enable (read/write).
750 ///
751 UINT32 CRTNParityCheckEnable:1;
752 ///
753 /// [Bit 8] L2 Enabled (read/write).
754 ///
755 UINT32 L2Enabled:1;
756 ///
757 /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
758 /// Reserved.
759 ///
760 UINT32 L2Associativity:2;
761 ///
762 /// [Bits 12:11] Number of L2 banks (read only).
763 ///
764 UINT32 L2Banks:2;
765 ///
766 /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
767 /// 1MByte 2MByte 4MBytes.
768 ///
769 UINT32 CacheSizePerBank:5;
770 ///
771 /// [Bit 18] Cache State error checking enable (read/write).
772 ///
773 UINT32 CacheStateErrorEnable:1;
774 UINT32 Reserved1:1;
775 ///
776 /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
777 /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
778 ///
779 UINT32 L2AddressRange:3;
780 ///
781 /// [Bit 23] L2 Hardware Disable (read only).
782 ///
783 UINT32 L2HardwareDisable:1;
784 UINT32 Reserved2:1;
785 ///
786 /// [Bit 25] Cache bus fraction (read only).
787 ///
788 UINT32 CacheBusFraction:1;
789 UINT32 Reserved3:6;
790 UINT32 Reserved4:32;
791 } Bits;
792 ///
793 /// All bit fields as a 32-bit value
794 ///
795 UINT32 Uint32;
796 ///
797 /// All bit fields as a 64-bit value
798 ///
799 UINT64 Uint64;
800 } MSR_P6_BBL_CR_CTL3_REGISTER;
801
802
803 /**
804 CS register target for CPL 0 code.
805
806 @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)
807 @param EAX Lower 32-bits of MSR value.
808 @param EDX Upper 32-bits of MSR value.
809
810 <b>Example usage</b>
811 @code
812 UINT64 Msr;
813
814 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
815 AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
816 @endcode
817 @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.
818 **/
819 #define MSR_P6_SYSENTER_CS_MSR 0x00000174
820
821
822 /**
823 Stack pointer for CPL 0 stack.
824
825 @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)
826 @param EAX Lower 32-bits of MSR value.
827 @param EDX Upper 32-bits of MSR value.
828
829 <b>Example usage</b>
830 @code
831 UINT64 Msr;
832
833 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
834 AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
835 @endcode
836 @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.
837 **/
838 #define MSR_P6_SYSENTER_ESP_MSR 0x00000175
839
840
841 /**
842 CPL 0 code entry point.
843
844 @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)
845 @param EAX Lower 32-bits of MSR value.
846 @param EDX Upper 32-bits of MSR value.
847
848 <b>Example usage</b>
849 @code
850 UINT64 Msr;
851
852 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
853 AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
854 @endcode
855 @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.
856 **/
857 #define MSR_P6_SYSENTER_EIP_MSR 0x00000176
858
859
860 /**
861
862
863 @param ECX MSR_P6_MCG_CAP (0x00000179)
864 @param EAX Lower 32-bits of MSR value.
865 @param EDX Upper 32-bits of MSR value.
866
867 <b>Example usage</b>
868 @code
869 UINT64 Msr;
870
871 Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
872 AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
873 @endcode
874 @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.
875 **/
876 #define MSR_P6_MCG_CAP 0x00000179
877
878
879 /**
880
881
882 @param ECX MSR_P6_MCG_STATUS (0x0000017A)
883 @param EAX Lower 32-bits of MSR value.
884 @param EDX Upper 32-bits of MSR value.
885
886 <b>Example usage</b>
887 @code
888 UINT64 Msr;
889
890 Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
891 AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
892 @endcode
893 @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.
894 **/
895 #define MSR_P6_MCG_STATUS 0x0000017A
896
897
898 /**
899
900
901 @param ECX MSR_P6_MCG_CTL (0x0000017B)
902 @param EAX Lower 32-bits of MSR value.
903 @param EDX Upper 32-bits of MSR value.
904
905 <b>Example usage</b>
906 @code
907 UINT64 Msr;
908
909 Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
910 AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
911 @endcode
912 @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.
913 **/
914 #define MSR_P6_MCG_CTL 0x0000017B
915
916
917 /**
918
919
920 @param ECX MSR_P6_PERFEVTSELn
921 @param EAX Lower 32-bits of MSR value.
922 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
923 @param EDX Upper 32-bits of MSR value.
924 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
925
926 <b>Example usage</b>
927 @code
928 MSR_P6_PERFEVTSEL_REGISTER Msr;
929
930 Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
931 AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
932 @endcode
933 @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.
934 MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.
935 @{
936 **/
937 #define MSR_P6_PERFEVTSEL0 0x00000186
938 #define MSR_P6_PERFEVTSEL1 0x00000187
939 /// @}
940
941 /**
942 MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
943 #MSR_P6_PERFEVTSEL1.
944 **/
945 typedef union {
946 ///
947 /// Individual bit fields
948 ///
949 struct {
950 ///
951 /// [Bits 7:0] Event Select Refer to Performance Counter section for a
952 /// list of event encodings.
953 ///
954 UINT32 EventSelect:8;
955 ///
956 /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
957 /// all count options.
958 ///
959 UINT32 UMASK:8;
960 ///
961 /// [Bit 16] USER Controls the counting of events at Privilege levels of
962 /// 1, 2, and 3.
963 ///
964 UINT32 USR:1;
965 ///
966 /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
967 ///
968 UINT32 OS:1;
969 ///
970 /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
971 ///
972 UINT32 E:1;
973 ///
974 /// [Bit 19] PC Enabled the signaling of performance counter overflow via
975 /// BP0 pin.
976 ///
977 UINT32 PC:1;
978 ///
979 /// [Bit 20] INT Enables the signaling of counter overflow via input to
980 /// APIC 1 = Enable 0 = Disable.
981 ///
982 UINT32 INT:1;
983 UINT32 Reserved1:1;
984 ///
985 /// [Bit 22] ENABLE Enables the counting of performance events in both
986 /// counters 1 = Enable 0 = Disable.
987 ///
988 UINT32 EN:1;
989 ///
990 /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
991 /// = Non-Inverted.
992 ///
993 UINT32 INV:1;
994 ///
995 /// [Bits 31:24] CMASK (Counter Mask).
996 ///
997 UINT32 CMASK:8;
998 UINT32 Reserved2:32;
999 } Bits;
1000 ///
1001 /// All bit fields as a 32-bit value
1002 ///
1003 UINT32 Uint32;
1004 ///
1005 /// All bit fields as a 64-bit value
1006 ///
1007 UINT64 Uint64;
1008 } MSR_P6_PERFEVTSEL_REGISTER;
1009
1010
1011 /**
1012
1013
1014 @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)
1015 @param EAX Lower 32-bits of MSR value.
1016 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
1017 @param EDX Upper 32-bits of MSR value.
1018 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
1019
1020 <b>Example usage</b>
1021 @code
1022 MSR_P6_DEBUGCTLMSR_REGISTER Msr;
1023
1024 Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
1025 AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
1026 @endcode
1027 @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.
1028 **/
1029 #define MSR_P6_DEBUGCTLMSR 0x000001D9
1030
1031 /**
1032 MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
1033 **/
1034 typedef union {
1035 ///
1036 /// Individual bit fields
1037 ///
1038 struct {
1039 ///
1040 /// [Bit 0] Enable/Disable Last Branch Records.
1041 ///
1042 UINT32 LBR:1;
1043 ///
1044 /// [Bit 1] Branch Trap Flag.
1045 ///
1046 UINT32 BTF:1;
1047 ///
1048 /// [Bit 2] Performance Monitoring/Break Point Pins.
1049 ///
1050 UINT32 PB0:1;
1051 ///
1052 /// [Bit 3] Performance Monitoring/Break Point Pins.
1053 ///
1054 UINT32 PB1:1;
1055 ///
1056 /// [Bit 4] Performance Monitoring/Break Point Pins.
1057 ///
1058 UINT32 PB2:1;
1059 ///
1060 /// [Bit 5] Performance Monitoring/Break Point Pins.
1061 ///
1062 UINT32 PB3:1;
1063 ///
1064 /// [Bit 6] Enable/Disable Execution Trace Messages.
1065 ///
1066 UINT32 TR:1;
1067 UINT32 Reserved1:25;
1068 UINT32 Reserved2:32;
1069 } Bits;
1070 ///
1071 /// All bit fields as a 32-bit value
1072 ///
1073 UINT32 Uint32;
1074 ///
1075 /// All bit fields as a 64-bit value
1076 ///
1077 UINT64 Uint64;
1078 } MSR_P6_DEBUGCTLMSR_REGISTER;
1079
1080
1081 /**
1082
1083
1084 @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)
1085 @param EAX Lower 32-bits of MSR value.
1086 @param EDX Upper 32-bits of MSR value.
1087
1088 <b>Example usage</b>
1089 @code
1090 UINT64 Msr;
1091
1092 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
1093 AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
1094 @endcode
1095 @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.
1096 **/
1097 #define MSR_P6_LASTBRANCHFROMIP 0x000001DB
1098
1099
1100 /**
1101
1102
1103 @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)
1104 @param EAX Lower 32-bits of MSR value.
1105 @param EDX Upper 32-bits of MSR value.
1106
1107 <b>Example usage</b>
1108 @code
1109 UINT64 Msr;
1110
1111 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
1112 AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
1113 @endcode
1114 @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.
1115 **/
1116 #define MSR_P6_LASTBRANCHTOIP 0x000001DC
1117
1118
1119 /**
1120
1121
1122 @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)
1123 @param EAX Lower 32-bits of MSR value.
1124 @param EDX Upper 32-bits of MSR value.
1125
1126 <b>Example usage</b>
1127 @code
1128 UINT64 Msr;
1129
1130 Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
1131 AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
1132 @endcode
1133 @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.
1134 **/
1135 #define MSR_P6_LASTINTFROMIP 0x000001DD
1136
1137
1138 /**
1139
1140
1141 @param ECX MSR_P6_LASTINTTOIP (0x000001DE)
1142 @param EAX Lower 32-bits of MSR value.
1143 @param EDX Upper 32-bits of MSR value.
1144
1145 <b>Example usage</b>
1146 @code
1147 UINT64 Msr;
1148
1149 Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
1150 AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
1151 @endcode
1152 @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.
1153 **/
1154 #define MSR_P6_LASTINTTOIP 0x000001DE
1155
1156 /**
1157
1158
1159 @param ECX MSR_P6_MTRRPHYSBASEn
1160 @param EAX Lower 32-bits of MSR value.
1161 @param EDX Upper 32-bits of MSR value.
1162
1163 <b>Example usage</b>
1164 @code
1165 UINT64 Msr;
1166
1167 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
1168 AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
1169 @endcode
1170 @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
1171 MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
1172 MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
1173 MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
1174 MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
1175 MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
1176 MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
1177 MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
1178 @{
1179 **/
1180 #define MSR_P6_MTRRPHYSBASE0 0x00000200
1181 #define MSR_P6_MTRRPHYSBASE1 0x00000202
1182 #define MSR_P6_MTRRPHYSBASE2 0x00000204
1183 #define MSR_P6_MTRRPHYSBASE3 0x00000206
1184 #define MSR_P6_MTRRPHYSBASE4 0x00000208
1185 #define MSR_P6_MTRRPHYSBASE5 0x0000020A
1186 #define MSR_P6_MTRRPHYSBASE6 0x0000020C
1187 #define MSR_P6_MTRRPHYSBASE7 0x0000020E
1188 /// @}
1189
1190
1191 /**
1192
1193
1194 @param ECX MSR_P6_MTRRPHYSMASKn
1195 @param EAX Lower 32-bits of MSR value.
1196 @param EDX Upper 32-bits of MSR value.
1197
1198 <b>Example usage</b>
1199 @code
1200 UINT64 Msr;
1201
1202 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
1203 AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
1204 @endcode
1205 @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
1206 MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
1207 MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
1208 MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
1209 MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
1210 MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
1211 MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
1212 MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
1213 @{
1214 **/
1215 #define MSR_P6_MTRRPHYSMASK0 0x00000201
1216 #define MSR_P6_MTRRPHYSMASK1 0x00000203
1217 #define MSR_P6_MTRRPHYSMASK2 0x00000205
1218 #define MSR_P6_MTRRPHYSMASK3 0x00000207
1219 #define MSR_P6_MTRRPHYSMASK4 0x00000209
1220 #define MSR_P6_MTRRPHYSMASK5 0x0000020B
1221 #define MSR_P6_MTRRPHYSMASK6 0x0000020D
1222 #define MSR_P6_MTRRPHYSMASK7 0x0000020F
1223 /// @}
1224
1225
1226 /**
1227
1228
1229 @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)
1230 @param EAX Lower 32-bits of MSR value.
1231 @param EDX Upper 32-bits of MSR value.
1232
1233 <b>Example usage</b>
1234 @code
1235 UINT64 Msr;
1236
1237 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
1238 AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
1239 @endcode
1240 @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
1241 **/
1242 #define MSR_P6_MTRRFIX64K_00000 0x00000250
1243
1244
1245 /**
1246
1247
1248 @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)
1249 @param EAX Lower 32-bits of MSR value.
1250 @param EDX Upper 32-bits of MSR value.
1251
1252 <b>Example usage</b>
1253 @code
1254 UINT64 Msr;
1255
1256 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
1257 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
1258 @endcode
1259 @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
1260 **/
1261 #define MSR_P6_MTRRFIX16K_80000 0x00000258
1262
1263
1264 /**
1265
1266
1267 @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)
1268 @param EAX Lower 32-bits of MSR value.
1269 @param EDX Upper 32-bits of MSR value.
1270
1271 <b>Example usage</b>
1272 @code
1273 UINT64 Msr;
1274
1275 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
1276 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
1277 @endcode
1278 @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
1279 **/
1280 #define MSR_P6_MTRRFIX16K_A0000 0x00000259
1281
1282
1283 /**
1284
1285
1286 @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)
1287 @param EAX Lower 32-bits of MSR value.
1288 @param EDX Upper 32-bits of MSR value.
1289
1290 <b>Example usage</b>
1291 @code
1292 UINT64 Msr;
1293
1294 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
1295 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
1296 @endcode
1297 @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
1298 **/
1299 #define MSR_P6_MTRRFIX4K_C0000 0x00000268
1300
1301
1302 /**
1303
1304
1305 @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)
1306 @param EAX Lower 32-bits of MSR value.
1307 @param EDX Upper 32-bits of MSR value.
1308
1309 <b>Example usage</b>
1310 @code
1311 UINT64 Msr;
1312
1313 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
1314 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
1315 @endcode
1316 @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
1317 **/
1318 #define MSR_P6_MTRRFIX4K_C8000 0x00000269
1319
1320
1321 /**
1322
1323
1324 @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
1325 @param EAX Lower 32-bits of MSR value.
1326 @param EDX Upper 32-bits of MSR value.
1327
1328 <b>Example usage</b>
1329 @code
1330 UINT64 Msr;
1331
1332 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
1333 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
1334 @endcode
1335 @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
1336 **/
1337 #define MSR_P6_MTRRFIX4K_D0000 0x0000026A
1338
1339
1340 /**
1341
1342
1343 @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
1344 @param EAX Lower 32-bits of MSR value.
1345 @param EDX Upper 32-bits of MSR value.
1346
1347 <b>Example usage</b>
1348 @code
1349 UINT64 Msr;
1350
1351 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
1352 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
1353 @endcode
1354 @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
1355 **/
1356 #define MSR_P6_MTRRFIX4K_D8000 0x0000026B
1357
1358
1359 /**
1360
1361
1362 @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
1363 @param EAX Lower 32-bits of MSR value.
1364 @param EDX Upper 32-bits of MSR value.
1365
1366 <b>Example usage</b>
1367 @code
1368 UINT64 Msr;
1369
1370 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
1371 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
1372 @endcode
1373 @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
1374 **/
1375 #define MSR_P6_MTRRFIX4K_E0000 0x0000026C
1376
1377
1378 /**
1379
1380
1381 @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
1382 @param EAX Lower 32-bits of MSR value.
1383 @param EDX Upper 32-bits of MSR value.
1384
1385 <b>Example usage</b>
1386 @code
1387 UINT64 Msr;
1388
1389 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
1390 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
1391 @endcode
1392 @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
1393 **/
1394 #define MSR_P6_MTRRFIX4K_E8000 0x0000026D
1395
1396
1397 /**
1398
1399
1400 @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
1401 @param EAX Lower 32-bits of MSR value.
1402 @param EDX Upper 32-bits of MSR value.
1403
1404 <b>Example usage</b>
1405 @code
1406 UINT64 Msr;
1407
1408 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
1409 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
1410 @endcode
1411 @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
1412 **/
1413 #define MSR_P6_MTRRFIX4K_F0000 0x0000026E
1414
1415
1416 /**
1417
1418
1419 @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
1420 @param EAX Lower 32-bits of MSR value.
1421 @param EDX Upper 32-bits of MSR value.
1422
1423 <b>Example usage</b>
1424 @code
1425 UINT64 Msr;
1426
1427 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
1428 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
1429 @endcode
1430 @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
1431 **/
1432 #define MSR_P6_MTRRFIX4K_F8000 0x0000026F
1433
1434
1435 /**
1436
1437
1438 @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)
1439 @param EAX Lower 32-bits of MSR value.
1440 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1441 @param EDX Upper 32-bits of MSR value.
1442 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1443
1444 <b>Example usage</b>
1445 @code
1446 MSR_P6_MTRRDEFTYPE_REGISTER Msr;
1447
1448 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
1449 AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
1450 @endcode
1451 @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.
1452 **/
1453 #define MSR_P6_MTRRDEFTYPE 0x000002FF
1454
1455 /**
1456 MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
1457 **/
1458 typedef union {
1459 ///
1460 /// Individual bit fields
1461 ///
1462 struct {
1463 ///
1464 /// [Bits 2:0] Default memory type.
1465 ///
1466 UINT32 Type:3;
1467 UINT32 Reserved1:7;
1468 ///
1469 /// [Bit 10] Fixed MTRR enable.
1470 ///
1471 UINT32 FE:1;
1472 ///
1473 /// [Bit 11] MTRR Enable.
1474 ///
1475 UINT32 E:1;
1476 UINT32 Reserved2:20;
1477 UINT32 Reserved3:32;
1478 } Bits;
1479 ///
1480 /// All bit fields as a 32-bit value
1481 ///
1482 UINT32 Uint32;
1483 ///
1484 /// All bit fields as a 64-bit value
1485 ///
1486 UINT64 Uint64;
1487 } MSR_P6_MTRRDEFTYPE_REGISTER;
1488
1489
1490 /**
1491
1492
1493 @param ECX MSR_P6_MC0_CTL (0x00000400)
1494 @param EAX Lower 32-bits of MSR value.
1495 @param EDX Upper 32-bits of MSR value.
1496
1497 <b>Example usage</b>
1498 @code
1499 UINT64 Msr;
1500
1501 Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
1502 AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
1503 @endcode
1504 @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.
1505 MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.
1506 MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.
1507 MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.
1508 MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.
1509 @{
1510 **/
1511 #define MSR_P6_MC0_CTL 0x00000400
1512 #define MSR_P6_MC1_CTL 0x00000404
1513 #define MSR_P6_MC2_CTL 0x00000408
1514 #define MSR_P6_MC3_CTL 0x00000410
1515 #define MSR_P6_MC4_CTL 0x0000040C
1516 /// @}
1517
1518
1519 /**
1520
1521 Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
1522 except bits 0, 4, 57, and 61 are hardcoded to 1.
1523
1524 @param ECX MSR_P6_MCn_STATUS
1525 @param EAX Lower 32-bits of MSR value.
1526 Described by the type MSR_P6_MC_STATUS_REGISTER.
1527 @param EDX Upper 32-bits of MSR value.
1528 Described by the type MSR_P6_MC_STATUS_REGISTER.
1529
1530 <b>Example usage</b>
1531 @code
1532 MSR_P6_MC_STATUS_REGISTER Msr;
1533
1534 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
1535 AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
1536 @endcode
1537 @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.
1538 MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.
1539 MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.
1540 MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.
1541 MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.
1542 @{
1543 **/
1544 #define MSR_P6_MC0_STATUS 0x00000401
1545 #define MSR_P6_MC1_STATUS 0x00000405
1546 #define MSR_P6_MC2_STATUS 0x00000409
1547 #define MSR_P6_MC3_STATUS 0x00000411
1548 #define MSR_P6_MC4_STATUS 0x0000040D
1549 /// @}
1550
1551 /**
1552 MSR information returned for MSR index #MSR_P6_MC0_STATUS to
1553 #MSR_P6_MC4_STATUS
1554 **/
1555 typedef union {
1556 ///
1557 /// Individual bit fields
1558 ///
1559 struct {
1560 ///
1561 /// [Bits 15:0] MC_STATUS_MCACOD.
1562 ///
1563 UINT32 MC_STATUS_MCACOD:16;
1564 ///
1565 /// [Bits 31:16] MC_STATUS_MSCOD.
1566 ///
1567 UINT32 MC_STATUS_MSCOD:16;
1568 UINT32 Reserved:25;
1569 ///
1570 /// [Bit 57] MC_STATUS_DAM.
1571 ///
1572 UINT32 MC_STATUS_DAM:1;
1573 ///
1574 /// [Bit 58] MC_STATUS_ADDRV.
1575 ///
1576 UINT32 MC_STATUS_ADDRV:1;
1577 ///
1578 /// [Bit 59] MC_STATUS_MISCV.
1579 ///
1580 UINT32 MC_STATUS_MISCV:1;
1581 ///
1582 /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
1583 /// hardcoded to 1.).
1584 ///
1585 UINT32 MC_STATUS_EN:1;
1586 ///
1587 /// [Bit 61] MC_STATUS_UC.
1588 ///
1589 UINT32 MC_STATUS_UC:1;
1590 ///
1591 /// [Bit 62] MC_STATUS_O.
1592 ///
1593 UINT32 MC_STATUS_O:1;
1594 ///
1595 /// [Bit 63] MC_STATUS_V.
1596 ///
1597 UINT32 MC_STATUS_V:1;
1598 } Bits;
1599 ///
1600 /// All bit fields as a 64-bit value
1601 ///
1602 UINT64 Uint64;
1603 } MSR_P6_MC_STATUS_REGISTER;
1604
1605
1606 /**
1607
1608 MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
1609
1610 @param ECX MSR_P6_MC0_ADDR (0x00000402)
1611 @param EAX Lower 32-bits of MSR value.
1612 @param EDX Upper 32-bits of MSR value.
1613
1614 <b>Example usage</b>
1615 @code
1616 UINT64 Msr;
1617
1618 Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
1619 AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
1620 @endcode
1621 @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.
1622 MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.
1623 MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.
1624 MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.
1625 MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.
1626 @{
1627 **/
1628 #define MSR_P6_MC0_ADDR 0x00000402
1629 #define MSR_P6_MC1_ADDR 0x00000406
1630 #define MSR_P6_MC2_ADDR 0x0000040A
1631 #define MSR_P6_MC3_ADDR 0x00000412
1632 #define MSR_P6_MC4_ADDR 0x0000040E
1633 /// @}
1634
1635
1636 /**
1637 Defined in MCA architecture but not implemented in the P6 family processors.
1638
1639 @param ECX MSR_P6_MC0_MISC (0x00000403)
1640 @param EAX Lower 32-bits of MSR value.
1641 @param EDX Upper 32-bits of MSR value.
1642
1643 <b>Example usage</b>
1644 @code
1645 UINT64 Msr;
1646
1647 Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
1648 AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
1649 @endcode
1650 @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.
1651 MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.
1652 MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.
1653 MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.
1654 MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.
1655 @{
1656 **/
1657 #define MSR_P6_MC0_MISC 0x00000403
1658 #define MSR_P6_MC1_MISC 0x00000407
1659 #define MSR_P6_MC2_MISC 0x0000040B
1660 #define MSR_P6_MC3_MISC 0x00000413
1661 #define MSR_P6_MC4_MISC 0x0000040F
1662 /// @}
1663
1664 #endif
EFI Development Kit II mirror for PVE