2 MSR Definitions for P6 Family Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
27 #include <Register/ArchitecturalMsr.h>
30 Is P6 Family Processors?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x03 || \
42 DisplayModel == 0x05 || \
43 DisplayModel == 0x07 || \
44 DisplayModel == 0x08 || \
45 DisplayModel == 0x0A || \
46 DisplayModel == 0x0B \
51 See Section 2.22, "MSRs in Pentium Processors.".
53 @param ECX MSR_P6_P5_MC_ADDR (0x00000000)
54 @param EAX Lower 32-bits of MSR value.
55 @param EDX Upper 32-bits of MSR value.
61 Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
62 AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
64 @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
66 #define MSR_P6_P5_MC_ADDR 0x00000000
70 See Section 2.22, "MSRs in Pentium Processors.".
72 @param ECX MSR_P6_P5_MC_TYPE (0x00000001)
73 @param EAX Lower 32-bits of MSR value.
74 @param EDX Upper 32-bits of MSR value.
80 Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
81 AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
83 @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
85 #define MSR_P6_P5_MC_TYPE 0x00000001
89 See Section 17.17, "Time-Stamp Counter.".
91 @param ECX MSR_P6_TSC (0x00000010)
92 @param EAX Lower 32-bits of MSR value.
93 @param EDX Upper 32-bits of MSR value.
99 Msr = AsmReadMsr64 (MSR_P6_TSC);
100 AsmWriteMsr64 (MSR_P6_TSC, Msr);
102 @note MSR_P6_TSC is defined as TSC in SDM.
104 #define MSR_P6_TSC 0x00000010
108 Platform ID (R) The operating system can use this MSR to determine "slot"
109 information for the processor and the proper microcode update to load.
111 @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)
112 @param EAX Lower 32-bits of MSR value.
113 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
114 @param EDX Upper 32-bits of MSR value.
115 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
119 MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;
121 Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
123 @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
125 #define MSR_P6_IA32_PLATFORM_ID 0x00000017
128 MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
132 /// Individual bit fields
138 /// [Bits 52:50] Platform Id (R) Contains information concerning the
139 /// intended platform for the processor.
142 /// 0 0 0 Processor Flag 0.
143 /// 0 0 1 Processor Flag 1
144 /// 0 1 0 Processor Flag 2
145 /// 0 1 1 Processor Flag 3
146 /// 1 0 0 Processor Flag 4
147 /// 1 0 1 Processor Flag 5
148 /// 1 1 0 Processor Flag 6
149 /// 1 1 1 Processor Flag 7
153 /// [Bits 56:53] L2 Cache Latency Read.
155 UINT32 L2CacheLatencyRead
:4;
158 /// [Bit 60] Clock Frequency Ratio Read.
160 UINT32 ClockFrequencyRatioRead
:1;
164 /// All bit fields as a 64-bit value
167 } MSR_P6_IA32_PLATFORM_ID_REGISTER
;
171 Section 10.4.4, "Local APIC Status and Location.".
173 @param ECX MSR_P6_APIC_BASE (0x0000001B)
174 @param EAX Lower 32-bits of MSR value.
175 Described by the type MSR_P6_APIC_BASE_REGISTER.
176 @param EDX Upper 32-bits of MSR value.
177 Described by the type MSR_P6_APIC_BASE_REGISTER.
181 MSR_P6_APIC_BASE_REGISTER Msr;
183 Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
184 AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
186 @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
188 #define MSR_P6_APIC_BASE 0x0000001B
191 MSR information returned for MSR index #MSR_P6_APIC_BASE
195 /// Individual bit fields
200 /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
205 /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
210 /// [Bits 31:12] APIC Base Address.
216 /// All bit fields as a 32-bit value
220 /// All bit fields as a 64-bit value
223 } MSR_P6_APIC_BASE_REGISTER
;
227 Processor Hard Power-On Configuration (R/W) Enables and disables processor
228 features; (R) indicates current processor configuration.
230 @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)
231 @param EAX Lower 32-bits of MSR value.
232 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
233 @param EDX Upper 32-bits of MSR value.
234 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
238 MSR_P6_EBL_CR_POWERON_REGISTER Msr;
240 Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
241 AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
243 @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
245 #define MSR_P6_EBL_CR_POWERON 0x0000002A
248 MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
252 /// Individual bit fields
257 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
259 UINT32 DataErrorCheckingEnable
:1;
261 /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
262 /// 1 = Enabled 0 = Disabled.
264 UINT32 ResponseErrorCheckingEnable
:1;
266 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
268 UINT32 AERR_DriveEnable
:1;
270 /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
273 UINT32 BERR_Enable
:1;
276 /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
277 /// Enabled 0 = Disabled.
279 UINT32 BERR_DriverEnable
:1;
281 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
283 UINT32 BINIT_DriverEnable
:1;
285 /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
287 UINT32 OutputTriStateEnable
:1;
289 /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
291 UINT32 ExecuteBIST
:1;
293 /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
295 UINT32 AERR_ObservationEnabled
:1;
298 /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
300 UINT32 BINIT_ObservationEnabled
:1;
302 /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
304 UINT32 InOrderQueueDepth
:1;
306 /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
308 UINT32 ResetVector
:1;
310 /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
312 UINT32 FRCModeEnable
:1;
314 /// [Bits 17:16] APIC Cluster ID (R).
316 UINT32 APICClusterID
:2;
318 /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
319 /// 133MHz 11 = Reserved.
321 UINT32 SystemBusFrequency
:2;
323 /// [Bits 21:20] Symmetric Arbitration ID (R).
325 UINT32 SymmetricArbitrationID
:2;
327 /// [Bits 25:22] Clock Frequency Ratio (R).
329 UINT32 ClockFrequencyRatio
:4;
331 /// [Bit 26] Low Power Mode Enable (R/W).
333 UINT32 LowPowerModeEnable
:1;
335 /// [Bit 27] Clock Frequency Ratio.
337 UINT32 ClockFrequencyRatio1
:1;
342 /// All bit fields as a 32-bit value
346 /// All bit fields as a 64-bit value
349 } MSR_P6_EBL_CR_POWERON_REGISTER
;
353 Test Control Register.
355 @param ECX MSR_P6_TEST_CTL (0x00000033)
356 @param EAX Lower 32-bits of MSR value.
357 Described by the type MSR_P6_TEST_CTL_REGISTER.
358 @param EDX Upper 32-bits of MSR value.
359 Described by the type MSR_P6_TEST_CTL_REGISTER.
363 MSR_P6_TEST_CTL_REGISTER Msr;
365 Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
366 AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
368 @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
370 #define MSR_P6_TEST_CTL 0x00000033
373 MSR information returned for MSR index #MSR_P6_TEST_CTL
377 /// Individual bit fields
382 /// [Bit 30] Streaming Buffer Disable.
384 UINT32 StreamingBufferDisable
:1;
386 /// [Bit 31] Disable LOCK# Assertion for split locked access.
388 UINT32 Disable_LOCK
:1;
392 /// All bit fields as a 32-bit value
396 /// All bit fields as a 64-bit value
399 } MSR_P6_TEST_CTL_REGISTER
;
403 BIOS Update Trigger Register.
405 @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)
406 @param EAX Lower 32-bits of MSR value.
407 @param EDX Upper 32-bits of MSR value.
413 Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
414 AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
416 @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
418 #define MSR_P6_BIOS_UPDT_TRIG 0x00000079
422 Chunk n data register D[63:0]: used to write to and read from the L2.
424 @param ECX MSR_P6_BBL_CR_Dn
425 @param EAX Lower 32-bits of MSR value.
426 @param EDX Upper 32-bits of MSR value.
432 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
433 AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
435 @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
436 MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
437 MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
440 #define MSR_P6_BBL_CR_D0 0x00000088
441 #define MSR_P6_BBL_CR_D1 0x00000089
442 #define MSR_P6_BBL_CR_D2 0x0000008A
447 BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
448 write to and read from the L2 depending on the usage model.
450 @param ECX MSR_P6_BIOS_SIGN (0x0000008B)
451 @param EAX Lower 32-bits of MSR value.
452 @param EDX Upper 32-bits of MSR value.
458 Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
459 AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
461 @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
463 #define MSR_P6_BIOS_SIGN 0x0000008B
469 @param ECX MSR_P6_PERFCTR0 (0x000000C1)
470 @param EAX Lower 32-bits of MSR value.
471 @param EDX Upper 32-bits of MSR value.
477 Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
478 AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
480 @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
481 MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
484 #define MSR_P6_PERFCTR0 0x000000C1
485 #define MSR_P6_PERFCTR1 0x000000C2
492 @param ECX MSR_P6_MTRRCAP (0x000000FE)
493 @param EAX Lower 32-bits of MSR value.
494 @param EDX Upper 32-bits of MSR value.
500 Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
501 AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
503 @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
505 #define MSR_P6_MTRRCAP 0x000000FE
509 Address register: used to send specified address (A31-A3) to L2 during cache
510 initialization accesses.
512 @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)
513 @param EAX Lower 32-bits of MSR value.
514 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
515 @param EDX Upper 32-bits of MSR value.
516 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
520 MSR_P6_BBL_CR_ADDR_REGISTER Msr;
522 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
523 AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
525 @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
527 #define MSR_P6_BBL_CR_ADDR 0x00000116
530 MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
534 /// Individual bit fields
539 /// [Bits 31:3] Address bits
545 /// All bit fields as a 32-bit value
549 /// All bit fields as a 64-bit value
552 } MSR_P6_BBL_CR_ADDR_REGISTER
;
556 Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
558 @param ECX MSR_P6_BBL_CR_DECC (0x00000118)
559 @param EAX Lower 32-bits of MSR value.
560 @param EDX Upper 32-bits of MSR value.
566 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
567 AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
569 @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
571 #define MSR_P6_BBL_CR_DECC 0x00000118
575 Control register: used to program L2 commands to be issued via cache
576 configuration accesses mechanism. Also receives L2 lookup response.
578 @param ECX MSR_P6_BBL_CR_CTL (0x00000119)
579 @param EAX Lower 32-bits of MSR value.
580 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
581 @param EDX Upper 32-bits of MSR value.
582 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
586 MSR_P6_BBL_CR_CTL_REGISTER Msr;
588 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
589 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
591 @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
593 #define MSR_P6_BBL_CR_CTL 0x00000119
596 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
600 /// Individual bit fields
604 /// [Bits 4:0] L2 Command
605 /// Data Read w/ LRU update (RLU)
606 /// Tag Read w/ Data Read (TRR)
608 /// L2 Control Register Read (CR)
609 /// L2 Control Register Write (CW)
610 /// Tag Write w/ Data Read (TWR)
611 /// Tag Write w/ Data Write (TWW)
616 /// [Bits 6:5] State to L2
621 /// [Bits 9:8] Way to L2.
625 /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
629 /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
633 /// [Bits 15:14] State from L2.
635 UINT32 StateFromL2
:2;
643 /// [Bits 20:19] User supplied ECC.
647 /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
649 UINT32 ProcessorNumber
:1;
654 /// All bit fields as a 32-bit value
658 /// All bit fields as a 64-bit value
661 } MSR_P6_BBL_CR_CTL_REGISTER
;
665 Trigger register: used to initiate a cache configuration accesses access,
666 Write only with Data = 0.
668 @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)
669 @param EAX Lower 32-bits of MSR value.
670 @param EDX Upper 32-bits of MSR value.
676 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
677 AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
679 @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
681 #define MSR_P6_BBL_CR_TRIG 0x0000011A
685 Busy register: indicates when a cache configuration accesses L2 command is
686 in progress. D[0] = 1 = BUSY.
688 @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)
689 @param EAX Lower 32-bits of MSR value.
690 @param EDX Upper 32-bits of MSR value.
696 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
697 AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
699 @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.
701 #define MSR_P6_BBL_CR_BUSY 0x0000011B
705 Control register 3: used to configure the L2 Cache.
707 @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)
708 @param EAX Lower 32-bits of MSR value.
709 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
710 @param EDX Upper 32-bits of MSR value.
711 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
715 MSR_P6_BBL_CR_CTL3_REGISTER Msr;
717 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
718 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
720 @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.
722 #define MSR_P6_BBL_CR_CTL3 0x0000011E
725 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
729 /// Individual bit fields
733 /// [Bit 0] L2 Configured (read/write ).
735 UINT32 L2Configured
:1;
737 /// [Bits 4:1] L2 Cache Latency (read/write).
739 UINT32 L2CacheLatency
:4;
741 /// [Bit 5] ECC Check Enable (read/write).
743 UINT32 ECCCheckEnable
:1;
745 /// [Bit 6] Address Parity Check Enable (read/write).
747 UINT32 AddressParityCheckEnable
:1;
749 /// [Bit 7] CRTN Parity Check Enable (read/write).
751 UINT32 CRTNParityCheckEnable
:1;
753 /// [Bit 8] L2 Enabled (read/write).
757 /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
760 UINT32 L2Associativity
:2;
762 /// [Bits 12:11] Number of L2 banks (read only).
766 /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
767 /// 1MByte 2MByte 4MBytes.
769 UINT32 CacheSizePerBank
:5;
771 /// [Bit 18] Cache State error checking enable (read/write).
773 UINT32 CacheStateErrorEnable
:1;
776 /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
777 /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
779 UINT32 L2AddressRange
:3;
781 /// [Bit 23] L2 Hardware Disable (read only).
783 UINT32 L2HardwareDisable
:1;
786 /// [Bit 25] Cache bus fraction (read only).
788 UINT32 CacheBusFraction
:1;
793 /// All bit fields as a 32-bit value
797 /// All bit fields as a 64-bit value
800 } MSR_P6_BBL_CR_CTL3_REGISTER
;
804 CS register target for CPL 0 code.
806 @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)
807 @param EAX Lower 32-bits of MSR value.
808 @param EDX Upper 32-bits of MSR value.
814 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
815 AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
817 @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.
819 #define MSR_P6_SYSENTER_CS_MSR 0x00000174
823 Stack pointer for CPL 0 stack.
825 @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)
826 @param EAX Lower 32-bits of MSR value.
827 @param EDX Upper 32-bits of MSR value.
833 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
834 AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
836 @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.
838 #define MSR_P6_SYSENTER_ESP_MSR 0x00000175
842 CPL 0 code entry point.
844 @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)
845 @param EAX Lower 32-bits of MSR value.
846 @param EDX Upper 32-bits of MSR value.
852 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
853 AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
855 @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.
857 #define MSR_P6_SYSENTER_EIP_MSR 0x00000176
863 @param ECX MSR_P6_MCG_CAP (0x00000179)
864 @param EAX Lower 32-bits of MSR value.
865 @param EDX Upper 32-bits of MSR value.
871 Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
872 AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
874 @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.
876 #define MSR_P6_MCG_CAP 0x00000179
882 @param ECX MSR_P6_MCG_STATUS (0x0000017A)
883 @param EAX Lower 32-bits of MSR value.
884 @param EDX Upper 32-bits of MSR value.
890 Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
891 AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
893 @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.
895 #define MSR_P6_MCG_STATUS 0x0000017A
901 @param ECX MSR_P6_MCG_CTL (0x0000017B)
902 @param EAX Lower 32-bits of MSR value.
903 @param EDX Upper 32-bits of MSR value.
909 Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
910 AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
912 @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.
914 #define MSR_P6_MCG_CTL 0x0000017B
920 @param ECX MSR_P6_PERFEVTSELn
921 @param EAX Lower 32-bits of MSR value.
922 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
923 @param EDX Upper 32-bits of MSR value.
924 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
928 MSR_P6_PERFEVTSEL_REGISTER Msr;
930 Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
931 AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
933 @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.
934 MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.
937 #define MSR_P6_PERFEVTSEL0 0x00000186
938 #define MSR_P6_PERFEVTSEL1 0x00000187
942 MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
947 /// Individual bit fields
951 /// [Bits 7:0] Event Select Refer to Performance Counter section for a
952 /// list of event encodings.
954 UINT32 EventSelect
:8;
956 /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
957 /// all count options.
961 /// [Bit 16] USER Controls the counting of events at Privilege levels of
966 /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
970 /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
974 /// [Bit 19] PC Enabled the signaling of performance counter overflow via
979 /// [Bit 20] INT Enables the signaling of counter overflow via input to
980 /// APIC 1 = Enable 0 = Disable.
985 /// [Bit 22] ENABLE Enables the counting of performance events in both
986 /// counters 1 = Enable 0 = Disable.
990 /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
995 /// [Bits 31:24] CMASK (Counter Mask).
1001 /// All bit fields as a 32-bit value
1005 /// All bit fields as a 64-bit value
1008 } MSR_P6_PERFEVTSEL_REGISTER
;
1014 @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)
1015 @param EAX Lower 32-bits of MSR value.
1016 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
1017 @param EDX Upper 32-bits of MSR value.
1018 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
1020 <b>Example usage</b>
1022 MSR_P6_DEBUGCTLMSR_REGISTER Msr;
1024 Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
1025 AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
1027 @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.
1029 #define MSR_P6_DEBUGCTLMSR 0x000001D9
1032 MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
1036 /// Individual bit fields
1040 /// [Bit 0] Enable/Disable Last Branch Records.
1044 /// [Bit 1] Branch Trap Flag.
1048 /// [Bit 2] Performance Monitoring/Break Point Pins.
1052 /// [Bit 3] Performance Monitoring/Break Point Pins.
1056 /// [Bit 4] Performance Monitoring/Break Point Pins.
1060 /// [Bit 5] Performance Monitoring/Break Point Pins.
1064 /// [Bit 6] Enable/Disable Execution Trace Messages.
1067 UINT32 Reserved1
:25;
1068 UINT32 Reserved2
:32;
1071 /// All bit fields as a 32-bit value
1075 /// All bit fields as a 64-bit value
1078 } MSR_P6_DEBUGCTLMSR_REGISTER
;
1084 @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)
1085 @param EAX Lower 32-bits of MSR value.
1086 @param EDX Upper 32-bits of MSR value.
1088 <b>Example usage</b>
1092 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
1093 AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
1095 @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.
1097 #define MSR_P6_LASTBRANCHFROMIP 0x000001DB
1103 @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)
1104 @param EAX Lower 32-bits of MSR value.
1105 @param EDX Upper 32-bits of MSR value.
1107 <b>Example usage</b>
1111 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
1112 AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
1114 @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.
1116 #define MSR_P6_LASTBRANCHTOIP 0x000001DC
1122 @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)
1123 @param EAX Lower 32-bits of MSR value.
1124 @param EDX Upper 32-bits of MSR value.
1126 <b>Example usage</b>
1130 Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
1131 AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
1133 @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.
1135 #define MSR_P6_LASTINTFROMIP 0x000001DD
1141 @param ECX MSR_P6_LASTINTTOIP (0x000001DE)
1142 @param EAX Lower 32-bits of MSR value.
1143 @param EDX Upper 32-bits of MSR value.
1145 <b>Example usage</b>
1149 Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
1150 AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
1152 @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.
1154 #define MSR_P6_LASTINTTOIP 0x000001DE
1159 @param ECX MSR_P6_MTRRPHYSBASEn
1160 @param EAX Lower 32-bits of MSR value.
1161 @param EDX Upper 32-bits of MSR value.
1163 <b>Example usage</b>
1167 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
1168 AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
1170 @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
1171 MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
1172 MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
1173 MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
1174 MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
1175 MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
1176 MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
1177 MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
1180 #define MSR_P6_MTRRPHYSBASE0 0x00000200
1181 #define MSR_P6_MTRRPHYSBASE1 0x00000202
1182 #define MSR_P6_MTRRPHYSBASE2 0x00000204
1183 #define MSR_P6_MTRRPHYSBASE3 0x00000206
1184 #define MSR_P6_MTRRPHYSBASE4 0x00000208
1185 #define MSR_P6_MTRRPHYSBASE5 0x0000020A
1186 #define MSR_P6_MTRRPHYSBASE6 0x0000020C
1187 #define MSR_P6_MTRRPHYSBASE7 0x0000020E
1194 @param ECX MSR_P6_MTRRPHYSMASKn
1195 @param EAX Lower 32-bits of MSR value.
1196 @param EDX Upper 32-bits of MSR value.
1198 <b>Example usage</b>
1202 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
1203 AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
1205 @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
1206 MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
1207 MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
1208 MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
1209 MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
1210 MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
1211 MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
1212 MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
1215 #define MSR_P6_MTRRPHYSMASK0 0x00000201
1216 #define MSR_P6_MTRRPHYSMASK1 0x00000203
1217 #define MSR_P6_MTRRPHYSMASK2 0x00000205
1218 #define MSR_P6_MTRRPHYSMASK3 0x00000207
1219 #define MSR_P6_MTRRPHYSMASK4 0x00000209
1220 #define MSR_P6_MTRRPHYSMASK5 0x0000020B
1221 #define MSR_P6_MTRRPHYSMASK6 0x0000020D
1222 #define MSR_P6_MTRRPHYSMASK7 0x0000020F
1229 @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)
1230 @param EAX Lower 32-bits of MSR value.
1231 @param EDX Upper 32-bits of MSR value.
1233 <b>Example usage</b>
1237 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
1238 AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
1240 @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
1242 #define MSR_P6_MTRRFIX64K_00000 0x00000250
1248 @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)
1249 @param EAX Lower 32-bits of MSR value.
1250 @param EDX Upper 32-bits of MSR value.
1252 <b>Example usage</b>
1256 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
1257 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
1259 @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
1261 #define MSR_P6_MTRRFIX16K_80000 0x00000258
1267 @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)
1268 @param EAX Lower 32-bits of MSR value.
1269 @param EDX Upper 32-bits of MSR value.
1271 <b>Example usage</b>
1275 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
1276 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
1278 @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
1280 #define MSR_P6_MTRRFIX16K_A0000 0x00000259
1286 @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)
1287 @param EAX Lower 32-bits of MSR value.
1288 @param EDX Upper 32-bits of MSR value.
1290 <b>Example usage</b>
1294 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
1295 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
1297 @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
1299 #define MSR_P6_MTRRFIX4K_C0000 0x00000268
1305 @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)
1306 @param EAX Lower 32-bits of MSR value.
1307 @param EDX Upper 32-bits of MSR value.
1309 <b>Example usage</b>
1313 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
1314 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
1316 @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
1318 #define MSR_P6_MTRRFIX4K_C8000 0x00000269
1324 @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
1325 @param EAX Lower 32-bits of MSR value.
1326 @param EDX Upper 32-bits of MSR value.
1328 <b>Example usage</b>
1332 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
1333 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
1335 @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
1337 #define MSR_P6_MTRRFIX4K_D0000 0x0000026A
1343 @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
1344 @param EAX Lower 32-bits of MSR value.
1345 @param EDX Upper 32-bits of MSR value.
1347 <b>Example usage</b>
1351 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
1352 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
1354 @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
1356 #define MSR_P6_MTRRFIX4K_D8000 0x0000026B
1362 @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
1363 @param EAX Lower 32-bits of MSR value.
1364 @param EDX Upper 32-bits of MSR value.
1366 <b>Example usage</b>
1370 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
1371 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
1373 @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
1375 #define MSR_P6_MTRRFIX4K_E0000 0x0000026C
1381 @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
1382 @param EAX Lower 32-bits of MSR value.
1383 @param EDX Upper 32-bits of MSR value.
1385 <b>Example usage</b>
1389 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
1390 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
1392 @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
1394 #define MSR_P6_MTRRFIX4K_E8000 0x0000026D
1400 @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
1401 @param EAX Lower 32-bits of MSR value.
1402 @param EDX Upper 32-bits of MSR value.
1404 <b>Example usage</b>
1408 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
1409 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
1411 @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
1413 #define MSR_P6_MTRRFIX4K_F0000 0x0000026E
1419 @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
1420 @param EAX Lower 32-bits of MSR value.
1421 @param EDX Upper 32-bits of MSR value.
1423 <b>Example usage</b>
1427 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
1428 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
1430 @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
1432 #define MSR_P6_MTRRFIX4K_F8000 0x0000026F
1438 @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)
1439 @param EAX Lower 32-bits of MSR value.
1440 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1441 @param EDX Upper 32-bits of MSR value.
1442 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1444 <b>Example usage</b>
1446 MSR_P6_MTRRDEFTYPE_REGISTER Msr;
1448 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
1449 AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
1451 @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.
1453 #define MSR_P6_MTRRDEFTYPE 0x000002FF
1456 MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
1460 /// Individual bit fields
1464 /// [Bits 2:0] Default memory type.
1469 /// [Bit 10] Fixed MTRR enable.
1473 /// [Bit 11] MTRR Enable.
1476 UINT32 Reserved2
:20;
1477 UINT32 Reserved3
:32;
1480 /// All bit fields as a 32-bit value
1484 /// All bit fields as a 64-bit value
1487 } MSR_P6_MTRRDEFTYPE_REGISTER
;
1493 @param ECX MSR_P6_MC0_CTL (0x00000400)
1494 @param EAX Lower 32-bits of MSR value.
1495 @param EDX Upper 32-bits of MSR value.
1497 <b>Example usage</b>
1501 Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
1502 AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
1504 @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.
1505 MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.
1506 MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.
1507 MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.
1508 MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.
1511 #define MSR_P6_MC0_CTL 0x00000400
1512 #define MSR_P6_MC1_CTL 0x00000404
1513 #define MSR_P6_MC2_CTL 0x00000408
1514 #define MSR_P6_MC3_CTL 0x00000410
1515 #define MSR_P6_MC4_CTL 0x0000040C
1521 Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
1522 except bits 0, 4, 57, and 61 are hardcoded to 1.
1524 @param ECX MSR_P6_MCn_STATUS
1525 @param EAX Lower 32-bits of MSR value.
1526 Described by the type MSR_P6_MC_STATUS_REGISTER.
1527 @param EDX Upper 32-bits of MSR value.
1528 Described by the type MSR_P6_MC_STATUS_REGISTER.
1530 <b>Example usage</b>
1532 MSR_P6_MC_STATUS_REGISTER Msr;
1534 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
1535 AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
1537 @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.
1538 MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.
1539 MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.
1540 MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.
1541 MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.
1544 #define MSR_P6_MC0_STATUS 0x00000401
1545 #define MSR_P6_MC1_STATUS 0x00000405
1546 #define MSR_P6_MC2_STATUS 0x00000409
1547 #define MSR_P6_MC3_STATUS 0x00000411
1548 #define MSR_P6_MC4_STATUS 0x0000040D
1552 MSR information returned for MSR index #MSR_P6_MC0_STATUS to
1557 /// Individual bit fields
1561 /// [Bits 15:0] MC_STATUS_MCACOD.
1563 UINT32 MC_STATUS_MCACOD
:16;
1565 /// [Bits 31:16] MC_STATUS_MSCOD.
1567 UINT32 MC_STATUS_MSCOD
:16;
1570 /// [Bit 57] MC_STATUS_DAM.
1572 UINT32 MC_STATUS_DAM
:1;
1574 /// [Bit 58] MC_STATUS_ADDRV.
1576 UINT32 MC_STATUS_ADDRV
:1;
1578 /// [Bit 59] MC_STATUS_MISCV.
1580 UINT32 MC_STATUS_MISCV
:1;
1582 /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
1583 /// hardcoded to 1.).
1585 UINT32 MC_STATUS_EN
:1;
1587 /// [Bit 61] MC_STATUS_UC.
1589 UINT32 MC_STATUS_UC
:1;
1591 /// [Bit 62] MC_STATUS_O.
1593 UINT32 MC_STATUS_O
:1;
1595 /// [Bit 63] MC_STATUS_V.
1597 UINT32 MC_STATUS_V
:1;
1600 /// All bit fields as a 64-bit value
1603 } MSR_P6_MC_STATUS_REGISTER
;
1608 MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
1610 @param ECX MSR_P6_MC0_ADDR (0x00000402)
1611 @param EAX Lower 32-bits of MSR value.
1612 @param EDX Upper 32-bits of MSR value.
1614 <b>Example usage</b>
1618 Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
1619 AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
1621 @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.
1622 MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.
1623 MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.
1624 MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.
1625 MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.
1628 #define MSR_P6_MC0_ADDR 0x00000402
1629 #define MSR_P6_MC1_ADDR 0x00000406
1630 #define MSR_P6_MC2_ADDR 0x0000040A
1631 #define MSR_P6_MC3_ADDR 0x00000412
1632 #define MSR_P6_MC4_ADDR 0x0000040E
1637 Defined in MCA architecture but not implemented in the P6 family processors.
1639 @param ECX MSR_P6_MC0_MISC (0x00000403)
1640 @param EAX Lower 32-bits of MSR value.
1641 @param EDX Upper 32-bits of MSR value.
1643 <b>Example usage</b>
1647 Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
1648 AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
1650 @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.
1651 MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.
1652 MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.
1653 MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.
1654 MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.
1657 #define MSR_P6_MC0_MISC 0x00000403
1658 #define MSR_P6_MC1_MISC 0x00000407
1659 #define MSR_P6_MC2_MISC 0x0000040B
1660 #define MSR_P6_MC3_MISC 0x00000413
1661 #define MSR_P6_MC4_MISC 0x0000040F