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1 /** @file
2 MSR Definitions for P6 Family Processors.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
14
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21.
21
22 **/
23
24 #ifndef __P6_MSR_H__
25 #define __P6_MSR_H__
26
27 #include <Register/ArchitecturalMsr.h>
28
29 /**
30 Is P6 Family Processors?
31
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
34
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
37 **/
38 #define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
40 ( \
41 DisplayModel == 0x03 || \
42 DisplayModel == 0x05 || \
43 DisplayModel == 0x07 || \
44 DisplayModel == 0x08 || \
45 DisplayModel == 0x0A || \
46 DisplayModel == 0x0B \
47 ) \
48 )
49
50 /**
51 See Section 35.22, "MSRs in Pentium Processors.".
52
53 @param ECX MSR_P6_P5_MC_ADDR (0x00000000)
54 @param EAX Lower 32-bits of MSR value.
55 @param EDX Upper 32-bits of MSR value.
56
57 <b>Example usage</b>
58 @code
59 UINT64 Msr;
60
61 Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
62 AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
63 @endcode
64 @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
65 **/
66 #define MSR_P6_P5_MC_ADDR 0x00000000
67
68
69 /**
70 See Section 35.22, "MSRs in Pentium Processors.".
71
72 @param ECX MSR_P6_P5_MC_TYPE (0x00000001)
73 @param EAX Lower 32-bits of MSR value.
74 @param EDX Upper 32-bits of MSR value.
75
76 <b>Example usage</b>
77 @code
78 UINT64 Msr;
79
80 Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
81 AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
82 @endcode
83 @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
84 **/
85 #define MSR_P6_P5_MC_TYPE 0x00000001
86
87
88 /**
89 See Section 17.14, "Time-Stamp Counter.".
90
91 @param ECX MSR_P6_TSC (0x00000010)
92 @param EAX Lower 32-bits of MSR value.
93 @param EDX Upper 32-bits of MSR value.
94
95 <b>Example usage</b>
96 @code
97 UINT64 Msr;
98
99 Msr = AsmReadMsr64 (MSR_P6_TSC);
100 AsmWriteMsr64 (MSR_P6_TSC, Msr);
101 @endcode
102 @note MSR_P6_TSC is defined as TSC in SDM.
103 **/
104 #define MSR_P6_TSC 0x00000010
105
106
107 /**
108 Platform ID (R) The operating system can use this MSR to determine "slot"
109 information for the processor and the proper microcode update to load.
110
111 @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)
112 @param EAX Lower 32-bits of MSR value.
113 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
114 @param EDX Upper 32-bits of MSR value.
115 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
116
117 <b>Example usage</b>
118 @code
119 MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;
120
121 Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
122 @endcode
123 @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
124 **/
125 #define MSR_P6_IA32_PLATFORM_ID 0x00000017
126
127 /**
128 MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
129 **/
130 typedef union {
131 ///
132 /// Individual bit fields
133 ///
134 struct {
135 UINT32 Reserved1:32;
136 UINT32 Reserved2:18;
137 ///
138 /// [Bits 52:50] Platform Id (R) Contains information concerning the
139 /// intended platform for the processor.
140 ///
141 /// 52 51 50
142 /// 0 0 0 Processor Flag 0.
143 /// 0 0 1 Processor Flag 1
144 /// 0 1 0 Processor Flag 2
145 /// 0 1 1 Processor Flag 3
146 /// 1 0 0 Processor Flag 4
147 /// 1 0 1 Processor Flag 5
148 /// 1 1 0 Processor Flag 6
149 /// 1 1 1 Processor Flag 7
150 ///
151 UINT32 PlatformId:3;
152 ///
153 /// [Bits 56:53] L2 Cache Latency Read.
154 ///
155 UINT32 L2CacheLatencyRead:4;
156 UINT32 Reserved3:3;
157 ///
158 /// [Bit 60] Clock Frequency Ratio Read.
159 ///
160 UINT32 ClockFrequencyRatioRead:1;
161 UINT32 Reserved4:3;
162 } Bits;
163 ///
164 /// All bit fields as a 64-bit value
165 ///
166 UINT64 Uint64;
167 } MSR_P6_IA32_PLATFORM_ID_REGISTER;
168
169
170 /**
171 Section 10.4.4, "Local APIC Status and Location.".
172
173 @param ECX MSR_P6_APIC_BASE (0x0000001B)
174 @param EAX Lower 32-bits of MSR value.
175 Described by the type MSR_P6_APIC_BASE_REGISTER.
176 @param EDX Upper 32-bits of MSR value.
177 Described by the type MSR_P6_APIC_BASE_REGISTER.
178
179 <b>Example usage</b>
180 @code
181 MSR_P6_APIC_BASE_REGISTER Msr;
182
183 Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
184 AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
185 @endcode
186 @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
187 **/
188 #define MSR_P6_APIC_BASE 0x0000001B
189
190 /**
191 MSR information returned for MSR index #MSR_P6_APIC_BASE
192 **/
193 typedef union {
194 ///
195 /// Individual bit fields
196 ///
197 struct {
198 UINT32 Reserved1:8;
199 ///
200 /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
201 ///
202 UINT32 BSP:1;
203 UINT32 Reserved2:2;
204 ///
205 /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
206 /// Disabled.
207 ///
208 UINT32 EN:1;
209 ///
210 /// [Bits 31:12] APIC Base Address.
211 ///
212 UINT32 ApicBase:20;
213 UINT32 Reserved3:32;
214 } Bits;
215 ///
216 /// All bit fields as a 32-bit value
217 ///
218 UINT32 Uint32;
219 ///
220 /// All bit fields as a 64-bit value
221 ///
222 UINT64 Uint64;
223 } MSR_P6_APIC_BASE_REGISTER;
224
225
226 /**
227 Processor Hard Power-On Configuration (R/W) Enables and disables processor
228 features; (R) indicates current processor configuration.
229
230 @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)
231 @param EAX Lower 32-bits of MSR value.
232 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
233 @param EDX Upper 32-bits of MSR value.
234 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
235
236 <b>Example usage</b>
237 @code
238 MSR_P6_EBL_CR_POWERON_REGISTER Msr;
239
240 Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
241 AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
242 @endcode
243 @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
244 **/
245 #define MSR_P6_EBL_CR_POWERON 0x0000002A
246
247 /**
248 MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
249 **/
250 typedef union {
251 ///
252 /// Individual bit fields
253 ///
254 struct {
255 UINT32 Reserved1:1;
256 ///
257 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
258 ///
259 UINT32 DataErrorCheckingEnable:1;
260 ///
261 /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
262 /// 1 = Enabled 0 = Disabled.
263 ///
264 UINT32 ResponseErrorCheckingEnable:1;
265 ///
266 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
267 ///
268 UINT32 AERR_DriveEnable:1;
269 ///
270 /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
271 /// Disabled.
272 ///
273 UINT32 BERR_Enable:1;
274 UINT32 Reserved2:1;
275 ///
276 /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
277 /// Enabled 0 = Disabled.
278 ///
279 UINT32 BERR_DriverEnable:1;
280 ///
281 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
282 ///
283 UINT32 BINIT_DriverEnable:1;
284 ///
285 /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
286 ///
287 UINT32 OutputTriStateEnable:1;
288 ///
289 /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
290 ///
291 UINT32 ExecuteBIST:1;
292 ///
293 /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
294 ///
295 UINT32 AERR_ObservationEnabled:1;
296 UINT32 Reserved3:1;
297 ///
298 /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
299 ///
300 UINT32 BINIT_ObservationEnabled:1;
301 ///
302 /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
303 ///
304 UINT32 InOrderQueueDepth:1;
305 ///
306 /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
307 ///
308 UINT32 ResetVector:1;
309 ///
310 /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
311 ///
312 UINT32 FRCModeEnable:1;
313 ///
314 /// [Bits 17:16] APIC Cluster ID (R).
315 ///
316 UINT32 APICClusterID:2;
317 ///
318 /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
319 /// 133MHz 11 = Reserved.
320 ///
321 UINT32 SystemBusFrequency:2;
322 ///
323 /// [Bits 21:20] Symmetric Arbitration ID (R).
324 ///
325 UINT32 SymmetricArbitrationID:2;
326 ///
327 /// [Bits 25:22] Clock Frequency Ratio (R).
328 ///
329 UINT32 ClockFrequencyRatio:4;
330 ///
331 /// [Bit 26] Low Power Mode Enable (R/W).
332 ///
333 UINT32 LowPowerModeEnable:1;
334 ///
335 /// [Bit 27] Clock Frequency Ratio.
336 ///
337 UINT32 ClockFrequencyRatio1:1;
338 UINT32 Reserved4:4;
339 UINT32 Reserved5:32;
340 } Bits;
341 ///
342 /// All bit fields as a 32-bit value
343 ///
344 UINT32 Uint32;
345 ///
346 /// All bit fields as a 64-bit value
347 ///
348 UINT64 Uint64;
349 } MSR_P6_EBL_CR_POWERON_REGISTER;
350
351
352 /**
353 Test Control Register.
354
355 @param ECX MSR_P6_TEST_CTL (0x00000033)
356 @param EAX Lower 32-bits of MSR value.
357 Described by the type MSR_P6_TEST_CTL_REGISTER.
358 @param EDX Upper 32-bits of MSR value.
359 Described by the type MSR_P6_TEST_CTL_REGISTER.
360
361 <b>Example usage</b>
362 @code
363 MSR_P6_TEST_CTL_REGISTER Msr;
364
365 Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
366 AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
367 @endcode
368 @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
369 **/
370 #define MSR_P6_TEST_CTL 0x00000033
371
372 /**
373 MSR information returned for MSR index #MSR_P6_TEST_CTL
374 **/
375 typedef union {
376 ///
377 /// Individual bit fields
378 ///
379 struct {
380 UINT32 Reserved1:30;
381 ///
382 /// [Bit 30] Streaming Buffer Disable.
383 ///
384 UINT32 StreamingBufferDisable:1;
385 ///
386 /// [Bit 31] Disable LOCK# Assertion for split locked access.
387 ///
388 UINT32 Disable_LOCK:1;
389 UINT32 Reserved2:32;
390 } Bits;
391 ///
392 /// All bit fields as a 32-bit value
393 ///
394 UINT32 Uint32;
395 ///
396 /// All bit fields as a 64-bit value
397 ///
398 UINT64 Uint64;
399 } MSR_P6_TEST_CTL_REGISTER;
400
401
402 /**
403 BIOS Update Trigger Register.
404
405 @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)
406 @param EAX Lower 32-bits of MSR value.
407 @param EDX Upper 32-bits of MSR value.
408
409 <b>Example usage</b>
410 @code
411 UINT64 Msr;
412
413 Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
414 AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
415 @endcode
416 @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
417 **/
418 #define MSR_P6_BIOS_UPDT_TRIG 0x00000079
419
420
421 /**
422 Chunk n data register D[63:0]: used to write to and read from the L2.
423
424 @param ECX MSR_P6_BBL_CR_Dn
425 @param EAX Lower 32-bits of MSR value.
426 @param EDX Upper 32-bits of MSR value.
427
428 <b>Example usage</b>
429 @code
430 UINT64 Msr;
431
432 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
433 AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
434 @endcode
435 @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
436 MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
437 MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
438 @{
439 **/
440 #define MSR_P6_BBL_CR_D0 0x00000088
441 #define MSR_P6_BBL_CR_D1 0x00000089
442 #define MSR_P6_BBL_CR_D2 0x0000008A
443 /// @}
444
445
446 /**
447 BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
448 write to and read from the L2 depending on the usage model.
449
450 @param ECX MSR_P6_BIOS_SIGN (0x0000008B)
451 @param EAX Lower 32-bits of MSR value.
452 @param EDX Upper 32-bits of MSR value.
453
454 <b>Example usage</b>
455 @code
456 UINT64 Msr;
457
458 Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
459 AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
460 @endcode
461 @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
462 **/
463 #define MSR_P6_BIOS_SIGN 0x0000008B
464
465
466 /**
467
468
469 @param ECX MSR_P6_PERFCTR0 (0x000000C1)
470 @param EAX Lower 32-bits of MSR value.
471 @param EDX Upper 32-bits of MSR value.
472
473 <b>Example usage</b>
474 @code
475 UINT64 Msr;
476
477 Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
478 AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
479 @endcode
480 @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
481 MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
482 @{
483 **/
484 #define MSR_P6_PERFCTR0 0x000000C1
485 #define MSR_P6_PERFCTR1 0x000000C2
486 /// @}
487
488
489 /**
490
491
492 @param ECX MSR_P6_MTRRCAP (0x000000FE)
493 @param EAX Lower 32-bits of MSR value.
494 @param EDX Upper 32-bits of MSR value.
495
496 <b>Example usage</b>
497 @code
498 UINT64 Msr;
499
500 Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
501 AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
502 @endcode
503 @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
504 **/
505 #define MSR_P6_MTRRCAP 0x000000FE
506
507
508 /**
509 Address register: used to send specified address (A31-A3) to L2 during cache
510 initialization accesses.
511
512 @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)
513 @param EAX Lower 32-bits of MSR value.
514 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
515 @param EDX Upper 32-bits of MSR value.
516 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
517
518 <b>Example usage</b>
519 @code
520 MSR_P6_BBL_CR_ADDR_REGISTER Msr;
521
522 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
523 AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
524 @endcode
525 @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
526 **/
527 #define MSR_P6_BBL_CR_ADDR 0x00000116
528
529 /**
530 MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
531 **/
532 typedef union {
533 ///
534 /// Individual bit fields
535 ///
536 struct {
537 UINT32 Reserved1:3;
538 ///
539 /// [Bits 31:3] Address bits
540 ///
541 UINT32 Address:29;
542 UINT32 Reserved2:32;
543 } Bits;
544 ///
545 /// All bit fields as a 32-bit value
546 ///
547 UINT32 Uint32;
548 ///
549 /// All bit fields as a 64-bit value
550 ///
551 UINT64 Uint64;
552 } MSR_P6_BBL_CR_ADDR_REGISTER;
553
554
555 /**
556 Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
557
558 @param ECX MSR_P6_BBL_CR_DECC (0x00000118)
559 @param EAX Lower 32-bits of MSR value.
560 @param EDX Upper 32-bits of MSR value.
561
562 <b>Example usage</b>
563 @code
564 UINT64 Msr;
565
566 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
567 AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
568 @endcode
569 @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
570 **/
571 #define MSR_P6_BBL_CR_DECC 0x00000118
572
573
574 /**
575 Control register: used to program L2 commands to be issued via cache
576 configuration accesses mechanism. Also receives L2 lookup response.
577
578 @param ECX MSR_P6_BBL_CR_CTL (0x00000119)
579 @param EAX Lower 32-bits of MSR value.
580 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
581 @param EDX Upper 32-bits of MSR value.
582 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
583
584 <b>Example usage</b>
585 @code
586 MSR_P6_BBL_CR_CTL_REGISTER Msr;
587
588 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
589 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
590 @endcode
591 @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
592 **/
593 #define MSR_P6_BBL_CR_CTL 0x00000119
594
595 /**
596 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
597 **/
598 typedef union {
599 ///
600 /// Individual bit fields
601 ///
602 struct {
603 ///
604 /// [Bits 4:0] L2 Command
605 /// Data Read w/ LRU update (RLU)
606 /// Tag Read w/ Data Read (TRR)
607 /// Tag Inquire (TI)
608 /// L2 Control Register Read (CR)
609 /// L2 Control Register Write (CW)
610 /// Tag Write w/ Data Read (TWR)
611 /// Tag Write w/ Data Write (TWW)
612 /// Tag Write (TW).
613 ///
614 UINT32 L2Command:5;
615 ///
616 /// [Bits 6:5] State to L2
617 ///
618 UINT32 StateToL2:2;
619 UINT32 Reserved:1;
620 ///
621 /// [Bits 9:8] Way to L2.
622 ///
623 UINT32 WayToL2:2;
624 ///
625 /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
626 ///
627 UINT32 Way:2;
628 ///
629 /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
630 ///
631 UINT32 MESI:2;
632 ///
633 /// [Bits 15:14] State from L2.
634 ///
635 UINT32 StateFromL2:2;
636 UINT32 Reserved2:1;
637 ///
638 /// [Bit 17] L2 Hit.
639 ///
640 UINT32 L2Hit:1;
641 UINT32 Reserved3:1;
642 ///
643 /// [Bits 20:19] User supplied ECC.
644 ///
645 UINT32 UserEcc:2;
646 ///
647 /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
648 ///
649 UINT32 ProcessorNumber:1;
650 UINT32 Reserved4:10;
651 UINT32 Reserved5:32;
652 } Bits;
653 ///
654 /// All bit fields as a 32-bit value
655 ///
656 UINT32 Uint32;
657 ///
658 /// All bit fields as a 64-bit value
659 ///
660 UINT64 Uint64;
661 } MSR_P6_BBL_CR_CTL_REGISTER;
662
663
664 /**
665 Trigger register: used to initiate a cache configuration accesses access,
666 Write only with Data = 0.
667
668 @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)
669 @param EAX Lower 32-bits of MSR value.
670 @param EDX Upper 32-bits of MSR value.
671
672 <b>Example usage</b>
673 @code
674 UINT64 Msr;
675
676 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
677 AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
678 @endcode
679 @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
680 **/
681 #define MSR_P6_BBL_CR_TRIG 0x0000011A
682
683
684 /**
685 Busy register: indicates when a cache configuration accesses L2 command is
686 in progress. D[0] = 1 = BUSY.
687
688 @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)
689 @param EAX Lower 32-bits of MSR value.
690 @param EDX Upper 32-bits of MSR value.
691
692 <b>Example usage</b>
693 @code
694 UINT64 Msr;
695
696 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
697 AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
698 @endcode
699 @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.
700 **/
701 #define MSR_P6_BBL_CR_BUSY 0x0000011B
702
703
704 /**
705 Control register 3: used to configure the L2 Cache.
706
707 @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)
708 @param EAX Lower 32-bits of MSR value.
709 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
710 @param EDX Upper 32-bits of MSR value.
711 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
712
713 <b>Example usage</b>
714 @code
715 MSR_P6_BBL_CR_CTL3_REGISTER Msr;
716
717 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
718 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
719 @endcode
720 @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.
721 **/
722 #define MSR_P6_BBL_CR_CTL3 0x0000011E
723
724 /**
725 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
726 **/
727 typedef union {
728 ///
729 /// Individual bit fields
730 ///
731 struct {
732 ///
733 /// [Bit 0] L2 Configured (read/write ).
734 ///
735 UINT32 L2Configured:1;
736 ///
737 /// [Bits 4:1] L2 Cache Latency (read/write).
738 ///
739 UINT32 L2CacheLatency:4;
740 ///
741 /// [Bit 5] ECC Check Enable (read/write).
742 ///
743 UINT32 ECCCheckEnable:1;
744 ///
745 /// [Bit 6] Address Parity Check Enable (read/write).
746 ///
747 UINT32 AddressParityCheckEnable:1;
748 ///
749 /// [Bit 7] CRTN Parity Check Enable (read/write).
750 ///
751 UINT32 CRTNParityCheckEnable:1;
752 ///
753 /// [Bit 8] L2 Enabled (read/write).
754 ///
755 UINT32 L2Enabled:1;
756 ///
757 /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
758 /// Reserved.
759 ///
760 UINT32 L2Associativity:2;
761 ///
762 /// [Bits 12:11] Number of L2 banks (read only).
763 ///
764 UINT32 L2Banks:2;
765 ///
766 /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
767 /// 1MByte 2MByte 4MBytes.
768 ///
769 UINT32 CacheSizePerBank:5;
770 ///
771 /// [Bit 18] Cache State error checking enable (read/write).
772 ///
773 UINT32 CacheStateErrorEnable:1;
774 UINT32 Reserved1:1;
775 ///
776 /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
777 /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
778 ///
779 UINT32 L2AddressRange:3;
780 ///
781 /// [Bit 23] L2 Hardware Disable (read only).
782 ///
783 UINT32 L2HardwareDisable:1;
784 UINT32 Reserved2:1;
785 ///
786 /// [Bit 25] Cache bus fraction (read only).
787 ///
788 UINT32 CacheBusFraction:1;
789 UINT32 Reserved3:6;
790 UINT32 Reserved4:32;
791 } Bits;
792 ///
793 /// All bit fields as a 32-bit value
794 ///
795 UINT32 Uint32;
796 ///
797 /// All bit fields as a 64-bit value
798 ///
799 UINT64 Uint64;
800 } MSR_P6_BBL_CR_CTL3_REGISTER;
801
802
803 /**
804 CS register target for CPL 0 code.
805
806 @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)
807 @param EAX Lower 32-bits of MSR value.
808 @param EDX Upper 32-bits of MSR value.
809
810 <b>Example usage</b>
811 @code
812 UINT64 Msr;
813
814 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
815 AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
816 @endcode
817 @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.
818 **/
819 #define MSR_P6_SYSENTER_CS_MSR 0x00000174
820
821
822 /**
823 Stack pointer for CPL 0 stack.
824
825 @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)
826 @param EAX Lower 32-bits of MSR value.
827 @param EDX Upper 32-bits of MSR value.
828
829 <b>Example usage</b>
830 @code
831 UINT64 Msr;
832
833 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
834 AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
835 @endcode
836 @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.
837 **/
838 #define MSR_P6_SYSENTER_ESP_MSR 0x00000175
839
840
841 /**
842 CPL 0 code entry point.
843
844 @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)
845 @param EAX Lower 32-bits of MSR value.
846 @param EDX Upper 32-bits of MSR value.
847
848 <b>Example usage</b>
849 @code
850 UINT64 Msr;
851
852 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
853 AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
854 @endcode
855 @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.
856 **/
857 #define MSR_P6_SYSENTER_EIP_MSR 0x00000176
858
859
860 /**
861
862
863 @param ECX MSR_P6_MCG_CAP (0x00000179)
864 @param EAX Lower 32-bits of MSR value.
865 @param EDX Upper 32-bits of MSR value.
866
867 <b>Example usage</b>
868 @code
869 UINT64 Msr;
870
871 Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
872 AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
873 @endcode
874 @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.
875 **/
876 #define MSR_P6_MCG_CAP 0x00000179
877
878
879 /**
880
881
882 @param ECX MSR_P6_MCG_STATUS (0x0000017A)
883 @param EAX Lower 32-bits of MSR value.
884 @param EDX Upper 32-bits of MSR value.
885
886 <b>Example usage</b>
887 @code
888 UINT64 Msr;
889
890 Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
891 AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
892 @endcode
893 @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.
894 **/
895 #define MSR_P6_MCG_STATUS 0x0000017A
896
897
898 /**
899
900
901 @param ECX MSR_P6_MCG_CTL (0x0000017B)
902 @param EAX Lower 32-bits of MSR value.
903 @param EDX Upper 32-bits of MSR value.
904
905 <b>Example usage</b>
906 @code
907 UINT64 Msr;
908
909 Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
910 AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
911 @endcode
912 @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.
913 **/
914 #define MSR_P6_MCG_CTL 0x0000017B
915
916
917 /**
918
919
920 @param ECX MSR_P6_PERFEVTSELn
921 @param EAX Lower 32-bits of MSR value.
922 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
923 @param EDX Upper 32-bits of MSR value.
924 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
925
926 <b>Example usage</b>
927 @code
928 MSR_P6_PERFEVTSEL_REGISTER Msr;
929
930 Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
931 AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
932 @endcode
933 @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.
934 MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.
935 @{
936 **/
937 #define MSR_P6_PERFEVTSEL0 0x00000186
938 #define MSR_P6_PERFEVTSEL1 0x00000187
939 /// @}
940
941 /**
942 MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
943 #MSR_P6_PERFEVTSEL1.
944 **/
945 typedef union {
946 ///
947 /// Individual bit fields
948 ///
949 struct {
950 ///
951 /// [Bits 7:0] Event Select Refer to Performance Counter section for a
952 /// list of event encodings.
953 ///
954 UINT32 EventSelect:8;
955 ///
956 /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
957 /// all count options.
958 ///
959 UINT32 UMASK:8;
960 ///
961 /// [Bit 16] USER Controls the counting of events at Privilege levels of
962 /// 1, 2, and 3.
963 ///
964 UINT32 USR:1;
965 ///
966 /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
967 ///
968 UINT32 OS:1;
969 ///
970 /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
971 ///
972 UINT32 E:1;
973 ///
974 /// [Bit 19] PC Enabled the signaling of performance counter overflow via
975 /// BP0 pin.
976 ///
977 UINT32 PC:1;
978 ///
979 /// [Bit 20] INT Enables the signaling of counter overflow via input to
980 /// APIC 1 = Enable 0 = Disable.
981 ///
982 UINT32 INT:1;
983 UINT32 Reserved1:1;
984 ///
985 /// [Bit 22] ENABLE Enables the counting of performance events in both
986 /// counters 1 = Enable 0 = Disable.
987 ///
988 UINT32 EN:1;
989 ///
990 /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
991 /// = Non-Inverted.
992 ///
993 UINT32 INV:1;
994 ///
995 /// [Bits 31:24] CMASK (Counter Mask).
996 ///
997 UINT32 CMASK:8;
998 UINT32 Reserved2:32;
999 } Bits;
1000 ///
1001 /// All bit fields as a 32-bit value
1002 ///
1003 UINT32 Uint32;
1004 ///
1005 /// All bit fields as a 64-bit value
1006 ///
1007 UINT64 Uint64;
1008 } MSR_P6_PERFEVTSEL_REGISTER;
1009
1010
1011 /**
1012
1013
1014 @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)
1015 @param EAX Lower 32-bits of MSR value.
1016 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
1017 @param EDX Upper 32-bits of MSR value.
1018 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
1019
1020 <b>Example usage</b>
1021 @code
1022 MSR_P6_DEBUGCTLMSR_REGISTER Msr;
1023
1024 Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
1025 AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
1026 @endcode
1027 @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.
1028 **/
1029 #define MSR_P6_DEBUGCTLMSR 0x000001D9
1030
1031 /**
1032 MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
1033 **/
1034 typedef union {
1035 ///
1036 /// Individual bit fields
1037 ///
1038 struct {
1039 ///
1040 /// [Bit 0] Enable/Disable Last Branch Records.
1041 ///
1042 UINT32 LBR:1;
1043 ///
1044 /// [Bit 1] Branch Trap Flag.
1045 ///
1046 UINT32 BTF:1;
1047 ///
1048 /// [Bit 2] Performance Monitoring/Break Point Pins.
1049 ///
1050 UINT32 PB0:1;
1051 ///
1052 /// [Bit 3] Performance Monitoring/Break Point Pins.
1053 ///
1054 UINT32 PB1:1;
1055 ///
1056 /// [Bit 4] Performance Monitoring/Break Point Pins.
1057 ///
1058 UINT32 PB2:1;
1059 ///
1060 /// [Bit 5] Performance Monitoring/Break Point Pins.
1061 ///
1062 UINT32 PB3:1;
1063 ///
1064 /// [Bit 6] Enable/Disable Execution Trace Messages.
1065 ///
1066 UINT32 TR:1;
1067 UINT32 Reserved1:25;
1068 UINT32 Reserved2:32;
1069 } Bits;
1070 ///
1071 /// All bit fields as a 32-bit value
1072 ///
1073 UINT32 Uint32;
1074 ///
1075 /// All bit fields as a 64-bit value
1076 ///
1077 UINT64 Uint64;
1078 } MSR_P6_DEBUGCTLMSR_REGISTER;
1079
1080
1081 /**
1082
1083
1084 @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)
1085 @param EAX Lower 32-bits of MSR value.
1086 @param EDX Upper 32-bits of MSR value.
1087
1088 <b>Example usage</b>
1089 @code
1090 UINT64 Msr;
1091
1092 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
1093 AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
1094 @endcode
1095 @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.
1096 **/
1097 #define MSR_P6_LASTBRANCHFROMIP 0x000001DB
1098
1099
1100 /**
1101
1102
1103 @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)
1104 @param EAX Lower 32-bits of MSR value.
1105 @param EDX Upper 32-bits of MSR value.
1106
1107 <b>Example usage</b>
1108 @code
1109 UINT64 Msr;
1110
1111 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
1112 AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
1113 @endcode
1114 @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.
1115 **/
1116 #define MSR_P6_LASTBRANCHTOIP 0x000001DC
1117
1118
1119 /**
1120
1121
1122 @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)
1123 @param EAX Lower 32-bits of MSR value.
1124 @param EDX Upper 32-bits of MSR value.
1125
1126 <b>Example usage</b>
1127 @code
1128 UINT64 Msr;
1129
1130 Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
1131 AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
1132 @endcode
1133 @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.
1134 **/
1135 #define MSR_P6_LASTINTFROMIP 0x000001DD
1136
1137
1138 /**
1139
1140
1141 @param ECX MSR_P6_LASTINTTOIP (0x000001DE)
1142 @param EAX Lower 32-bits of MSR value.
1143 @param EDX Upper 32-bits of MSR value.
1144
1145 <b>Example usage</b>
1146 @code
1147 UINT64 Msr;
1148
1149 Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
1150 AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
1151 @endcode
1152 @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.
1153 **/
1154 #define MSR_P6_LASTINTTOIP 0x000001DE
1155
1156
1157 /**
1158
1159
1160 @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0)
1161 @param EAX Lower 32-bits of MSR value.
1162 Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
1163 @param EDX Upper 32-bits of MSR value.
1164 Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
1165
1166 <b>Example usage</b>
1167 @code
1168 MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr;
1169
1170 Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
1171 AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
1172 @endcode
1173 @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
1174 **/
1175 #define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0
1176
1177 /**
1178 MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6
1179 **/
1180 typedef union {
1181 ///
1182 /// Individual bit fields
1183 ///
1184 struct {
1185 UINT32 Reserved1:2;
1186 ///
1187 /// [Bit 2] Fast Strings Enable bit. Default is enabled.
1188 ///
1189 UINT32 FastStrings:1;
1190 UINT32 Reserved2:29;
1191 UINT32 Reserved3:32;
1192 } Bits;
1193 ///
1194 /// All bit fields as a 32-bit value
1195 ///
1196 UINT32 Uint32;
1197 ///
1198 /// All bit fields as a 64-bit value
1199 ///
1200 UINT64 Uint64;
1201 } MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;
1202
1203
1204 /**
1205
1206
1207 @param ECX MSR_P6_MTRRPHYSBASEn
1208 @param EAX Lower 32-bits of MSR value.
1209 @param EDX Upper 32-bits of MSR value.
1210
1211 <b>Example usage</b>
1212 @code
1213 UINT64 Msr;
1214
1215 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
1216 AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
1217 @endcode
1218 @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
1219 MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
1220 MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
1221 MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
1222 MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
1223 MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
1224 MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
1225 MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
1226 @{
1227 **/
1228 #define MSR_P6_MTRRPHYSBASE0 0x00000200
1229 #define MSR_P6_MTRRPHYSBASE1 0x00000202
1230 #define MSR_P6_MTRRPHYSBASE2 0x00000204
1231 #define MSR_P6_MTRRPHYSBASE3 0x00000206
1232 #define MSR_P6_MTRRPHYSBASE4 0x00000208
1233 #define MSR_P6_MTRRPHYSBASE5 0x0000020A
1234 #define MSR_P6_MTRRPHYSBASE6 0x0000020C
1235 #define MSR_P6_MTRRPHYSBASE7 0x0000020E
1236 /// @}
1237
1238
1239 /**
1240
1241
1242 @param ECX MSR_P6_MTRRPHYSMASKn
1243 @param EAX Lower 32-bits of MSR value.
1244 @param EDX Upper 32-bits of MSR value.
1245
1246 <b>Example usage</b>
1247 @code
1248 UINT64 Msr;
1249
1250 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
1251 AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
1252 @endcode
1253 @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
1254 MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
1255 MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
1256 MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
1257 MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
1258 MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
1259 MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
1260 MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
1261 @{
1262 **/
1263 #define MSR_P6_MTRRPHYSMASK0 0x00000201
1264 #define MSR_P6_MTRRPHYSMASK1 0x00000203
1265 #define MSR_P6_MTRRPHYSMASK2 0x00000205
1266 #define MSR_P6_MTRRPHYSMASK3 0x00000207
1267 #define MSR_P6_MTRRPHYSMASK4 0x00000209
1268 #define MSR_P6_MTRRPHYSMASK5 0x0000020B
1269 #define MSR_P6_MTRRPHYSMASK6 0x0000020D
1270 #define MSR_P6_MTRRPHYSMASK7 0x0000020F
1271 /// @}
1272
1273
1274 /**
1275
1276
1277 @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)
1278 @param EAX Lower 32-bits of MSR value.
1279 @param EDX Upper 32-bits of MSR value.
1280
1281 <b>Example usage</b>
1282 @code
1283 UINT64 Msr;
1284
1285 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
1286 AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
1287 @endcode
1288 @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
1289 **/
1290 #define MSR_P6_MTRRFIX64K_00000 0x00000250
1291
1292
1293 /**
1294
1295
1296 @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)
1297 @param EAX Lower 32-bits of MSR value.
1298 @param EDX Upper 32-bits of MSR value.
1299
1300 <b>Example usage</b>
1301 @code
1302 UINT64 Msr;
1303
1304 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
1305 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
1306 @endcode
1307 @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
1308 **/
1309 #define MSR_P6_MTRRFIX16K_80000 0x00000258
1310
1311
1312 /**
1313
1314
1315 @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)
1316 @param EAX Lower 32-bits of MSR value.
1317 @param EDX Upper 32-bits of MSR value.
1318
1319 <b>Example usage</b>
1320 @code
1321 UINT64 Msr;
1322
1323 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
1324 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
1325 @endcode
1326 @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
1327 **/
1328 #define MSR_P6_MTRRFIX16K_A0000 0x00000259
1329
1330
1331 /**
1332
1333
1334 @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)
1335 @param EAX Lower 32-bits of MSR value.
1336 @param EDX Upper 32-bits of MSR value.
1337
1338 <b>Example usage</b>
1339 @code
1340 UINT64 Msr;
1341
1342 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
1343 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
1344 @endcode
1345 @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
1346 **/
1347 #define MSR_P6_MTRRFIX4K_C0000 0x00000268
1348
1349
1350 /**
1351
1352
1353 @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)
1354 @param EAX Lower 32-bits of MSR value.
1355 @param EDX Upper 32-bits of MSR value.
1356
1357 <b>Example usage</b>
1358 @code
1359 UINT64 Msr;
1360
1361 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
1362 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
1363 @endcode
1364 @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
1365 **/
1366 #define MSR_P6_MTRRFIX4K_C8000 0x00000269
1367
1368
1369 /**
1370
1371
1372 @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
1373 @param EAX Lower 32-bits of MSR value.
1374 @param EDX Upper 32-bits of MSR value.
1375
1376 <b>Example usage</b>
1377 @code
1378 UINT64 Msr;
1379
1380 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
1381 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
1382 @endcode
1383 @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
1384 **/
1385 #define MSR_P6_MTRRFIX4K_D0000 0x0000026A
1386
1387
1388 /**
1389
1390
1391 @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
1392 @param EAX Lower 32-bits of MSR value.
1393 @param EDX Upper 32-bits of MSR value.
1394
1395 <b>Example usage</b>
1396 @code
1397 UINT64 Msr;
1398
1399 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
1400 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
1401 @endcode
1402 @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
1403 **/
1404 #define MSR_P6_MTRRFIX4K_D8000 0x0000026B
1405
1406
1407 /**
1408
1409
1410 @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
1411 @param EAX Lower 32-bits of MSR value.
1412 @param EDX Upper 32-bits of MSR value.
1413
1414 <b>Example usage</b>
1415 @code
1416 UINT64 Msr;
1417
1418 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
1419 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
1420 @endcode
1421 @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
1422 **/
1423 #define MSR_P6_MTRRFIX4K_E0000 0x0000026C
1424
1425
1426 /**
1427
1428
1429 @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
1430 @param EAX Lower 32-bits of MSR value.
1431 @param EDX Upper 32-bits of MSR value.
1432
1433 <b>Example usage</b>
1434 @code
1435 UINT64 Msr;
1436
1437 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
1438 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
1439 @endcode
1440 @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
1441 **/
1442 #define MSR_P6_MTRRFIX4K_E8000 0x0000026D
1443
1444
1445 /**
1446
1447
1448 @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
1449 @param EAX Lower 32-bits of MSR value.
1450 @param EDX Upper 32-bits of MSR value.
1451
1452 <b>Example usage</b>
1453 @code
1454 UINT64 Msr;
1455
1456 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
1457 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
1458 @endcode
1459 @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
1460 **/
1461 #define MSR_P6_MTRRFIX4K_F0000 0x0000026E
1462
1463
1464 /**
1465
1466
1467 @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
1468 @param EAX Lower 32-bits of MSR value.
1469 @param EDX Upper 32-bits of MSR value.
1470
1471 <b>Example usage</b>
1472 @code
1473 UINT64 Msr;
1474
1475 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
1476 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
1477 @endcode
1478 @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
1479 **/
1480 #define MSR_P6_MTRRFIX4K_F8000 0x0000026F
1481
1482
1483 /**
1484
1485
1486 @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)
1487 @param EAX Lower 32-bits of MSR value.
1488 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1489 @param EDX Upper 32-bits of MSR value.
1490 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1491
1492 <b>Example usage</b>
1493 @code
1494 MSR_P6_MTRRDEFTYPE_REGISTER Msr;
1495
1496 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
1497 AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
1498 @endcode
1499 @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.
1500 **/
1501 #define MSR_P6_MTRRDEFTYPE 0x000002FF
1502
1503 /**
1504 MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
1505 **/
1506 typedef union {
1507 ///
1508 /// Individual bit fields
1509 ///
1510 struct {
1511 ///
1512 /// [Bits 2:0] Default memory type.
1513 ///
1514 UINT32 Type:3;
1515 UINT32 Reserved1:7;
1516 ///
1517 /// [Bit 10] Fixed MTRR enable.
1518 ///
1519 UINT32 FE:1;
1520 ///
1521 /// [Bit 11] MTRR Enable.
1522 ///
1523 UINT32 E:1;
1524 UINT32 Reserved2:20;
1525 UINT32 Reserved3:32;
1526 } Bits;
1527 ///
1528 /// All bit fields as a 32-bit value
1529 ///
1530 UINT32 Uint32;
1531 ///
1532 /// All bit fields as a 64-bit value
1533 ///
1534 UINT64 Uint64;
1535 } MSR_P6_MTRRDEFTYPE_REGISTER;
1536
1537
1538 /**
1539
1540
1541 @param ECX MSR_P6_MC0_CTL (0x00000400)
1542 @param EAX Lower 32-bits of MSR value.
1543 @param EDX Upper 32-bits of MSR value.
1544
1545 <b>Example usage</b>
1546 @code
1547 UINT64 Msr;
1548
1549 Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
1550 AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
1551 @endcode
1552 @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.
1553 MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.
1554 MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.
1555 MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.
1556 MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.
1557 @{
1558 **/
1559 #define MSR_P6_MC0_CTL 0x00000400
1560 #define MSR_P6_MC1_CTL 0x00000404
1561 #define MSR_P6_MC2_CTL 0x00000408
1562 #define MSR_P6_MC3_CTL 0x00000410
1563 #define MSR_P6_MC4_CTL 0x0000040C
1564 /// @}
1565
1566
1567 /**
1568
1569 Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
1570 except bits 0, 4, 57, and 61 are hardcoded to 1.
1571
1572 @param ECX MSR_P6_MCn_STATUS
1573 @param EAX Lower 32-bits of MSR value.
1574 Described by the type MSR_P6_MC_STATUS_REGISTER.
1575 @param EDX Upper 32-bits of MSR value.
1576 Described by the type MSR_P6_MC_STATUS_REGISTER.
1577
1578 <b>Example usage</b>
1579 @code
1580 MSR_P6_MC_STATUS_REGISTER Msr;
1581
1582 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
1583 AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
1584 @endcode
1585 @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.
1586 MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.
1587 MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.
1588 MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.
1589 MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.
1590 @{
1591 **/
1592 #define MSR_P6_MC0_STATUS 0x00000401
1593 #define MSR_P6_MC1_STATUS 0x00000405
1594 #define MSR_P6_MC2_STATUS 0x00000409
1595 #define MSR_P6_MC3_STATUS 0x00000411
1596 #define MSR_P6_MC4_STATUS 0x0000040D
1597 /// @}
1598
1599 /**
1600 MSR information returned for MSR index #MSR_P6_MC0_STATUS to
1601 #MSR_P6_MC4_STATUS
1602 **/
1603 typedef union {
1604 ///
1605 /// Individual bit fields
1606 ///
1607 struct {
1608 ///
1609 /// [Bits 15:0] MC_STATUS_MCACOD.
1610 ///
1611 UINT32 MC_STATUS_MCACOD:16;
1612 ///
1613 /// [Bits 31:16] MC_STATUS_MSCOD.
1614 ///
1615 UINT32 MC_STATUS_MSCOD:16;
1616 UINT32 Reserved:25;
1617 ///
1618 /// [Bit 57] MC_STATUS_DAM.
1619 ///
1620 UINT32 MC_STATUS_DAM:1;
1621 ///
1622 /// [Bit 58] MC_STATUS_ADDRV.
1623 ///
1624 UINT32 MC_STATUS_ADDRV:1;
1625 ///
1626 /// [Bit 59] MC_STATUS_MISCV.
1627 ///
1628 UINT32 MC_STATUS_MISCV:1;
1629 ///
1630 /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
1631 /// hardcoded to 1.).
1632 ///
1633 UINT32 MC_STATUS_EN:1;
1634 ///
1635 /// [Bit 61] MC_STATUS_UC.
1636 ///
1637 UINT32 MC_STATUS_UC:1;
1638 ///
1639 /// [Bit 62] MC_STATUS_O.
1640 ///
1641 UINT32 MC_STATUS_O:1;
1642 ///
1643 /// [Bit 63] MC_STATUS_V.
1644 ///
1645 UINT32 MC_STATUS_V:1;
1646 } Bits;
1647 ///
1648 /// All bit fields as a 64-bit value
1649 ///
1650 UINT64 Uint64;
1651 } MSR_P6_MC_STATUS_REGISTER;
1652
1653
1654 /**
1655
1656 MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
1657
1658 @param ECX MSR_P6_MC0_ADDR (0x00000402)
1659 @param EAX Lower 32-bits of MSR value.
1660 @param EDX Upper 32-bits of MSR value.
1661
1662 <b>Example usage</b>
1663 @code
1664 UINT64 Msr;
1665
1666 Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
1667 AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
1668 @endcode
1669 @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.
1670 MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.
1671 MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.
1672 MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.
1673 MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.
1674 @{
1675 **/
1676 #define MSR_P6_MC0_ADDR 0x00000402
1677 #define MSR_P6_MC1_ADDR 0x00000406
1678 #define MSR_P6_MC2_ADDR 0x0000040A
1679 #define MSR_P6_MC3_ADDR 0x00000412
1680 #define MSR_P6_MC4_ADDR 0x0000040E
1681 /// @}
1682
1683
1684 /**
1685 Defined in MCA architecture but not implemented in the P6 family processors.
1686
1687 @param ECX MSR_P6_MC0_MISC (0x00000403)
1688 @param EAX Lower 32-bits of MSR value.
1689 @param EDX Upper 32-bits of MSR value.
1690
1691 <b>Example usage</b>
1692 @code
1693 UINT64 Msr;
1694
1695 Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
1696 AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
1697 @endcode
1698 @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.
1699 MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.
1700 MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.
1701 MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.
1702 MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.
1703 @{
1704 **/
1705 #define MSR_P6_MC0_MISC 0x00000403
1706 #define MSR_P6_MC1_MISC 0x00000407
1707 #define MSR_P6_MC2_MISC 0x0000040B
1708 #define MSR_P6_MC3_MISC 0x00000413
1709 #define MSR_P6_MC4_MISC 0x0000040F
1710 /// @}
1711
1712 #endif
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