UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h

   1 /** @file
   2   MSR Definitions for Pentium(R) 4 Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.
  21
  22 **/
  23
  24 #ifndef __PENTIUM_4_MSR_H__
  25 #define __PENTIUM_4_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
  31   Determination.".
  32
  33   @param  ECX  MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)
  34   @param  EAX  Lower 32-bits of MSR value.
  35   @param  EDX  Upper 32-bits of MSR value.
  36
  37   <b>Example usage</b>
  38   @code
  39   UINT64  Msr;
  40
  41   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
  42   AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
  43   @endcode
  44 **/
  45 #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006
  46
  47
  48 /**
  49   0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
  50   Enables and disables processor features; (R) indicates current processor
  51   configuration.
  52
  53   @param  ECX  MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)
  54   @param  EAX  Lower 32-bits of MSR value.
  55                Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
  56   @param  EDX  Upper 32-bits of MSR value.
  57                Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
  58
  59   <b>Example usage</b>
  60   @code
  61   MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER  Msr;
  62
  63   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
  64   AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
  65   @endcode
  66 **/
  67 #define MSR_PENTIUM_4_EBC_HARD_POWERON           0x0000002A
  68
  69 /**
  70   MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
  71 **/
  72 typedef union {
  73   ///
  74   /// Individual bit fields
  75   ///
  76   struct {
  77     ///
  78     /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
  79     /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
  80     /// The value in this bit is written on the deassertion of RESET#; the bit
  81     /// is set to 1 when the address bus signal is asserted.
  82     ///
  83     UINT32  OutputTriStateEnabled:1;
  84     ///
  85     /// [Bit 1] Execute BIST (R)  Indicates whether the execution of the BIST
  86     /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
  87     /// value in this bit is written on the deassertion of RESET#; the bit is
  88     /// set to 1 when the address bus signal is asserted.
  89     ///
  90     UINT32  ExecuteBIST:1;
  91     ///
  92     /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
  93     /// depth for the system bus is 1 (1) or up to 12 (0) as set by the
  94     /// strapping of A7#. The value in this bit is written on the deassertion
  95     /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
  96     ///
  97     UINT32  InOrderQueueDepth:1;
  98     ///
  99     /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
 100     /// observation is enabled (0) or disabled (1) as determined by the
 101     /// strapping of A9#. The value in this bit is written on the deassertion
 102     /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
 103     ///
 104     UINT32  MCERR_ObservationDisabled:1;
 105     ///
 106     /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
 107     /// observation is enabled (0) or disabled (1) as determined by the
 108     /// strapping of A10#. The value in this bit is written on the deassertion
 109     /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
 110     ///
 111     UINT32  BINIT_ObservationEnabled:1;
 112     ///
 113     /// [Bits 6:5] APIC Cluster ID (R)  Contains the logical APIC cluster ID
 114     /// value as set by the strapping of A12# and A11#. The logical cluster ID
 115     /// value is written into the field on the deassertion of RESET#; the
 116     /// field is set to 1 when the address bus signal is asserted.
 117     ///
 118     UINT32  APICClusterID:2;
 119     ///
 120     /// [Bit 7] Bus Park Disable (R)  Indicates whether bus park is enabled
 121     /// (0) or disabled (1) as set by the strapping of A15#. The value in this
 122     /// bit is written on the deassertion of RESET#; the bit is set to 1 when
 123     /// the address bus signal is asserted.
 124     ///
 125     UINT32  BusParkDisable:1;
 126     UINT32  Reserved1:4;
 127     ///
 128     /// [Bits 13:12] Agent ID (R)  Contains the logical agent ID value as set
 129     /// by the strapping of BR[3:0]. The logical ID value is written into the
 130     /// field on the deassertion of RESET#; the field is set to 1 when the
 131     /// address bus signal is asserted.
 132     ///
 133     UINT32  AgentID:2;
 134     UINT32  Reserved2:18;
 135     UINT32  Reserved3:32;
 136   } Bits;
 137   ///
 138   /// All bit fields as a 32-bit value
 139   ///
 140   UINT32  Uint32;
 141   ///
 142   /// All bit fields as a 64-bit value
 143   ///
 144   UINT64  Uint64;
 145 } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;
 146
 147
 148 /**
 149   0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)
 150   Enables and disables processor features.
 151
 152   @param  ECX  MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)
 153   @param  EAX  Lower 32-bits of MSR value.
 154                Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
 155   @param  EDX  Upper 32-bits of MSR value.
 156                Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
 157
 158   <b>Example usage</b>
 159   @code
 160   MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER  Msr;
 161
 162   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
 163   AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
 164   @endcode
 165 **/
 166 #define MSR_PENTIUM_4_EBC_SOFT_POWERON           0x0000002B
 167
 168 /**
 169   MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON
 170 **/
 171 typedef union {
 172   ///
 173   /// Individual bit fields
 174   ///
 175   struct {
 176     ///
 177     /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W)  Controls the
 178     /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear
 179     /// to disabled (0, default).
 180     ///
 181     UINT32  RCNT_SCNT:1;
 182     ///
 183     /// [Bit 1] Data Error Checking Disable (R/W)  Set to disable system data
 184     /// bus parity checking; clear to enable parity checking.
 185     ///
 186     UINT32  DataErrorCheckingDisable:1;
 187     ///
 188     /// [Bit 2] Response Error Checking Disable (R/W) Set to disable
 189     /// (default); clear to enable.
 190     ///
 191     UINT32  ResponseErrorCheckingDisable:1;
 192     ///
 193     /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable
 194     /// (default); clear to enable.
 195     ///
 196     UINT32  AddressRequestErrorCheckingDisable:1;
 197     ///
 198     /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving
 199     /// for initiator bus requests (default); clear to enable.
 200     ///
 201     UINT32  InitiatorMCERR_Disable:1;
 202     ///
 203     /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving
 204     /// for initiator internal errors (default); clear to enable.
 205     ///
 206     UINT32  InternalMCERR_Disable:1;
 207     ///
 208     /// [Bit 6] BINIT# Driver Disable (R/W)  Set to disable BINIT# driver
 209     /// (default); clear to enable driver.
 210     ///
 211     UINT32  BINIT_DriverDisable:1;
 212     UINT32  Reserved1:25;
 213     UINT32  Reserved2:32;
 214   } Bits;
 215   ///
 216   /// All bit fields as a 32-bit value
 217   ///
 218   UINT32  Uint32;
 219   ///
 220   /// All bit fields as a 64-bit value
 221   ///
 222   UINT64  Uint64;
 223 } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;
 224
 225
 226 /**
 227   2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of
 228   this MSR varies according to the MODEL value in the CPUID version
 229   information. The following bit field layout applies to Pentium 4 and Xeon
 230   Processors with MODEL encoding equal or greater than 2. (R) The field
 231   Indicates the current processor frequency configuration.
 232
 233   @param  ECX  MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)
 234   @param  EAX  Lower 32-bits of MSR value.
 235                Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
 236   @param  EDX  Upper 32-bits of MSR value.
 237                Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
 238
 239   <b>Example usage</b>
 240   @code
 241   MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER  Msr;
 242
 243   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
 244   @endcode
 245 **/
 246 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID           0x0000002C
 247
 248 /**
 249   MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID
 250 **/
 251 typedef union {
 252   ///
 253   /// Individual bit fields
 254   ///
 255   struct {
 256     UINT32  Reserved1:16;
 257     ///
 258     /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable
 259     /// bus speed: *EncodingScalable Bus Speed*
 260     ///
 261     ///   000B 100 MHz (Model 2).
 262     ///   000B 266 MHz (Model 3 or 4)
 263     ///   001B 133 MHz
 264     ///   010B 200 MHz
 265     ///   011B 166 MHz
 266     ///   100B 333 MHz (Model 6)
 267     ///
 268     ///   133.33 MHz should be utilized if performing calculation with System
 269     ///   Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
 270     ///   performing calculation with System Bus Speed when encoding is 011B.
 271     ///   266.67 MHz should be utilized if performing calculation with System
 272     ///   Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33
 273     ///   MHz should be utilized if performing calculation with System Bus
 274     ///   Speed when encoding is 100B and model encoding = 6. All other values
 275     ///   are reserved.
 276     ///
 277     UINT32  ScalableBusSpeed:3;
 278     UINT32  Reserved2:5;
 279     ///
 280     /// [Bits 31:24] Core Clock Frequency to System Bus  Frequency Ratio (R)
 281     /// The processor core clock frequency to system bus frequency ratio
 282     /// observed at the de-assertion of the reset pin.
 283     ///
 284     UINT32  ClockRatio:8;
 285     UINT32  Reserved3:32;
 286   } Bits;
 287   ///
 288   /// All bit fields as a 32-bit value
 289   ///
 290   UINT32  Uint32;
 291   ///
 292   /// All bit fields as a 64-bit value
 293   ///
 294   UINT64  Uint64;
 295 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;
 296
 297
 298 /**
 299   0, 1. Shared. Processor Frequency Configuration (R)  The bit field layout of
 300   this MSR varies according to the MODEL value of the CPUID version
 301   information. This bit field layout applies to Pentium 4 and Xeon Processors
 302   with MODEL encoding less than 2. Indicates current processor frequency
 303   configuration.
 304
 305   @param  ECX  MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)
 306   @param  EAX  Lower 32-bits of MSR value.
 307                Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
 308   @param  EDX  Upper 32-bits of MSR value.
 309                Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
 310
 311   <b>Example usage</b>
 312   @code
 313   MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER  Msr;
 314
 315   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
 316   @endcode
 317 **/
 318 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1         0x0000002C
 319
 320 /**
 321   MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1
 322 **/
 323 typedef union {
 324   ///
 325   /// Individual bit fields
 326   ///
 327   struct {
 328     UINT32  Reserved1:21;
 329     ///
 330     /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable
 331     /// bus speed: *Encoding* *Scalable Bus Speed*
 332     ///
 333     ///   000B 100 MHz All others values reserved.
 334     ///
 335     UINT32  ScalableBusSpeed:3;
 336     UINT32  Reserved2:8;
 337     UINT32  Reserved3:32;
 338   } Bits;
 339   ///
 340   /// All bit fields as a 32-bit value
 341   ///
 342   UINT32  Uint32;
 343   ///
 344   /// All bit fields as a 64-bit value
 345   ///
 346   UINT64  Uint64;
 347 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;
 348
 349
 350 /**
 351   0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section
 352   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 353   state at time of machine check error. When in non-64-bit modes at the time
 354   of the error, bits 63-32 do not contain valid data.
 355
 356   @param  ECX  MSR_PENTIUM_4_MCG_RAX (0x00000180)
 357   @param  EAX  Lower 32-bits of MSR value.
 358   @param  EDX  Upper 32-bits of MSR value.
 359
 360   <b>Example usage</b>
 361   @code
 362   UINT64  Msr;
 363
 364   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
 365   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
 366   @endcode
 367 **/
 368 #define MSR_PENTIUM_4_MCG_RAX                    0x00000180
 369
 370
 371 /**
 372   0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section
 373   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 374   state at time of machine check error. When in non-64-bit modes at the time
 375   of the error, bits 63-32 do not contain valid data.
 376
 377   @param  ECX  MSR_PENTIUM_4_MCG_RBX (0x00000181)
 378   @param  EAX  Lower 32-bits of MSR value.
 379   @param  EDX  Upper 32-bits of MSR value.
 380
 381   <b>Example usage</b>
 382   @code
 383   UINT64  Msr;
 384
 385   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
 386   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
 387   @endcode
 388 **/
 389 #define MSR_PENTIUM_4_MCG_RBX                    0x00000181
 390
 391
 392 /**
 393   0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section
 394   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 395   state at time of machine check error. When in non-64-bit modes at the time
 396   of the error, bits 63-32 do not contain valid data.
 397
 398   @param  ECX  MSR_PENTIUM_4_MCG_RCX (0x00000182)
 399   @param  EAX  Lower 32-bits of MSR value.
 400   @param  EDX  Upper 32-bits of MSR value.
 401
 402   <b>Example usage</b>
 403   @code
 404   UINT64  Msr;
 405
 406   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
 407   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
 408   @endcode
 409 **/
 410 #define MSR_PENTIUM_4_MCG_RCX                    0x00000182
 411
 412
 413 /**
 414   0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section
 415   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 416   state at time of machine check error. When in non-64-bit modes at the time
 417   of the error, bits 63-32 do not contain valid data.
 418
 419   @param  ECX  MSR_PENTIUM_4_MCG_RDX (0x00000183)
 420   @param  EAX  Lower 32-bits of MSR value.
 421   @param  EDX  Upper 32-bits of MSR value.
 422
 423   <b>Example usage</b>
 424   @code
 425   UINT64  Msr;
 426
 427   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
 428   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
 429   @endcode
 430 **/
 431 #define MSR_PENTIUM_4_MCG_RDX                    0x00000183
 432
 433
 434 /**
 435   0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section
 436   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 437   state at time of machine check error. When in non-64-bit modes at the time
 438   of the error, bits 63-32 do not contain valid data.
 439
 440   @param  ECX  MSR_PENTIUM_4_MCG_RSI (0x00000184)
 441   @param  EAX  Lower 32-bits of MSR value.
 442   @param  EDX  Upper 32-bits of MSR value.
 443
 444   <b>Example usage</b>
 445   @code
 446   UINT64  Msr;
 447
 448   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
 449   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
 450   @endcode
 451 **/
 452 #define MSR_PENTIUM_4_MCG_RSI                    0x00000184
 453
 454
 455 /**
 456   0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section
 457   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 458   state at time of machine check error. When in non-64-bit modes at the time
 459   of the error, bits 63-32 do not contain valid data.
 460
 461   @param  ECX  MSR_PENTIUM_4_MCG_RDI (0x00000185)
 462   @param  EAX  Lower 32-bits of MSR value.
 463   @param  EDX  Upper 32-bits of MSR value.
 464
 465   <b>Example usage</b>
 466   @code
 467   UINT64  Msr;
 468
 469   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
 470   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
 471   @endcode
 472 **/
 473 #define MSR_PENTIUM_4_MCG_RDI                    0x00000185
 474
 475
 476 /**
 477   0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section
 478   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 479   state at time of machine check error. When in non-64-bit modes at the time
 480   of the error, bits 63-32 do not contain valid data.
 481
 482   @param  ECX  MSR_PENTIUM_4_MCG_RBP (0x00000186)
 483   @param  EAX  Lower 32-bits of MSR value.
 484   @param  EDX  Upper 32-bits of MSR value.
 485
 486   <b>Example usage</b>
 487   @code
 488   UINT64  Msr;
 489
 490   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
 491   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
 492   @endcode
 493 **/
 494 #define MSR_PENTIUM_4_MCG_RBP                    0x00000186
 495
 496
 497 /**
 498   0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section
 499   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 500   state at time of machine check error. When in non-64-bit modes at the time
 501   of the error, bits 63-32 do not contain valid data.
 502
 503   @param  ECX  MSR_PENTIUM_4_MCG_RSP (0x00000187)
 504   @param  EAX  Lower 32-bits of MSR value.
 505   @param  EDX  Upper 32-bits of MSR value.
 506
 507   <b>Example usage</b>
 508   @code
 509   UINT64  Msr;
 510
 511   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
 512   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
 513   @endcode
 514 **/
 515 #define MSR_PENTIUM_4_MCG_RSP                    0x00000187
 516
 517
 518 /**
 519   0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section
 520   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 521   state at time of machine check error. When in non-64-bit modes at the time
 522   of the error, bits 63-32 do not contain valid data.
 523
 524   @param  ECX  MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)
 525   @param  EAX  Lower 32-bits of MSR value.
 526   @param  EDX  Upper 32-bits of MSR value.
 527
 528   <b>Example usage</b>
 529   @code
 530   UINT64  Msr;
 531
 532   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
 533   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
 534   @endcode
 535 **/
 536 #define MSR_PENTIUM_4_MCG_RFLAGS                 0x00000188
 537
 538
 539 /**
 540   0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section
 541   15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
 542   state at time of machine check error. When in non-64-bit modes at the time
 543   of the error, bits 63-32 do not contain valid data.
 544
 545   @param  ECX  MSR_PENTIUM_4_MCG_RIP (0x00000189)
 546   @param  EAX  Lower 32-bits of MSR value.
 547   @param  EDX  Upper 32-bits of MSR value.
 548
 549   <b>Example usage</b>
 550   @code
 551   UINT64  Msr;
 552
 553   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
 554   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
 555   @endcode
 556 **/
 557 #define MSR_PENTIUM_4_MCG_RIP                    0x00000189
 558
 559
 560 /**
 561   0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,
 562   "IA32_MCG Extended Machine Check State MSRs.".
 563
 564   @param  ECX  MSR_PENTIUM_4_MCG_MISC (0x0000018A)
 565   @param  EAX  Lower 32-bits of MSR value.
 566                Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
 567   @param  EDX  Upper 32-bits of MSR value.
 568                Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
 569
 570   <b>Example usage</b>
 571   @code
 572   MSR_PENTIUM_4_MCG_MISC_REGISTER  Msr;
 573
 574   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
 575   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);
 576   @endcode
 577 **/
 578 #define MSR_PENTIUM_4_MCG_MISC                   0x0000018A
 579
 580 /**
 581   MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC
 582 **/
 583 typedef union {
 584   ///
 585   /// Individual bit fields
 586   ///
 587   struct {
 588     ///
 589     /// [Bit 0] DS When set, the bit indicates that a page assist or page
 590     /// fault occurred during DS normal operation. The processors response is
 591     /// to shut down. The bit is used as an aid for debugging DS handling
 592     /// code. It is the responsibility of the user (BIOS or operating system)
 593     /// to clear this bit for normal operation.
 594     ///
 595     UINT32  DS:1;
 596     UINT32  Reserved1:31;
 597     UINT32  Reserved2:32;
 598   } Bits;
 599   ///
 600   /// All bit fields as a 32-bit value
 601   ///
 602   UINT32  Uint32;
 603   ///
 604   /// All bit fields as a 64-bit value
 605   ///
 606   UINT64  Uint64;
 607 } MSR_PENTIUM_4_MCG_MISC_REGISTER;
 608
 609
 610 /**
 611   0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG
 612   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 613   state-save MSRs) exist only in Intel 64 processors. These registers contain
 614   valid information only when the processor is operating in 64-bit mode at the
 615   time of the error.
 616
 617   @param  ECX  MSR_PENTIUM_4_MCG_R8 (0x00000190)
 618   @param  EAX  Lower 32-bits of MSR value.
 619   @param  EDX  Upper 32-bits of MSR value.
 620
 621   <b>Example usage</b>
 622   @code
 623   UINT64  Msr;
 624
 625   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
 626   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);
 627   @endcode
 628 **/
 629 #define MSR_PENTIUM_4_MCG_R8                     0x00000190
 630
 631
 632 /**
 633   0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,
 634   "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the
 635   associated state-save MSRs) exist only in Intel 64 processors. These
 636   registers contain valid information only when the processor is operating in
 637   64-bit mode at the time of the error.
 638
 639   @param  ECX  MSR_PENTIUM_4_MCG_R9 (0x00000191)
 640   @param  EAX  Lower 32-bits of MSR value.
 641   @param  EDX  Upper 32-bits of MSR value.
 642
 643   <b>Example usage</b>
 644   @code
 645   UINT64  Msr;
 646
 647   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
 648   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);
 649   @endcode
 650 **/
 651 #define MSR_PENTIUM_4_MCG_R9                     0x00000191
 652
 653
 654 /**
 655   0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG
 656   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 657   state-save MSRs) exist only in Intel 64 processors. These registers contain
 658   valid information only when the processor is operating in 64-bit mode at the
 659   time of the error.
 660
 661   @param  ECX  MSR_PENTIUM_4_MCG_R10 (0x00000192)
 662   @param  EAX  Lower 32-bits of MSR value.
 663   @param  EDX  Upper 32-bits of MSR value.
 664
 665   <b>Example usage</b>
 666   @code
 667   UINT64  Msr;
 668
 669   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
 670   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);
 671   @endcode
 672 **/
 673 #define MSR_PENTIUM_4_MCG_R10                    0x00000192
 674
 675
 676 /**
 677   0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG
 678   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 679   state-save MSRs) exist only in Intel 64 processors. These registers contain
 680   valid information only when the processor is operating in 64-bit mode at the
 681   time of the error.
 682
 683   @param  ECX  MSR_PENTIUM_4_MCG_R11 (0x00000193)
 684   @param  EAX  Lower 32-bits of MSR value.
 685   @param  EDX  Upper 32-bits of MSR value.
 686
 687   <b>Example usage</b>
 688   @code
 689   UINT64  Msr;
 690
 691   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
 692   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);
 693   @endcode
 694 **/
 695 #define MSR_PENTIUM_4_MCG_R11                    0x00000193
 696
 697
 698 /**
 699   0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG
 700   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 701   state-save MSRs) exist only in Intel 64 processors. These registers contain
 702   valid information only when the processor is operating in 64-bit mode at the
 703   time of the error.
 704
 705   @param  ECX  MSR_PENTIUM_4_MCG_R12 (0x00000194)
 706   @param  EAX  Lower 32-bits of MSR value.
 707   @param  EDX  Upper 32-bits of MSR value.
 708
 709   <b>Example usage</b>
 710   @code
 711   UINT64  Msr;
 712
 713   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
 714   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);
 715   @endcode
 716 **/
 717 #define MSR_PENTIUM_4_MCG_R12                    0x00000194
 718
 719
 720 /**
 721   0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG
 722   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 723   state-save MSRs) exist only in Intel 64 processors. These registers contain
 724   valid information only when the processor is operating in 64-bit mode at the
 725   time of the error.
 726
 727   @param  ECX  MSR_PENTIUM_4_MCG_R13 (0x00000195)
 728   @param  EAX  Lower 32-bits of MSR value.
 729   @param  EDX  Upper 32-bits of MSR value.
 730
 731   <b>Example usage</b>
 732   @code
 733   UINT64  Msr;
 734
 735   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
 736   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);
 737   @endcode
 738 **/
 739 #define MSR_PENTIUM_4_MCG_R13                    0x00000195
 740
 741
 742 /**
 743   0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG
 744   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 745   state-save MSRs) exist only in Intel 64 processors. These registers contain
 746   valid information only when the processor is operating in 64-bit mode at the
 747   time of the error.
 748
 749   @param  ECX  MSR_PENTIUM_4_MCG_R14 (0x00000196)
 750   @param  EAX  Lower 32-bits of MSR value.
 751   @param  EDX  Upper 32-bits of MSR value.
 752
 753   <b>Example usage</b>
 754   @code
 755   UINT64  Msr;
 756
 757   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
 758   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);
 759   @endcode
 760 **/
 761 #define MSR_PENTIUM_4_MCG_R14                    0x00000196
 762
 763
 764 /**
 765   0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG
 766   Extended Machine Check State MSRs.". Registers R8-15 (and the associated
 767   state-save MSRs) exist only in Intel 64 processors. These registers contain
 768   valid information only when the processor is operating in 64-bit mode at the
 769   time of the error.
 770
 771   @param  ECX  MSR_PENTIUM_4_MCG_R15 (0x00000197)
 772   @param  EAX  Lower 32-bits of MSR value.
 773   @param  EDX  Upper 32-bits of MSR value.
 774
 775   <b>Example usage</b>
 776   @code
 777   UINT64  Msr;
 778
 779   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
 780   AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);
 781   @endcode
 782 **/
 783 #define MSR_PENTIUM_4_MCG_R15                    0x00000197
 784
 785
 786 /**
 787   Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:
 788   When read, specifies the value of the target TM2 transition last written.
 789   When set, it sets the next target value for TM2 transition. 4, 6. Shared.
 790   For Family F, Model 4 and Model 6 processors: When read, specifies the value
 791   of the target TM2 transition last written. Writes may cause #GP exceptions.
 792
 793   @param  ECX  MSR_PENTIUM_4_THERM2_CTL (0x0000019D)
 794   @param  EAX  Lower 32-bits of MSR value.
 795   @param  EDX  Upper 32-bits of MSR value.
 796
 797   <b>Example usage</b>
 798   @code
 799   UINT64  Msr;
 800
 801   Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
 802   AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);
 803   @endcode
 804 **/
 805 #define MSR_PENTIUM_4_THERM2_CTL                 0x0000019D
 806
 807
 808 /**
 809   0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).
 810
 811   @param  ECX  MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)
 812   @param  EAX  Lower 32-bits of MSR value.
 813                Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
 814   @param  EDX  Upper 32-bits of MSR value.
 815                Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
 816
 817   <b>Example usage</b>
 818   @code
 819   MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER  Msr;
 820
 821   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
 822   AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);
 823   @endcode
 824 **/
 825 #define MSR_PENTIUM_4_IA32_MISC_ENABLE           0x000001A0
 826
 827 /**
 828   MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE
 829 **/
 830 typedef union {
 831   ///
 832   /// Individual bit fields
 833   ///
 834   struct {
 835     ///
 836     /// [Bit 0] Fast-Strings Enable. See Table 35-2.
 837     ///
 838     UINT32  FastStrings:1;
 839     UINT32  Reserved1:1;
 840     ///
 841     /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.
 842     ///
 843     UINT32  FPU:1;
 844     ///
 845     /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
 846     /// Monitor," and see Table 35-2.
 847     ///
 848     UINT32  TM1:1;
 849     ///
 850     /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception
 851     /// to be issued instead of a split-lock cycle. Operating systems that set
 852     /// this bit must align system structures to avoid split-lock scenarios.
 853     /// When the bit is clear (default), normal split-locks are issued to the
 854     /// bus.
 855     ///   This debug feature is specific to the Pentium 4 processor.
 856     ///
 857     UINT32  SplitLockDisable:1;
 858     UINT32  Reserved2:1;
 859     ///
 860     /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level
 861     /// cache is disabled; when clear (default) the third-level cache is
 862     /// enabled. This flag is reserved for processors that do not have a
 863     /// third-level cache. Note that the bit controls only the third-level
 864     /// cache; and only if overall caching is enabled through the CD flag of
 865     /// control register CR0, the page-level cache controls, and/or the MTRRs.
 866     /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".
 867     ///
 868     UINT32  ThirdLevelCacheDisable:1;
 869     ///
 870     /// [Bit 7] Performance Monitoring Available (R) See Table 35-2.
 871     ///
 872     UINT32  PerformanceMonitoring:1;
 873     ///
 874     /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is
 875     /// suppressed during a Split Lock access. When clear (default), LOCK is
 876     /// not suppressed.
 877     ///
 878     UINT32  SuppressLockEnable:1;
 879     ///
 880     /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.
 881     /// When clear (default), enables the prefetch queue.
 882     ///
 883     UINT32  PrefetchQueueDisable:1;
 884     ///
 885     /// [Bit 10] FERR# Interrupt Reporting Enable (R/W)  When set, interrupt
 886     /// reporting through the FERR# pin is enabled; when clear, this interrupt
 887     /// reporting function is disabled.
 888     ///   When this flag is set and the processor is in the stop-clock state
 889     ///   (STPCLK# is asserted), asserting the FERR# pin signals to the
 890     ///   processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
 891     ///   SMI#, or RESET#) is pending and that the processor should return to
 892     ///   normal operation to handle the interrupt. This flag does not affect
 893     ///   the normal operation of the FERR# pin (to indicate an unmasked
 894     ///   floatingpoint error) when the STPCLK# pin is not asserted.
 895     ///
 896     UINT32  FERR:1;
 897     ///
 898     /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
 899     /// Table 35-2. When set, the processor does not support branch trace
 900     /// storage (BTS); when clear, BTS is supported.
 901     ///
 902     UINT32  BTS:1;
 903     ///
 904     /// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)
 905     /// See Table 35-2. When set, the processor does not support precise
 906     /// event-based sampling (PEBS); when clear, PEBS is supported.
 907     ///
 908     UINT32  PEBS:1;
 909     ///
 910     /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal
 911     /// sensor indicates that the die temperature is at the predetermined
 912     /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce
 913     /// the bus to core ratio and voltage according to the value last written
 914     /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the
 915     /// processor does not change the VID signals or the bus to core ratio
 916     /// when the processor enters a thermal managed state. If the TM2 feature
 917     /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then
 918     /// this feature is not supported and BIOS must not alter the contents of
 919     /// this bit location. The processor is operating out of spec if both this
 920     /// bit and the TM1 bit are set to disabled states.
 921     ///
 922     UINT32  TM2:1;
 923     UINT32  Reserved3:4;
 924     ///
 925     /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.
 926     ///
 927     UINT32  MONITOR:1;
 928     ///
 929     /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W)  When set to 1,
 930     /// the processor fetches the cache line of the 128-byte sector containing
 931     /// currently required data. When set to 0, the processor fetches both
 932     /// cache lines in the sector.
 933     ///   Single processor platforms should not set this bit. Server platforms
 934     ///   should set or clear this bit based on platform performance observed
 935     ///   in validation and testing. BIOS may contain a setup option that
 936     ///   controls the setting of this bit.
 937     ///
 938     UINT32  AdjacentCacheLinePrefetchDisable:1;
 939     UINT32  Reserved4:2;
 940     ///
 941     /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting
 942     /// this can cause unexpected behavior to software that depends on the
 943     /// availability of CPUID leaves greater than 3.
 944     ///
 945     UINT32  LimitCpuidMaxval:1;
 946     ///
 947     /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
 948     ///
 949     UINT32  xTPR_Message_Disable:1;
 950     ///
 951     /// [Bit 24] L1 Data Cache Context Mode (R/W)  When set, the L1 data cache
 952     /// is placed in shared mode; when clear (default), the cache is placed in
 953     /// adaptive mode. This bit is only enabled for IA-32 processors that
 954     /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data
 955     /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are
 956     /// identical, data in L1 is shared across logical processors. Otherwise,
 957     /// L1 is not shared and cache use is competitive. If the Context ID
 958     /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,
 959     /// the ability to switch modes is not supported. BIOS must not alter the
 960     /// contents of IA32_MISC_ENABLE[24].
 961     ///
 962     UINT32  L1DataCacheContextMode:1;
 963     UINT32  Reserved5:7;
 964     UINT32  Reserved6:2;
 965     ///
 966     /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
 967     ///
 968     UINT32  XD:1;
 969     UINT32  Reserved7:29;
 970   } Bits;
 971   ///
 972   /// All bit fields as a 64-bit value
 973   ///
 974   UINT64  Uint64;
 975 } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;
 976
 977
 978 /**
 979   3, 4, 6. Shared. Platform Feature Requirements (R).
 980
 981   @param  ECX  MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)
 982   @param  EAX  Lower 32-bits of MSR value.
 983                Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
 984   @param  EDX  Upper 32-bits of MSR value.
 985                Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
 986
 987   <b>Example usage</b>
 988   @code
 989   MSR_PENTIUM_4_PLATFORM_BRV_REGISTER  Msr;
 990
 991   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);
 992   @endcode
 993 **/
 994 #define MSR_PENTIUM_4_PLATFORM_BRV               0x000001A1
 995
 996 /**
 997   MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV
 998 **/
 999 typedef union {
1000   ///
1001   /// Individual bit fields
1002   ///
1003   struct {
1004     UINT32  Reserved1:18;
1005     ///
1006     /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor
1007     /// has specific platform requirements. The details of the platform
1008     /// requirements are listed in the respective data sheets of the processor.
1009     ///
1010     UINT32  PLATFORM:1;
1011     UINT32  Reserved2:13;
1012     UINT32  Reserved3:32;
1013   } Bits;
1014   ///
1015   /// All bit fields as a 32-bit value
1016   ///
1017   UINT32  Uint32;
1018   ///
1019   /// All bit fields as a 64-bit value
1020   ///
1021   UINT64  Uint64;
1022 } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;
1023
1024
1025 /**
1026   0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R)  Contains
1027   a pointer to the last branch instruction that the processor executed prior
1028   to the last exception that was generated or the last interrupt that was
1029   handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear
1030   IP Linear address of the last branch instruction (If IA32e mode is active).
1031   From Linear IP Linear address of the last branch instruction. Reserved.
1032
1033   @param  ECX  MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
1034   @param  EAX  Lower 32-bits of MSR value.
1035   @param  EDX  Upper 32-bits of MSR value.
1036
1037   <b>Example usage</b>
1038   @code
1039   UINT64  Msr;
1040
1041   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);
1042   @endcode
1043 **/
1044 #define MSR_PENTIUM_4_LER_FROM_LIP               0x000001D7
1045
1046
1047 /**
1048   0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R)  This area
1049   contains a pointer to the target of the last branch instruction that the
1050   processor executed prior to the last exception that was generated or the
1051   last interrupt that was handled. See Section 17.10.3, "Last Exception
1052   Records.". Unique. From Linear IP Linear address of the target of the last
1053   branch instruction (If IA-32e mode is active). From Linear IP Linear address
1054   of the target of the last branch instruction. Reserved.
1055
1056   @param  ECX  MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)
1057   @param  EAX  Lower 32-bits of MSR value.
1058   @param  EDX  Upper 32-bits of MSR value.
1059
1060   <b>Example usage</b>
1061   @code
1062   UINT64  Msr;
1063
1064   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);
1065   @endcode
1066 **/
1067 #define MSR_PENTIUM_4_LER_TO_LIP                 0x000001D8
1068
1069
1070 /**
1071   0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W)  Controls how several debug
1072   features are used. Bit definitions are discussed in the referenced section.
1073   See Section 17.10.1, "MSR_DEBUGCTLA MSR.".
1074
1075   @param  ECX  MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
1076   @param  EAX  Lower 32-bits of MSR value.
1077   @param  EDX  Upper 32-bits of MSR value.
1078
1079   <b>Example usage</b>
1080   @code
1081   UINT64  Msr;
1082
1083   Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
1084   AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);
1085   @endcode
1086 **/
1087 #define MSR_PENTIUM_4_DEBUGCTLA                  0x000001D9
1088
1089
1090 /**
1091   0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W)  Contains an
1092   index (0-3 or 0-15) that points to the top of the last branch record stack
1093   (that is, that points the index of the MSR containing the most recent branch
1094   record). See Section 17.10.2, "LBR Stack for Processors Based on Intel
1095   NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
1096
1097   @param  ECX  MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
1098   @param  EAX  Lower 32-bits of MSR value.
1099   @param  EDX  Upper 32-bits of MSR value.
1100
1101   <b>Example usage</b>
1102   @code
1103   UINT64  Msr;
1104
1105   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
1106   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);
1107   @endcode
1108 **/
1109 #define MSR_PENTIUM_4_LASTBRANCH_TOS             0x000001DA
1110
1111
1112 /**
1113   0, 1, 2. Unique. Last Branch Record n (R/W)  One of four last branch record
1114   registers on the last branch record stack. It contains pointers to the
1115   source and destination instruction for one of the last four branches,
1116   exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
1117   MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
1118   0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
1119   Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
1120   for Processors based on Skylake Microarchitecture.".
1121
1122   @param  ECX  MSR_PENTIUM_4_LASTBRANCH_n
1123   @param  EAX  Lower 32-bits of MSR value.
1124   @param  EDX  Upper 32-bits of MSR value.
1125
1126   <b>Example usage</b>
1127   @code
1128   UINT64  Msr;
1129
1130   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
1131   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);
1132   @endcode
1133   @{
1134 **/
1135 #define MSR_PENTIUM_4_LASTBRANCH_0               0x000001DB
1136 #define MSR_PENTIUM_4_LASTBRANCH_1               0x000001DC
1137 #define MSR_PENTIUM_4_LASTBRANCH_2               0x000001DD
1138 #define MSR_PENTIUM_4_LASTBRANCH_3               0x000001DE
1139 /// @}
1140
1141
1142 /**
1143   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
1144
1145   @param  ECX  MSR_PENTIUM_4_BPU_COUNTERn
1146   @param  EAX  Lower 32-bits of MSR value.
1147   @param  EDX  Upper 32-bits of MSR value.
1148
1149   <b>Example usage</b>
1150   @code
1151   UINT64  Msr;
1152
1153   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
1154   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);
1155   @endcode
1156   @{
1157 **/
1158 #define MSR_PENTIUM_4_BPU_COUNTER0               0x00000300
1159 #define MSR_PENTIUM_4_BPU_COUNTER1               0x00000301
1160 #define MSR_PENTIUM_4_BPU_COUNTER2               0x00000302
1161 #define MSR_PENTIUM_4_BPU_COUNTER3               0x00000303
1162 /// @}
1163
1164
1165 /**
1166   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
1167
1168   @param  ECX  MSR_PENTIUM_4_MS_COUNTERn
1169   @param  EAX  Lower 32-bits of MSR value.
1170   @param  EDX  Upper 32-bits of MSR value.
1171
1172   <b>Example usage</b>
1173   @code
1174   UINT64  Msr;
1175
1176   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
1177   AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);
1178   @endcode
1179   @{
1180 **/
1181 #define MSR_PENTIUM_4_MS_COUNTER0                0x00000304
1182 #define MSR_PENTIUM_4_MS_COUNTER1                0x00000305
1183 #define MSR_PENTIUM_4_MS_COUNTER2                0x00000306
1184 #define MSR_PENTIUM_4_MS_COUNTER3                0x00000307
1185 /// @}
1186
1187
1188 /**
1189   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
1190
1191   @param  ECX  MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
1192   @param  EAX  Lower 32-bits of MSR value.
1193   @param  EDX  Upper 32-bits of MSR value.
1194
1195   <b>Example usage</b>
1196   @code
1197   UINT64  Msr;
1198
1199   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
1200   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);
1201   @endcode
1202   @{
1203 **/
1204 #define MSR_PENTIUM_4_FLAME_COUNTER0             0x00000308
1205 #define MSR_PENTIUM_4_FLAME_COUNTER1             0x00000309
1206 #define MSR_PENTIUM_4_FLAME_COUNTER2             0x0000030A
1207 #define MSR_PENTIUM_4_FLAME_COUNTER3             0x0000030B
1208 /// @}
1209
1210
1211 /**
1212   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
1213
1214   @param  ECX  MSR_PENTIUM_4_IQ_COUNTERn
1215   @param  EAX  Lower 32-bits of MSR value.
1216   @param  EDX  Upper 32-bits of MSR value.
1217
1218   <b>Example usage</b>
1219   @code
1220   UINT64  Msr;
1221
1222   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
1223   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);
1224   @endcode
1225   @{
1226 **/
1227 #define MSR_PENTIUM_4_IQ_COUNTER0                0x0000030C
1228 #define MSR_PENTIUM_4_IQ_COUNTER1                0x0000030D
1229 #define MSR_PENTIUM_4_IQ_COUNTER2                0x0000030E
1230 #define MSR_PENTIUM_4_IQ_COUNTER3                0x0000030F
1231 #define MSR_PENTIUM_4_IQ_COUNTER4                0x00000310
1232 #define MSR_PENTIUM_4_IQ_COUNTER5                0x00000311
1233 /// @}
1234
1235
1236 /**
1237   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
1238
1239   @param  ECX  MSR_PENTIUM_4_BPU_CCCRn
1240   @param  EAX  Lower 32-bits of MSR value.
1241   @param  EDX  Upper 32-bits of MSR value.
1242
1243   <b>Example usage</b>
1244   @code
1245   UINT64  Msr;
1246
1247   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
1248   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);
1249   @endcode
1250   @{
1251 **/
1252 #define MSR_PENTIUM_4_BPU_CCCR0                  0x00000360
1253 #define MSR_PENTIUM_4_BPU_CCCR1                  0x00000361
1254 #define MSR_PENTIUM_4_BPU_CCCR2                  0x00000362
1255 #define MSR_PENTIUM_4_BPU_CCCR3                  0x00000363
1256 /// @}
1257
1258
1259 /**
1260   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
1261
1262   @param  ECX  MSR_PENTIUM_4_MS_CCCRn
1263   @param  EAX  Lower 32-bits of MSR value.
1264   @param  EDX  Upper 32-bits of MSR value.
1265
1266   <b>Example usage</b>
1267   @code
1268   UINT64  Msr;
1269
1270   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
1271   AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);
1272   @endcode
1273   @{
1274 **/
1275 #define MSR_PENTIUM_4_MS_CCCR0                   0x00000364
1276 #define MSR_PENTIUM_4_MS_CCCR1                   0x00000365
1277 #define MSR_PENTIUM_4_MS_CCCR2                   0x00000366
1278 #define MSR_PENTIUM_4_MS_CCCR3                   0x00000367
1279 /// @}
1280
1281
1282 /**
1283   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
1284
1285   @param  ECX  MSR_PENTIUM_4_FLAME_CCCRn
1286   @param  EAX  Lower 32-bits of MSR value.
1287   @param  EDX  Upper 32-bits of MSR value.
1288
1289   <b>Example usage</b>
1290   @code
1291   UINT64  Msr;
1292
1293   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
1294   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);
1295   @endcode
1296   @{
1297 **/
1298 #define MSR_PENTIUM_4_FLAME_CCCR0                0x00000368
1299 #define MSR_PENTIUM_4_FLAME_CCCR1                0x00000369
1300 #define MSR_PENTIUM_4_FLAME_CCCR2                0x0000036A
1301 #define MSR_PENTIUM_4_FLAME_CCCR3                0x0000036B
1302 /// @}
1303
1304
1305 /**
1306   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
1307
1308   @param  ECX  MSR_PENTIUM_4_IQ_CCCRn
1309   @param  EAX  Lower 32-bits of MSR value.
1310   @param  EDX  Upper 32-bits of MSR value.
1311
1312   <b>Example usage</b>
1313   @code
1314   UINT64  Msr;
1315
1316   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
1317   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);
1318   @endcode
1319   @{
1320 **/
1321 #define MSR_PENTIUM_4_IQ_CCCR0                   0x0000036C
1322 #define MSR_PENTIUM_4_IQ_CCCR1                   0x0000036D
1323 #define MSR_PENTIUM_4_IQ_CCCR2                   0x0000036E
1324 #define MSR_PENTIUM_4_IQ_CCCR3                   0x0000036F
1325 #define MSR_PENTIUM_4_IQ_CCCR4                   0x00000370
1326 #define MSR_PENTIUM_4_IQ_CCCR5                   0x00000371
1327 /// @}
1328
1329
1330 /**
1331   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1332
1333   @param  ECX  MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
1334   @param  EAX  Lower 32-bits of MSR value.
1335   @param  EDX  Upper 32-bits of MSR value.
1336
1337   <b>Example usage</b>
1338   @code
1339   UINT64  Msr;
1340
1341   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
1342   AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);
1343   @endcode
1344 **/
1345 #define MSR_PENTIUM_4_BSU_ESCR0                  0x000003A0
1346
1347
1348 /**
1349   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1350
1351   @param  ECX  MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
1352   @param  EAX  Lower 32-bits of MSR value.
1353   @param  EDX  Upper 32-bits of MSR value.
1354
1355   <b>Example usage</b>
1356   @code
1357   UINT64  Msr;
1358
1359   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
1360   AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);
1361   @endcode
1362 **/
1363 #define MSR_PENTIUM_4_BSU_ESCR1                  0x000003A1
1364
1365
1366 /**
1367   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1368
1369   @param  ECX  MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
1370   @param  EAX  Lower 32-bits of MSR value.
1371   @param  EDX  Upper 32-bits of MSR value.
1372
1373   <b>Example usage</b>
1374   @code
1375   UINT64  Msr;
1376
1377   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
1378   AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);
1379   @endcode
1380 **/
1381 #define MSR_PENTIUM_4_FSB_ESCR0                  0x000003A2
1382
1383
1384 /**
1385   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1386
1387   @param  ECX  MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
1388   @param  EAX  Lower 32-bits of MSR value.
1389   @param  EDX  Upper 32-bits of MSR value.
1390
1391   <b>Example usage</b>
1392   @code
1393   UINT64  Msr;
1394
1395   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
1396   AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);
1397   @endcode
1398 **/
1399 #define MSR_PENTIUM_4_FSB_ESCR1                  0x000003A3
1400
1401
1402 /**
1403   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1404
1405   @param  ECX  MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
1406   @param  EAX  Lower 32-bits of MSR value.
1407   @param  EDX  Upper 32-bits of MSR value.
1408
1409   <b>Example usage</b>
1410   @code
1411   UINT64  Msr;
1412
1413   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
1414   AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);
1415   @endcode
1416 **/
1417 #define MSR_PENTIUM_4_FIRM_ESCR0                 0x000003A4
1418
1419
1420 /**
1421   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1422
1423   @param  ECX  MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
1424   @param  EAX  Lower 32-bits of MSR value.
1425   @param  EDX  Upper 32-bits of MSR value.
1426
1427   <b>Example usage</b>
1428   @code
1429   UINT64  Msr;
1430
1431   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
1432   AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);
1433   @endcode
1434 **/
1435 #define MSR_PENTIUM_4_FIRM_ESCR1                 0x000003A5
1436
1437
1438 /**
1439   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1440
1441   @param  ECX  MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
1442   @param  EAX  Lower 32-bits of MSR value.
1443   @param  EDX  Upper 32-bits of MSR value.
1444
1445   <b>Example usage</b>
1446   @code
1447   UINT64  Msr;
1448
1449   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
1450   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);
1451   @endcode
1452 **/
1453 #define MSR_PENTIUM_4_FLAME_ESCR0                0x000003A6
1454
1455
1456 /**
1457   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1458
1459   @param  ECX  MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
1460   @param  EAX  Lower 32-bits of MSR value.
1461   @param  EDX  Upper 32-bits of MSR value.
1462
1463   <b>Example usage</b>
1464   @code
1465   UINT64  Msr;
1466
1467   Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
1468   AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);
1469   @endcode
1470 **/
1471 #define MSR_PENTIUM_4_FLAME_ESCR1                0x000003A7
1472
1473
1474 /**
1475   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1476
1477   @param  ECX  MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
1478   @param  EAX  Lower 32-bits of MSR value.
1479   @param  EDX  Upper 32-bits of MSR value.
1480
1481   <b>Example usage</b>
1482   @code
1483   UINT64  Msr;
1484
1485   Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
1486   AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);
1487   @endcode
1488 **/
1489 #define MSR_PENTIUM_4_DAC_ESCR0                  0x000003A8
1490
1491
1492 /**
1493   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1494
1495   @param  ECX  MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
1496   @param  EAX  Lower 32-bits of MSR value.
1497   @param  EDX  Upper 32-bits of MSR value.
1498
1499   <b>Example usage</b>
1500   @code
1501   UINT64  Msr;
1502
1503   Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
1504   AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);
1505   @endcode
1506 **/
1507 #define MSR_PENTIUM_4_DAC_ESCR1                  0x000003A9
1508
1509
1510 /**
1511   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1512
1513   @param  ECX  MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
1514   @param  EAX  Lower 32-bits of MSR value.
1515   @param  EDX  Upper 32-bits of MSR value.
1516
1517   <b>Example usage</b>
1518   @code
1519   UINT64  Msr;
1520
1521   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
1522   AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);
1523   @endcode
1524 **/
1525 #define MSR_PENTIUM_4_MOB_ESCR0                  0x000003AA
1526
1527
1528 /**
1529   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1530
1531   @param  ECX  MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
1532   @param  EAX  Lower 32-bits of MSR value.
1533   @param  EDX  Upper 32-bits of MSR value.
1534
1535   <b>Example usage</b>
1536   @code
1537   UINT64  Msr;
1538
1539   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
1540   AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);
1541   @endcode
1542 **/
1543 #define MSR_PENTIUM_4_MOB_ESCR1                  0x000003AB
1544
1545
1546 /**
1547   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1548
1549   @param  ECX  MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
1550   @param  EAX  Lower 32-bits of MSR value.
1551   @param  EDX  Upper 32-bits of MSR value.
1552
1553   <b>Example usage</b>
1554   @code
1555   UINT64  Msr;
1556
1557   Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
1558   AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);
1559   @endcode
1560 **/
1561 #define MSR_PENTIUM_4_PMH_ESCR0                  0x000003AC
1562
1563
1564 /**
1565   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1566
1567   @param  ECX  MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
1568   @param  EAX  Lower 32-bits of MSR value.
1569   @param  EDX  Upper 32-bits of MSR value.
1570
1571   <b>Example usage</b>
1572   @code
1573   UINT64  Msr;
1574
1575   Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
1576   AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);
1577   @endcode
1578 **/
1579 #define MSR_PENTIUM_4_PMH_ESCR1                  0x000003AD
1580
1581
1582 /**
1583   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1584
1585   @param  ECX  MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
1586   @param  EAX  Lower 32-bits of MSR value.
1587   @param  EDX  Upper 32-bits of MSR value.
1588
1589   <b>Example usage</b>
1590   @code
1591   UINT64  Msr;
1592
1593   Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
1594   AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);
1595   @endcode
1596 **/
1597 #define MSR_PENTIUM_4_SAAT_ESCR0                 0x000003AE
1598
1599
1600 /**
1601   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1602
1603   @param  ECX  MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
1604   @param  EAX  Lower 32-bits of MSR value.
1605   @param  EDX  Upper 32-bits of MSR value.
1606
1607   <b>Example usage</b>
1608   @code
1609   UINT64  Msr;
1610
1611   Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
1612   AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);
1613   @endcode
1614 **/
1615 #define MSR_PENTIUM_4_SAAT_ESCR1                 0x000003AF
1616
1617
1618 /**
1619   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1620
1621   @param  ECX  MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
1622   @param  EAX  Lower 32-bits of MSR value.
1623   @param  EDX  Upper 32-bits of MSR value.
1624
1625   <b>Example usage</b>
1626   @code
1627   UINT64  Msr;
1628
1629   Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
1630   AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);
1631   @endcode
1632 **/
1633 #define MSR_PENTIUM_4_U2L_ESCR0                  0x000003B0
1634
1635
1636 /**
1637   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1638
1639   @param  ECX  MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
1640   @param  EAX  Lower 32-bits of MSR value.
1641   @param  EDX  Upper 32-bits of MSR value.
1642
1643   <b>Example usage</b>
1644   @code
1645   UINT64  Msr;
1646
1647   Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
1648   AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);
1649   @endcode
1650 **/
1651 #define MSR_PENTIUM_4_U2L_ESCR1                  0x000003B1
1652
1653
1654 /**
1655   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1656
1657   @param  ECX  MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
1658   @param  EAX  Lower 32-bits of MSR value.
1659   @param  EDX  Upper 32-bits of MSR value.
1660
1661   <b>Example usage</b>
1662   @code
1663   UINT64  Msr;
1664
1665   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
1666   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);
1667   @endcode
1668 **/
1669 #define MSR_PENTIUM_4_BPU_ESCR0                  0x000003B2
1670
1671
1672 /**
1673   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1674
1675   @param  ECX  MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
1676   @param  EAX  Lower 32-bits of MSR value.
1677   @param  EDX  Upper 32-bits of MSR value.
1678
1679   <b>Example usage</b>
1680   @code
1681   UINT64  Msr;
1682
1683   Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
1684   AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);
1685   @endcode
1686 **/
1687 #define MSR_PENTIUM_4_BPU_ESCR1                  0x000003B3
1688
1689
1690 /**
1691   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1692
1693   @param  ECX  MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
1694   @param  EAX  Lower 32-bits of MSR value.
1695   @param  EDX  Upper 32-bits of MSR value.
1696
1697   <b>Example usage</b>
1698   @code
1699   UINT64  Msr;
1700
1701   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
1702   AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);
1703   @endcode
1704 **/
1705 #define MSR_PENTIUM_4_IS_ESCR0                   0x000003B4
1706
1707
1708 /**
1709   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1710
1711   @param  ECX  MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
1712   @param  EAX  Lower 32-bits of MSR value.
1713   @param  EDX  Upper 32-bits of MSR value.
1714
1715   <b>Example usage</b>
1716   @code
1717   UINT64  Msr;
1718
1719   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
1720   AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);
1721   @endcode
1722 **/
1723 #define MSR_PENTIUM_4_IS_ESCR1                   0x000003B5
1724
1725
1726 /**
1727   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1728
1729   @param  ECX  MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
1730   @param  EAX  Lower 32-bits of MSR value.
1731   @param  EDX  Upper 32-bits of MSR value.
1732
1733   <b>Example usage</b>
1734   @code
1735   UINT64  Msr;
1736
1737   Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
1738   AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);
1739   @endcode
1740 **/
1741 #define MSR_PENTIUM_4_ITLB_ESCR0                 0x000003B6
1742
1743
1744 /**
1745   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1746
1747   @param  ECX  MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
1748   @param  EAX  Lower 32-bits of MSR value.
1749   @param  EDX  Upper 32-bits of MSR value.
1750
1751   <b>Example usage</b>
1752   @code
1753   UINT64  Msr;
1754
1755   Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
1756   AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);
1757   @endcode
1758 **/
1759 #define MSR_PENTIUM_4_ITLB_ESCR1                 0x000003B7
1760
1761
1762 /**
1763   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1764
1765   @param  ECX  MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
1766   @param  EAX  Lower 32-bits of MSR value.
1767   @param  EDX  Upper 32-bits of MSR value.
1768
1769   <b>Example usage</b>
1770   @code
1771   UINT64  Msr;
1772
1773   Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
1774   AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);
1775   @endcode
1776 **/
1777 #define MSR_PENTIUM_4_CRU_ESCR0                  0x000003B8
1778
1779
1780 /**
1781   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1782
1783   @param  ECX  MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
1784   @param  EAX  Lower 32-bits of MSR value.
1785   @param  EDX  Upper 32-bits of MSR value.
1786
1787   <b>Example usage</b>
1788   @code
1789   UINT64  Msr;
1790
1791   Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
1792   AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);
1793   @endcode
1794 **/
1795 #define MSR_PENTIUM_4_CRU_ESCR1                  0x000003B9
1796
1797
1798 /**
1799   0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
1800   on later processors. It is only available on processor family 0FH, models
1801   01H-02H.
1802
1803   @param  ECX  MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
1804   @param  EAX  Lower 32-bits of MSR value.
1805   @param  EDX  Upper 32-bits of MSR value.
1806
1807   <b>Example usage</b>
1808   @code
1809   UINT64  Msr;
1810
1811   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
1812   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);
1813   @endcode
1814 **/
1815 #define MSR_PENTIUM_4_IQ_ESCR0                   0x000003BA
1816
1817
1818 /**
1819   0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
1820   on later processors. It is only available on processor family 0FH, models
1821   01H-02H.
1822
1823   @param  ECX  MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
1824   @param  EAX  Lower 32-bits of MSR value.
1825   @param  EDX  Upper 32-bits of MSR value.
1826
1827   <b>Example usage</b>
1828   @code
1829   UINT64  Msr;
1830
1831   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
1832   AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);
1833   @endcode
1834 **/
1835 #define MSR_PENTIUM_4_IQ_ESCR1                   0x000003BB
1836
1837
1838 /**
1839   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1840
1841   @param  ECX  MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
1842   @param  EAX  Lower 32-bits of MSR value.
1843   @param  EDX  Upper 32-bits of MSR value.
1844
1845   <b>Example usage</b>
1846   @code
1847   UINT64  Msr;
1848
1849   Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
1850   AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);
1851   @endcode
1852 **/
1853 #define MSR_PENTIUM_4_RAT_ESCR0                  0x000003BC
1854
1855
1856 /**
1857   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1858
1859   @param  ECX  MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
1860   @param  EAX  Lower 32-bits of MSR value.
1861   @param  EDX  Upper 32-bits of MSR value.
1862
1863   <b>Example usage</b>
1864   @code
1865   UINT64  Msr;
1866
1867   Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
1868   AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);
1869   @endcode
1870 **/
1871 #define MSR_PENTIUM_4_RAT_ESCR1                  0x000003BD
1872
1873
1874 /**
1875   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1876
1877   @param  ECX  MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
1878   @param  EAX  Lower 32-bits of MSR value.
1879   @param  EDX  Upper 32-bits of MSR value.
1880
1881   <b>Example usage</b>
1882   @code
1883   UINT64  Msr;
1884
1885   Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
1886   AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);
1887   @endcode
1888 **/
1889 #define MSR_PENTIUM_4_SSU_ESCR0                  0x000003BE
1890
1891
1892 /**
1893   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1894
1895   @param  ECX  MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
1896   @param  EAX  Lower 32-bits of MSR value.
1897   @param  EDX  Upper 32-bits of MSR value.
1898
1899   <b>Example usage</b>
1900   @code
1901   UINT64  Msr;
1902
1903   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
1904   AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);
1905   @endcode
1906 **/
1907 #define MSR_PENTIUM_4_MS_ESCR0                   0x000003C0
1908
1909
1910 /**
1911   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1912
1913   @param  ECX  MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
1914   @param  EAX  Lower 32-bits of MSR value.
1915   @param  EDX  Upper 32-bits of MSR value.
1916
1917   <b>Example usage</b>
1918   @code
1919   UINT64  Msr;
1920
1921   Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
1922   AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);
1923   @endcode
1924 **/
1925 #define MSR_PENTIUM_4_MS_ESCR1                   0x000003C1
1926
1927
1928 /**
1929   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1930
1931   @param  ECX  MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
1932   @param  EAX  Lower 32-bits of MSR value.
1933   @param  EDX  Upper 32-bits of MSR value.
1934
1935   <b>Example usage</b>
1936   @code
1937   UINT64  Msr;
1938
1939   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
1940   AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);
1941   @endcode
1942 **/
1943 #define MSR_PENTIUM_4_TBPU_ESCR0                 0x000003C2
1944
1945
1946 /**
1947   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1948
1949   @param  ECX  MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
1950   @param  EAX  Lower 32-bits of MSR value.
1951   @param  EDX  Upper 32-bits of MSR value.
1952
1953   <b>Example usage</b>
1954   @code
1955   UINT64  Msr;
1956
1957   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
1958   AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);
1959   @endcode
1960 **/
1961 #define MSR_PENTIUM_4_TBPU_ESCR1                 0x000003C3
1962
1963
1964 /**
1965   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1966
1967   @param  ECX  MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
1968   @param  EAX  Lower 32-bits of MSR value.
1969   @param  EDX  Upper 32-bits of MSR value.
1970
1971   <b>Example usage</b>
1972   @code
1973   UINT64  Msr;
1974
1975   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
1976   AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);
1977   @endcode
1978 **/
1979 #define MSR_PENTIUM_4_TC_ESCR0                   0x000003C4
1980
1981
1982 /**
1983   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
1984
1985   @param  ECX  MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
1986   @param  EAX  Lower 32-bits of MSR value.
1987   @param  EDX  Upper 32-bits of MSR value.
1988
1989   <b>Example usage</b>
1990   @code
1991   UINT64  Msr;
1992
1993   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
1994   AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);
1995   @endcode
1996 **/
1997 #define MSR_PENTIUM_4_TC_ESCR1                   0x000003C5
1998
1999
2000 /**
2001   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
2002
2003   @param  ECX  MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
2004   @param  EAX  Lower 32-bits of MSR value.
2005   @param  EDX  Upper 32-bits of MSR value.
2006
2007   <b>Example usage</b>
2008   @code
2009   UINT64  Msr;
2010
2011   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
2012   AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);
2013   @endcode
2014 **/
2015 #define MSR_PENTIUM_4_IX_ESCR0                   0x000003C8
2016
2017
2018 /**
2019   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
2020
2021   @param  ECX  MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
2022   @param  EAX  Lower 32-bits of MSR value.
2023   @param  EDX  Upper 32-bits of MSR value.
2024
2025   <b>Example usage</b>
2026   @code
2027   UINT64  Msr;
2028
2029   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
2030   AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);
2031   @endcode
2032 **/
2033 #define MSR_PENTIUM_4_IX_ESCR1                   0x000003C9
2034
2035
2036 /**
2037   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
2038
2039   @param  ECX  MSR_PENTIUM_4_ALF_ESCRn
2040   @param  EAX  Lower 32-bits of MSR value.
2041   @param  EDX  Upper 32-bits of MSR value.
2042
2043   <b>Example usage</b>
2044   @code
2045   UINT64  Msr;
2046
2047   Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
2048   AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);
2049   @endcode
2050   @{
2051 **/
2052 #define MSR_PENTIUM_4_ALF_ESCR0                  0x000003CA
2053 #define MSR_PENTIUM_4_ALF_ESCR1                  0x000003CB
2054 #define MSR_PENTIUM_4_CRU_ESCR2                  0x000003CC
2055 #define MSR_PENTIUM_4_CRU_ESCR3                  0x000003CD
2056 #define MSR_PENTIUM_4_CRU_ESCR4                  0x000003E0
2057 #define MSR_PENTIUM_4_CRU_ESCR5                  0x000003E1
2058 /// @}
2059
2060
2061 /**
2062   0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
2063
2064   @param  ECX  MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
2065   @param  EAX  Lower 32-bits of MSR value.
2066   @param  EDX  Upper 32-bits of MSR value.
2067
2068   <b>Example usage</b>
2069   @code
2070   UINT64  Msr;
2071
2072   Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
2073   AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);
2074   @endcode
2075 **/
2076 #define MSR_PENTIUM_4_TC_PRECISE_EVENT           0x000003F0
2077
2078
2079 /**
2080   0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)
2081   Controls the enabling of precise event sampling and replay tagging.
2082
2083   @param  ECX  MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
2084   @param  EAX  Lower 32-bits of MSR value.
2085                Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
2086   @param  EDX  Upper 32-bits of MSR value.
2087                Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
2088
2089   <b>Example usage</b>
2090   @code
2091   MSR_PENTIUM_4_PEBS_ENABLE_REGISTER  Msr;
2092
2093   Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
2094   AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);
2095   @endcode
2096 **/
2097 #define MSR_PENTIUM_4_PEBS_ENABLE                0x000003F1
2098
2099 /**
2100   MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE
2101 **/
2102 typedef union {
2103   ///
2104   /// Individual bit fields
2105   ///
2106   struct {
2107     ///
2108     /// [Bits 12:0] See Table 19-26.
2109     ///
2110     UINT32  EventNum:13;
2111     UINT32  Reserved1:11;
2112     ///
2113     /// [Bit 24] UOP Tag  Enables replay tagging when set.
2114     ///
2115     UINT32  UOP:1;
2116     ///
2117     /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
2118     /// processor when set; disables PEBS when clear (default). See Section
2119     /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
2120     /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
2121     /// that do not support Intel HyperThreading Technology.
2122     ///
2123     UINT32  ENABLE_PEBS_MY_THR:1;
2124     ///
2125     /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
2126     /// processor when set; disables PEBS when clear (default). See Section
2127     /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
2128     /// logical processor. This bit is reserved for IA-32 processors that do
2129     /// not support Intel Hyper-Threading Technology.
2130     ///
2131     UINT32  ENABLE_PEBS_OTH_THR:1;
2132     UINT32  Reserved2:5;
2133     UINT32  Reserved3:32;
2134   } Bits;
2135   ///
2136   /// All bit fields as a 32-bit value
2137   ///
2138   UINT32  Uint32;
2139   ///
2140   /// All bit fields as a 64-bit value
2141   ///
2142   UINT64  Uint64;
2143 } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;
2144
2145
2146 /**
2147   0, 1, 2, 3, 4, 6. Shared. See Table 19-26.
2148
2149   @param  ECX  MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
2150   @param  EAX  Lower 32-bits of MSR value.
2151   @param  EDX  Upper 32-bits of MSR value.
2152
2153   <b>Example usage</b>
2154   @code
2155   UINT64  Msr;
2156
2157   Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
2158   AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);
2159   @endcode
2160 **/
2161 #define MSR_PENTIUM_4_PEBS_MATRIX_VERT           0x000003F2
2162
2163
2164 /**
2165   3, 4, 6. Unique. Last Branch Record n (R/W)  One of 16 pairs of last branch
2166   record registers on the last branch record stack (680H-68FH). This part of
2167   the stack contains pointers to the source instruction for one of the last 16
2168   branches, exceptions, or interrupts taken by the processor. The MSRs at
2169   680H-68FH, 6C0H-6CfH are not available in processor releases before family
2170   0FH, model 03H. These MSRs replace MSRs previously located at
2171   1DBH-1DEH.which performed the same function for early releases. See Section
2172   17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for
2173   Processors based on Skylake Microarchitecture.".
2174
2175   @param  ECX  MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
2176   @param  EAX  Lower 32-bits of MSR value.
2177   @param  EDX  Upper 32-bits of MSR value.
2178
2179   <b>Example usage</b>
2180   @code
2181   UINT64  Msr;
2182
2183   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
2184   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);
2185   @endcode
2186   @{
2187 **/
2188 #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP       0x00000680
2189 #define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP       0x00000681
2190 #define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP       0x00000682
2191 #define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP       0x00000683
2192 #define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP       0x00000684
2193 #define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP       0x00000685
2194 #define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP       0x00000686
2195 #define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP       0x00000687
2196 #define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP       0x00000688
2197 #define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP       0x00000689
2198 #define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP      0x0000068A
2199 #define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP      0x0000068B
2200 #define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP      0x0000068C
2201 #define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP      0x0000068D
2202 #define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP      0x0000068E
2203 #define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP      0x0000068F
2204 /// @}
2205
2206
2207 /**
2208   3, 4, 6. Unique. Last Branch Record n (R/W)  One of 16 pairs of last branch
2209   record registers on the last branch record stack (6C0H-6CFH). This part of
2210   the stack contains pointers to the destination instruction for one of the
2211   last 16 branches, exceptions, or interrupts that the processor took. See
2212   Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
2213   for Processors based on Skylake Microarchitecture.".
2214
2215   @param  ECX  MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
2216   @param  EAX  Lower 32-bits of MSR value.
2217   @param  EDX  Upper 32-bits of MSR value.
2218
2219   <b>Example usage</b>
2220   @code
2221   UINT64  Msr;
2222
2223   Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
2224   AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);
2225   @endcode
2226   @{
2227 **/
2228 #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP         0x000006C0
2229 #define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP         0x000006C1
2230 #define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP         0x000006C2
2231 #define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP         0x000006C3
2232 #define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP         0x000006C4
2233 #define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP         0x000006C5
2234 #define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP         0x000006C6
2235 #define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP         0x000006C7
2236 #define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP         0x000006C8
2237 #define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP         0x000006C9
2238 #define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP        0x000006CA
2239 #define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP        0x000006CB
2240 #define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP        0x000006CC
2241 #define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP        0x000006CD
2242 #define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP        0x000006CE
2243 #define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP        0x000006CF
2244 /// @}
2245
2246
2247 /**
2248   3, 4. Shared. IFSB BUSQ Event Control and Counter  Register (R/W) See
2249   Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
2250   with Up to 8-MByte L3 Cache.".
2251
2252   @param  ECX  MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
2253   @param  EAX  Lower 32-bits of MSR value.
2254   @param  EDX  Upper 32-bits of MSR value.
2255
2256   <b>Example usage</b>
2257   @code
2258   UINT64  Msr;
2259
2260   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
2261   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);
2262   @endcode
2263 **/
2264 #define MSR_PENTIUM_4_IFSB_BUSQ0                 0x000107CC
2265
2266
2267 /**
2268   3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).
2269
2270   @param  ECX  MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)
2271   @param  EAX  Lower 32-bits of MSR value.
2272   @param  EDX  Upper 32-bits of MSR value.
2273
2274   <b>Example usage</b>
2275   @code
2276   UINT64  Msr;
2277
2278   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
2279   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);
2280   @endcode
2281 **/
2282 #define MSR_PENTIUM_4_IFSB_BUSQ1                 0x000107CD
2283
2284
2285 /**
2286   3, 4. Shared. IFSB SNPQ Event Control and Counter  Register (R/W)  See
2287   Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
2288   with Up to 8-MByte L3 Cache.".
2289
2290   @param  ECX  MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
2291   @param  EAX  Lower 32-bits of MSR value.
2292   @param  EDX  Upper 32-bits of MSR value.
2293
2294   <b>Example usage</b>
2295   @code
2296   UINT64  Msr;
2297
2298   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
2299   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);
2300   @endcode
2301 **/
2302 #define MSR_PENTIUM_4_IFSB_SNPQ0                 0x000107CE
2303
2304
2305 /**
2306   3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).
2307
2308   @param  ECX  MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)
2309   @param  EAX  Lower 32-bits of MSR value.
2310   @param  EDX  Upper 32-bits of MSR value.
2311
2312   <b>Example usage</b>
2313   @code
2314   UINT64  Msr;
2315
2316   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
2317   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);
2318   @endcode
2319 **/
2320 #define MSR_PENTIUM_4_IFSB_SNPQ1                 0x000107CF
2321
2322
2323 /**
2324   3, 4. Shared. EFSB DRDY Event Control and Counter  Register (R/W)  See
2325   Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
2326   with Up to 8-MByte L3 Cache" for details.
2327
2328   @param  ECX  MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
2329   @param  EAX  Lower 32-bits of MSR value.
2330   @param  EDX  Upper 32-bits of MSR value.
2331
2332   <b>Example usage</b>
2333   @code
2334   UINT64  Msr;
2335
2336   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
2337   AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);
2338   @endcode
2339 **/
2340 #define MSR_PENTIUM_4_EFSB_DRDY0                 0x000107D0
2341
2342
2343 /**
2344   3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).
2345
2346   @param  ECX  MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)
2347   @param  EAX  Lower 32-bits of MSR value.
2348   @param  EDX  Upper 32-bits of MSR value.
2349
2350   <b>Example usage</b>
2351   @code
2352   UINT64  Msr;
2353
2354   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
2355   AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);
2356   @endcode
2357 **/
2358 #define MSR_PENTIUM_4_EFSB_DRDY1                 0x000107D1
2359
2360
2361 /**
2362   3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,
2363   "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
2364   L3 Cache" for details.
2365
2366   @param  ECX  MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
2367   @param  EAX  Lower 32-bits of MSR value.
2368   @param  EDX  Upper 32-bits of MSR value.
2369
2370   <b>Example usage</b>
2371   @code
2372   UINT64  Msr;
2373
2374   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
2375   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);
2376   @endcode
2377 **/
2378 #define MSR_PENTIUM_4_IFSB_CTL6                  0x000107D2
2379
2380
2381 /**
2382   3, 4. Shared. IFSB Latency Event Counter Register  (R/W)  See Section 18.17,
2383   "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
2384   L3 Cache.".
2385
2386   @param  ECX  MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
2387   @param  EAX  Lower 32-bits of MSR value.
2388   @param  EDX  Upper 32-bits of MSR value.
2389
2390   <b>Example usage</b>
2391   @code
2392   UINT64  Msr;
2393
2394   Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
2395   AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);
2396   @endcode
2397 **/
2398 #define MSR_PENTIUM_4_IFSB_CNTR7                 0x000107D3
2399
2400
2401 /**
2402   6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,
2403   "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
2404   L3 Cache.".
2405
2406   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
2407   @param  EAX  Lower 32-bits of MSR value.
2408   @param  EDX  Upper 32-bits of MSR value.
2409
2410   <b>Example usage</b>
2411   @code
2412   UINT64  Msr;
2413
2414   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
2415   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);
2416   @endcode
2417 **/
2418 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0           0x000107CC
2419
2420
2421 /**
2422   6. Shared. GBUSQ Event Control and Counter Register (R/W).
2423
2424   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)
2425   @param  EAX  Lower 32-bits of MSR value.
2426   @param  EDX  Upper 32-bits of MSR value.
2427
2428   <b>Example usage</b>
2429   @code
2430   UINT64  Msr;
2431
2432   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
2433   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);
2434   @endcode
2435 **/
2436 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1           0x000107CD
2437
2438
2439 /**
2440   6. Shared. GSNPQ Event Control and Counter Register (R/W)  See Section
2441   18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
2442   8-MByte L3 Cache.".
2443
2444   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
2445   @param  EAX  Lower 32-bits of MSR value.
2446   @param  EDX  Upper 32-bits of MSR value.
2447
2448   <b>Example usage</b>
2449   @code
2450   UINT64  Msr;
2451
2452   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
2453   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);
2454   @endcode
2455 **/
2456 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2           0x000107CE
2457
2458
2459 /**
2460   6. Shared. GSNPQ Event Control and Counter Register (R/W).
2461
2462   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)
2463   @param  EAX  Lower 32-bits of MSR value.
2464   @param  EDX  Upper 32-bits of MSR value.
2465
2466   <b>Example usage</b>
2467   @code
2468   UINT64  Msr;
2469
2470   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
2471   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);
2472   @endcode
2473 **/
2474 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3           0x000107CF
2475
2476
2477 /**
2478   6. Shared. FSB Event Control and Counter Register  (R/W)  See Section 18.17,
2479   "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
2480   L3 Cache" for details.
2481
2482   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
2483   @param  EAX  Lower 32-bits of MSR value.
2484   @param  EDX  Upper 32-bits of MSR value.
2485
2486   <b>Example usage</b>
2487   @code
2488   UINT64  Msr;
2489
2490   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
2491   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);
2492   @endcode
2493 **/
2494 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4           0x000107D0
2495
2496
2497 /**
2498   6. Shared. FSB Event Control and Counter Register (R/W).
2499
2500   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)
2501   @param  EAX  Lower 32-bits of MSR value.
2502   @param  EDX  Upper 32-bits of MSR value.
2503
2504   <b>Example usage</b>
2505   @code
2506   UINT64  Msr;
2507
2508   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
2509   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);
2510   @endcode
2511 **/
2512 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5           0x000107D1
2513
2514
2515 /**
2516   6. Shared. FSB Event Control and Counter Register (R/W).
2517
2518   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)
2519   @param  EAX  Lower 32-bits of MSR value.
2520   @param  EDX  Upper 32-bits of MSR value.
2521
2522   <b>Example usage</b>
2523   @code
2524   UINT64  Msr;
2525
2526   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
2527   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);
2528   @endcode
2529 **/
2530 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6           0x000107D2
2531
2532
2533 /**
2534   6. Shared. FSB Event Control and Counter Register (R/W).
2535
2536   @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)
2537   @param  EAX  Lower 32-bits of MSR value.
2538   @param  EDX  Upper 32-bits of MSR value.
2539
2540   <b>Example usage</b>
2541   @code
2542   UINT64  Msr;
2543
2544   Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
2545   AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);
2546   @endcode
2547 **/
2548 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7           0x000107D3
2549
2550 #endif