UefiCpuPkg/Include/Register/Msr/PentiumMsr.h

   1 /** @file
   2   MSR Definitions for Pentium Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __PENTIUM_MSR_H__
  19 #define __PENTIUM_MSR_H__
  20
  21 #include <Register/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Pentium Processors?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x05 && \
  34    (                        \
  35     DisplayModel == 0x01 || \
  36     DisplayModel == 0x02 || \
  37     DisplayModel == 0x04    \
  38     )                       \
  39    )
  40
  41 /**
  42   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  43
  44   @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)
  45   @param  EAX  Lower 32-bits of MSR value.
  46   @param  EDX  Upper 32-bits of MSR value.
  47
  48   <b>Example usage</b>
  49   @code
  50   UINT64  Msr;
  51
  52   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
  53   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
  54   @endcode
  55   @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
  56 **/
  57 #define MSR_PENTIUM_P5_MC_ADDR                   0x00000000
  58
  59
  60 /**
  61   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  62
  63   @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x00000001)
  64   @param  EAX  Lower 32-bits of MSR value.
  65   @param  EDX  Upper 32-bits of MSR value.
  66
  67   <b>Example usage</b>
  68   @code
  69   UINT64  Msr;
  70
  71   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
  72   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
  73   @endcode
  74   @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
  75 **/
  76 #define MSR_PENTIUM_P5_MC_TYPE                   0x00000001
  77
  78
  79 /**
  80   See Section 17.17, "Time-Stamp Counter.".
  81
  82   @param  ECX  MSR_PENTIUM_TSC (0x00000010)
  83   @param  EAX  Lower 32-bits of MSR value.
  84   @param  EDX  Upper 32-bits of MSR value.
  85
  86   <b>Example usage</b>
  87   @code
  88   UINT64  Msr;
  89
  90   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
  91   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
  92   @endcode
  93   @note MSR_PENTIUM_TSC is defined as TSC in SDM.
  94 **/
  95 #define MSR_PENTIUM_TSC                          0x00000010
  96
  97
  98 /**
  99   See Section 18.6.9.1, "Control and Event Select Register (CESR).".
 100
 101   @param  ECX  MSR_PENTIUM_CESR (0x00000011)
 102   @param  EAX  Lower 32-bits of MSR value.
 103   @param  EDX  Upper 32-bits of MSR value.
 104
 105   <b>Example usage</b>
 106   @code
 107   UINT64  Msr;
 108
 109   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
 110   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
 111   @endcode
 112   @note MSR_PENTIUM_CESR is defined as CESR in SDM.
 113 **/
 114 #define MSR_PENTIUM_CESR                         0x00000011
 115
 116
 117 /**
 118   Section 18.6.9.3, "Events Counted.".
 119
 120   @param  ECX  MSR_PENTIUM_CTRn
 121   @param  EAX  Lower 32-bits of MSR value.
 122   @param  EDX  Upper 32-bits of MSR value.
 123
 124   <b>Example usage</b>
 125   @code
 126   UINT64  Msr;
 127
 128   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
 129   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
 130   @endcode
 131   @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
 132         MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
 133   @{
 134 **/
 135 #define MSR_PENTIUM_CTR0                         0x00000012
 136 #define MSR_PENTIUM_CTR1                         0x00000013
 137 /// @}
 138
 139 #endif