UefiCpuPkg/Include/Register/Msr/PentiumMsr.h

   1 /** @file
   2   MSR Definitions for Pentium Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  20   May 2018, Volume 4: Model-Specific-Registers (MSR)
  21
  22 **/
  23
  24 #ifndef __PENTIUM_MSR_H__
  25 #define __PENTIUM_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Is Pentium Processors?
  31
  32   @param   DisplayFamily  Display Family ID
  33   @param   DisplayModel   Display Model ID
  34
  35   @retval  TRUE   Yes, it is.
  36   @retval  FALSE  No, it isn't.
  37 **/
  38 #define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
  39   (DisplayFamily == 0x05 && \
  40    (                        \
  41     DisplayModel == 0x01 || \
  42     DisplayModel == 0x02 || \
  43     DisplayModel == 0x04    \
  44     )                       \
  45    )
  46
  47 /**
  48   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  49
  50   @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)
  51   @param  EAX  Lower 32-bits of MSR value.
  52   @param  EDX  Upper 32-bits of MSR value.
  53
  54   <b>Example usage</b>
  55   @code
  56   UINT64  Msr;
  57
  58   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
  59   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
  60   @endcode
  61   @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
  62 **/
  63 #define MSR_PENTIUM_P5_MC_ADDR                   0x00000000
  64
  65
  66 /**
  67   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  68
  69   @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x00000001)
  70   @param  EAX  Lower 32-bits of MSR value.
  71   @param  EDX  Upper 32-bits of MSR value.
  72
  73   <b>Example usage</b>
  74   @code
  75   UINT64  Msr;
  76
  77   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
  78   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
  79   @endcode
  80   @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
  81 **/
  82 #define MSR_PENTIUM_P5_MC_TYPE                   0x00000001
  83
  84
  85 /**
  86   See Section 17.17, "Time-Stamp Counter.".
  87
  88   @param  ECX  MSR_PENTIUM_TSC (0x00000010)
  89   @param  EAX  Lower 32-bits of MSR value.
  90   @param  EDX  Upper 32-bits of MSR value.
  91
  92   <b>Example usage</b>
  93   @code
  94   UINT64  Msr;
  95
  96   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
  97   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
  98   @endcode
  99   @note MSR_PENTIUM_TSC is defined as TSC in SDM.
 100 **/
 101 #define MSR_PENTIUM_TSC                          0x00000010
 102
 103
 104 /**
 105   See Section 18.6.9.1, "Control and Event Select Register (CESR).".
 106
 107   @param  ECX  MSR_PENTIUM_CESR (0x00000011)
 108   @param  EAX  Lower 32-bits of MSR value.
 109   @param  EDX  Upper 32-bits of MSR value.
 110
 111   <b>Example usage</b>
 112   @code
 113   UINT64  Msr;
 114
 115   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
 116   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
 117   @endcode
 118   @note MSR_PENTIUM_CESR is defined as CESR in SDM.
 119 **/
 120 #define MSR_PENTIUM_CESR                         0x00000011
 121
 122
 123 /**
 124   Section 18.6.9.3, "Events Counted.".
 125
 126   @param  ECX  MSR_PENTIUM_CTRn
 127   @param  EAX  Lower 32-bits of MSR value.
 128   @param  EDX  Upper 32-bits of MSR value.
 129
 130   <b>Example usage</b>
 131   @code
 132   UINT64  Msr;
 133
 134   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
 135   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
 136   @endcode
 137   @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
 138         MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
 139   @{
 140 **/
 141 #define MSR_PENTIUM_CTR0                         0x00000012
 142 #define MSR_PENTIUM_CTR1                         0x00000013
 143 /// @}
 144
 145 #endif