2 MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __SKYLAKE_MSR_H__
19 #define __SKYLAKE_MSR_H__
21 #include <Register/ArchitecturalMsr.h>
24 Is Intel processors based on the Skylake microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x4E || \
36 DisplayModel == 0x5E || \
37 DisplayModel == 0x55 || \
38 DisplayModel == 0x8E || \
39 DisplayModel == 0x9E || \
40 DisplayModel == 0x66 \
45 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
46 RW if MSR_PLATFORM_INFO.[28] = 1.
48 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
49 @param EAX Lower 32-bits of MSR value.
50 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
51 @param EDX Upper 32-bits of MSR value.
52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
56 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;
58 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
60 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
62 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD
65 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
69 /// Individual bit fields
73 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
74 /// limit of 1 core active.
78 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
79 /// limit of 2 core active.
83 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
84 /// limit of 3 core active.
88 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
89 /// limit of 4 core active.
95 /// All bit fields as a 32-bit value
99 /// All bit fields as a 64-bit value
102 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
;
106 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)
107 that points to the MSR containing the most recent branch record.
109 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
110 @param EAX Lower 32-bits of MSR value.
111 @param EDX Upper 32-bits of MSR value.
117 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
118 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
120 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
122 #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9
126 Core. Power Control Register See http://biosbits.org.
128 @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)
129 @param EAX Lower 32-bits of MSR value.
130 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
131 @param EDX Upper 32-bits of MSR value.
132 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
136 MSR_SKYLAKE_POWER_CTL_REGISTER Msr;
138 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
139 AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
142 #define MSR_SKYLAKE_POWER_CTL 0x000001FC
145 MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
149 /// Individual bit fields
154 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
155 /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
156 /// point when all execution cores enter MWAIT (C1).
161 /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
162 /// disables the Race to Halt optimization and avoids this optimization
163 /// limitation to execute below the most efficient frequency ratio.
164 /// Default value is 0 for processors that support Race to Halt
165 /// optimization. Default value is 1 for processors that do not support
166 /// Race to Halt optimization.
170 /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
171 /// disables the P-States energy efficiency optimization. Default value is
172 /// 0. Disable/enable the energy efficiency optimization in P-State legacy
173 /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
174 /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
175 /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
176 /// desired or OS maximize to the OS minimize performance setting.
178 UINT32 DisableEnergyEfficiencyOptimization
:1;
183 /// All bit fields as a 32-bit value
187 /// All bit fields as a 64-bit value
190 } MSR_SKYLAKE_POWER_CTL_REGISTER
;
194 Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
195 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
196 the package. Lower 64 bits of an 128-bit external entropy value for key
197 derivation of an enclave.
199 @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)
200 @param EAX Lower 32-bits of MSR value.
201 @param EDX Upper 32-bits of MSR value.
208 AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);
210 @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.
212 #define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300
215 // Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.
217 #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0
219 Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
220 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
221 the package. Upper 64 bits of an 128-bit external entropy value for key
222 derivation of an enclave.
224 @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)
225 @param EAX Lower 32-bits of MSR value.
226 @param EDX Upper 32-bits of MSR value.
233 AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);
235 @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.
237 #define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301
240 // Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.
242 #define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1
246 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
249 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
250 @param EAX Lower 32-bits of MSR value.
251 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
252 @param EDX Upper 32-bits of MSR value.
253 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
257 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
259 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);
260 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
262 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
264 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E
267 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS
271 /// Individual bit fields
275 /// [Bit 0] Thread. Ovf_PMC0.
279 /// [Bit 1] Thread. Ovf_PMC1.
283 /// [Bit 2] Thread. Ovf_PMC2.
287 /// [Bit 3] Thread. Ovf_PMC3.
291 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
295 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
299 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
303 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
308 /// [Bit 32] Thread. Ovf_FixedCtr0.
310 UINT32 Ovf_FixedCtr0
:1;
312 /// [Bit 33] Thread. Ovf_FixedCtr1.
314 UINT32 Ovf_FixedCtr1
:1;
316 /// [Bit 34] Thread. Ovf_FixedCtr2.
318 UINT32 Ovf_FixedCtr2
:1;
321 /// [Bit 55] Thread. Trace_ToPA_PMI.
323 UINT32 Trace_ToPA_PMI
:1;
326 /// [Bit 58] Thread. LBR_Frz.
330 /// [Bit 59] Thread. CTR_Frz.
334 /// [Bit 60] Thread. ASCI.
338 /// [Bit 61] Thread. Ovf_Uncore.
342 /// [Bit 62] Thread. Ovf_BufDSSAVE.
344 UINT32 Ovf_BufDSSAVE
:1;
346 /// [Bit 63] Thread. CondChgd.
351 /// All bit fields as a 64-bit value
354 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
358 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
361 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
362 @param EAX Lower 32-bits of MSR value.
363 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
364 @param EDX Upper 32-bits of MSR value.
365 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
369 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
371 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
372 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
374 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
376 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
379 MSR information returned for MSR index
380 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
384 /// Individual bit fields
388 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
392 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
396 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
400 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
404 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
408 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
412 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
416 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
421 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
423 UINT32 Ovf_FixedCtr0
:1;
425 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
427 UINT32 Ovf_FixedCtr1
:1;
429 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
431 UINT32 Ovf_FixedCtr2
:1;
434 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
436 UINT32 Trace_ToPA_PMI
:1;
439 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
443 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
447 /// [Bit 60] Thread. Set 1 to clear ASCI.
451 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
455 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
457 UINT32 Ovf_BufDSSAVE
:1;
459 /// [Bit 63] Thread. Set 1 to clear CondChgd.
464 /// All bit fields as a 64-bit value
467 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
471 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
474 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
475 @param EAX Lower 32-bits of MSR value.
476 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
477 @param EDX Upper 32-bits of MSR value.
478 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
482 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
484 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
485 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
487 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
489 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
492 MSR information returned for MSR index
493 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
497 /// Individual bit fields
501 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
505 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
509 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
513 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
517 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
521 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
525 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
529 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
534 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
536 UINT32 Ovf_FixedCtr0
:1;
538 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
540 UINT32 Ovf_FixedCtr1
:1;
542 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
544 UINT32 Ovf_FixedCtr2
:1;
547 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
549 UINT32 Trace_ToPA_PMI
:1;
552 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
556 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
560 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
564 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
568 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
570 UINT32 Ovf_BufDSSAVE
:1;
574 /// All bit fields as a 64-bit value
577 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
581 Thread. FrontEnd Precise Event Condition Select (R/W).
583 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
584 @param EAX Lower 32-bits of MSR value.
585 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
586 @param EDX Upper 32-bits of MSR value.
587 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
591 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;
593 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
594 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
596 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
598 #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7
601 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
605 /// Individual bit fields
609 /// [Bits 2:0] Event Code Select.
611 UINT32 EventCodeSelect
:3;
614 /// [Bit 4] Event Code Select High.
616 UINT32 EventCodeSelectHigh
:1;
619 /// [Bits 19:8] IDQ_Bubble_Length Specifier.
621 UINT32 IDQ_Bubble_Length
:12;
623 /// [Bits 22:20] IDQ_Bubble_Width Specifier.
625 UINT32 IDQ_Bubble_Width
:3;
630 /// All bit fields as a 32-bit value
634 /// All bit fields as a 64-bit value
637 } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
;
641 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
644 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
645 @param EAX Lower 32-bits of MSR value.
646 @param EDX Upper 32-bits of MSR value.
652 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
654 @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
656 #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
660 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
661 platform vendor hardware implementation and BIOS enablement support it. This
662 MSR will read 0 if not valid.
664 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
665 @param EAX Lower 32-bits of MSR value.
666 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
667 @param EDX Upper 32-bits of MSR value.
668 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
672 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;
674 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
676 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
678 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D
681 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
685 /// Individual bit fields
689 /// [Bits 31:0] Total energy consumed by all devices in the platform that
690 /// receive power from integrated power delivery mechanism, Included
691 /// platform devices are processor cores, SOC, memory, add-on or
692 /// peripheral devices that get powered directly from the platform power
693 /// delivery means. The energy units are specified in the
694 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
696 UINT32 TotalEnergy
:32;
700 /// All bit fields as a 32-bit value
704 /// All bit fields as a 64-bit value
707 } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
;
711 Thread. Productive Performance Count. (R/O). Hardware's view of workload
712 scalability. See Section 14.4.5.1.
714 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)
715 @param EAX Lower 32-bits of MSR value.
716 @param EDX Upper 32-bits of MSR value.
722 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
724 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
726 #define MSR_SKYLAKE_PPERF 0x0000064E
730 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
731 refers to processor core frequency).
733 @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)
734 @param EAX Lower 32-bits of MSR value.
735 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
736 @param EDX Upper 32-bits of MSR value.
737 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
741 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
743 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);
744 AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
746 @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
748 #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F
751 MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS
755 /// Individual bit fields
759 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
760 /// operating system request due to assertion of external PROCHOT.
762 UINT32 PROCHOT_Status
:1;
764 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
765 /// operating system request due to a thermal event.
767 UINT32 ThermalStatus
:1;
770 /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is
771 /// reduced below the operating system request due to residency state
772 /// regulation limit.
774 UINT32 ResidencyStateRegulationStatus
:1;
776 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
777 /// is reduced below the operating system request due to Running Average
778 /// Thermal Limit (RATL).
780 UINT32 RunningAverageThermalLimitStatus
:1;
782 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
783 /// below the operating system request due to a thermal alert from a
784 /// processor Voltage Regulator (VR).
786 UINT32 VRThermAlertStatus
:1;
788 /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is
789 /// reduced below the operating system request due to VR thermal design
792 UINT32 VRThermDesignCurrentStatus
:1;
794 /// [Bit 8] Other Status (R0) When set, frequency is reduced below the
795 /// operating system request due to electrical or other constraints.
797 UINT32 OtherStatus
:1;
800 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
801 /// set, frequency is reduced below the operating system request due to
802 /// package/platform-level power limiting PL1.
806 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
807 /// set, frequency is reduced below the operating system request due to
808 /// package/platform-level power limiting PL2/PL3.
812 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
813 /// below the operating system request due to multi-core turbo limits.
815 UINT32 MaxTurboLimitStatus
:1;
817 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
818 /// is reduced below the operating system request due to Turbo transition
819 /// attenuation. This prevents performance degradation due to frequent
820 /// operating ratio changes.
822 UINT32 TurboTransitionAttenuationStatus
:1;
825 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
826 /// has asserted since the log bit was last cleared. This log bit will
827 /// remain set until cleared by software writing 0.
829 UINT32 PROCHOT_Log
:1;
831 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
832 /// has asserted since the log bit was last cleared. This log bit will
833 /// remain set until cleared by software writing 0.
838 /// [Bit 20] Residency State Regulation Log When set, indicates that the
839 /// Residency State Regulation Status bit has asserted since the log bit
840 /// was last cleared. This log bit will remain set until cleared by
841 /// software writing 0.
843 UINT32 ResidencyStateRegulationLog
:1;
845 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
846 /// the RATL Status bit has asserted since the log bit was last cleared.
847 /// This log bit will remain set until cleared by software writing 0.
849 UINT32 RunningAverageThermalLimitLog
:1;
851 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
852 /// Alert Status bit has asserted since the log bit was last cleared. This
853 /// log bit will remain set until cleared by software writing 0.
855 UINT32 VRThermAlertLog
:1;
857 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
858 /// VR TDC Status bit has asserted since the log bit was last cleared.
859 /// This log bit will remain set until cleared by software writing 0.
861 UINT32 VRThermalDesignCurrentLog
:1;
863 /// [Bit 24] Other Log When set, indicates that the Other Status bit has
864 /// asserted since the log bit was last cleared. This log bit will remain
865 /// set until cleared by software writing 0.
870 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
871 /// indicates that the Package or Platform Level PL1 Power Limiting Status
872 /// bit has asserted since the log bit was last cleared. This log bit will
873 /// remain set until cleared by software writing 0.
877 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
878 /// indicates that the Package or Platform Level PL2/PL3 Power Limiting
879 /// Status bit has asserted since the log bit was last cleared. This log
880 /// bit will remain set until cleared by software writing 0.
884 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
885 /// Limit Status bit has asserted since the log bit was last cleared. This
886 /// log bit will remain set until cleared by software writing 0.
888 UINT32 MaxTurboLimitLog
:1;
890 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
891 /// Turbo Transition Attenuation Status bit has asserted since the log bit
892 /// was last cleared. This log bit will remain set until cleared by
893 /// software writing 0.
895 UINT32 TurboTransitionAttenuationLog
:1;
900 /// All bit fields as a 32-bit value
904 /// All bit fields as a 64-bit value
907 } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
;
911 Package. HDC Configuration (R/W)..
913 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
914 @param EAX Lower 32-bits of MSR value.
915 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
916 @param EDX Upper 32-bits of MSR value.
917 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
921 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;
923 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
924 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
926 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
928 #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652
931 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
935 /// Individual bit fields
939 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for
940 /// MSR_PKG_HDC_DEEP_RESIDENCY.
942 UINT32 PKG_Cx_Monitor
:3;
947 /// All bit fields as a 32-bit value
951 /// All bit fields as a 64-bit value
954 } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
;
958 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
960 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
961 @param EAX Lower 32-bits of MSR value.
962 @param EDX Upper 32-bits of MSR value.
968 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
970 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
972 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653
976 Package. Accumulate the cycles the package was in C2 state and at least one
977 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
979 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
980 @param EAX Lower 32-bits of MSR value.
981 @param EDX Upper 32-bits of MSR value.
987 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
989 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
991 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655
995 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
997 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
998 @param EAX Lower 32-bits of MSR value.
999 @param EDX Upper 32-bits of MSR value.
1001 <b>Example usage</b>
1005 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
1007 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
1009 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656
1013 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
1014 as the TSC. The increment each cycle is weighted by the number of processor
1015 cores in the package that reside in C0. If N cores are simultaneously in C0,
1016 then each cycle the counter increments by N.
1018 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
1019 @param EAX Lower 32-bits of MSR value.
1020 @param EDX Upper 32-bits of MSR value.
1022 <b>Example usage</b>
1026 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
1028 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
1030 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658
1034 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
1035 TSC. The increment each cycle is one if any processor core in the package is
1038 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
1039 @param EAX Lower 32-bits of MSR value.
1040 @param EDX Upper 32-bits of MSR value.
1042 <b>Example usage</b>
1046 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
1048 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
1050 #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659
1054 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
1055 as the TSC. The increment each cycle is one if any processor graphic
1056 device's compute engines are in C0.
1058 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
1059 @param EAX Lower 32-bits of MSR value.
1060 @param EDX Upper 32-bits of MSR value.
1062 <b>Example usage</b>
1066 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
1068 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
1070 #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A
1074 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
1075 at the same rate as the TSC. The increment each cycle is one if at least one
1076 compute engine of the processor graphics is in C0 and at least one processor
1077 core in the package is also in C0.
1079 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
1080 @param EAX Lower 32-bits of MSR value.
1081 @param EDX Upper 32-bits of MSR value.
1083 <b>Example usage</b>
1087 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
1089 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
1091 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B
1095 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
1096 limit power consumption of the platform devices to the specified values. The
1097 Long Duration power consumption is specified via Platform_Power_Limit_1 and
1098 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
1099 specified via the Platform_Power_Limit_2 with duration chosen by the
1100 processor. The processor implements an exponential-weighted algorithm in the
1101 placement of the time windows.
1103 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
1104 @param EAX Lower 32-bits of MSR value.
1105 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
1106 @param EDX Upper 32-bits of MSR value.
1107 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
1109 <b>Example usage</b>
1111 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;
1113 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
1114 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
1116 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
1118 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C
1121 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
1125 /// Individual bit fields
1129 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
1130 /// the platform must not exceed over a time window as specified by
1131 /// Power_Limit_1_TIME field. The default value is the Thermal Design
1132 /// Power (TDP) and varies with product skus. The unit is specified in
1133 /// MSR_RAPLPOWER_UNIT.
1135 UINT32 PlatformPowerLimit1
:15;
1137 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
1138 /// processor to apply control policy such that the platform power does
1139 /// not exceed Platform Power limit #1 over the time window specified by
1140 /// Power Limit #1 Time Window.
1142 UINT32 EnablePlatformPowerLimit1
:1;
1144 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
1145 /// processor to go below the OS requested P states in order to maintain
1146 /// the power below specified Platform Power Limit #1 value. This bit is
1147 /// writeable only when CPUID (EAX=6):EAX[4] is set.
1149 UINT32 PlatformClampingLimitation1
:1;
1151 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
1152 /// duration of the time window over which Platform Power Limit 1 value
1153 /// should be maintained for sustained long duration. This field is made
1154 /// up of two numbers from the following equation: Time Window = (float)
1155 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
1156 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
1157 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
1158 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
1163 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
1164 /// the platform must not exceed over the Short Duration time window
1165 /// chosen by the processor. The recommended default value is 1.25 times
1166 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
1168 UINT32 PlatformPowerLimit2
:15;
1170 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
1171 /// processor to apply control policy such that the platform power does
1172 /// not exceed Platform Power limit #2 over the Short Duration time window.
1174 UINT32 EnablePlatformPowerLimit2
:1;
1176 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
1177 /// processor to go below the OS requested P states in order to maintain
1178 /// the power below specified Platform Power Limit #2 value.
1180 UINT32 PlatformClampingLimitation2
:1;
1181 UINT32 Reserved2
:14;
1183 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
1184 /// until system RESET.
1189 /// All bit fields as a 64-bit value
1192 } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
;
1196 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
1197 branch record registers on the last branch record stack. This part of the
1198 stack contains pointers to the source instruction. See also: - Last Branch
1199 Record Stack TOS at 1C9H - Section 17.10.
1201 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
1202 @param EAX Lower 32-bits of MSR value.
1203 @param EDX Upper 32-bits of MSR value.
1205 <b>Example usage</b>
1209 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
1210 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
1212 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
1213 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
1214 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
1215 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
1216 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
1217 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
1218 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
1219 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
1220 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
1221 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
1222 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
1223 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
1224 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
1225 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
1226 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
1227 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
1230 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690
1231 #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691
1232 #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692
1233 #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693
1234 #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694
1235 #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695
1236 #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696
1237 #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697
1238 #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698
1239 #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699
1240 #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A
1241 #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B
1242 #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C
1243 #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D
1244 #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E
1245 #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
1250 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1251 (frequency refers to processor graphics frequency).
1253 @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1254 @param EAX Lower 32-bits of MSR value.
1255 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1256 @param EDX Upper 32-bits of MSR value.
1257 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1259 <b>Example usage</b>
1261 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1263 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);
1264 AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1266 @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1268 #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1271 MSR information returned for MSR index
1272 #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS
1276 /// Individual bit fields
1280 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
1281 /// assertion of external PROCHOT.
1283 UINT32 PROCHOT_Status
:1;
1285 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
1288 UINT32 ThermalStatus
:1;
1291 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
1292 /// is reduced due to running average thermal limit.
1294 UINT32 RunningAverageThermalLimitStatus
:1;
1296 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
1297 /// to a thermal alert from a processor Voltage Regulator.
1299 UINT32 VRThermAlertStatus
:1;
1301 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
1302 /// reduced due to VR TDC limit.
1304 UINT32 VRThermalDesignCurrentStatus
:1;
1306 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
1307 /// electrical or other constraints.
1309 UINT32 OtherStatus
:1;
1312 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
1313 /// set, frequency is reduced due to package/platform-level power limiting
1318 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
1319 /// set, frequency is reduced due to package/platform-level power limiting
1324 /// [Bit 12] Inefficient Operation Status (R0) When set, processor
1325 /// graphics frequency is operating below target frequency.
1327 UINT32 InefficientOperationStatus
:1;
1330 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1331 /// has asserted since the log bit was last cleared. This log bit will
1332 /// remain set until cleared by software writing 0.
1334 UINT32 PROCHOT_Log
:1;
1336 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1337 /// has asserted since the log bit was last cleared. This log bit will
1338 /// remain set until cleared by software writing 0.
1340 UINT32 ThermalLog
:1;
1343 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
1344 /// the RATL Status bit has asserted since the log bit was last cleared.
1345 /// This log bit will remain set until cleared by software writing 0.
1347 UINT32 RunningAverageThermalLimitLog
:1;
1349 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1350 /// Alert Status bit has asserted since the log bit was last cleared. This
1351 /// log bit will remain set until cleared by software writing 0.
1353 UINT32 VRThermAlertLog
:1;
1355 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
1356 /// VR Therm Alert Status bit has asserted since the log bit was last
1357 /// cleared. This log bit will remain set until cleared by software
1360 UINT32 VRThermalDesignCurrentLog
:1;
1362 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
1363 /// asserted since the log bit was last cleared. This log bit will remain
1364 /// set until cleared by software writing 0.
1369 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
1370 /// indicates that the Package/Platform Level PL1 Power Limiting Status
1371 /// bit has asserted since the log bit was last cleared. This log bit will
1372 /// remain set until cleared by software writing 0.
1376 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
1377 /// indicates that the Package/Platform Level PL2 Power Limiting Status
1378 /// bit has asserted since the log bit was last cleared. This log bit will
1379 /// remain set until cleared by software writing 0.
1383 /// [Bit 28] Inefficient Operation Log When set, indicates that the
1384 /// Inefficient Operation Status bit has asserted since the log bit was
1385 /// last cleared. This log bit will remain set until cleared by software
1388 UINT32 InefficientOperationLog
:1;
1390 UINT32 Reserved7
:32;
1393 /// All bit fields as a 32-bit value
1397 /// All bit fields as a 64-bit value
1400 } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
1404 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
1405 (frequency refers to ring interconnect in the uncore).
1407 @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)
1408 @param EAX Lower 32-bits of MSR value.
1409 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
1410 @param EDX Upper 32-bits of MSR value.
1411 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
1413 <b>Example usage</b>
1415 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;
1417 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);
1418 AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);
1420 @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
1422 #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1
1425 MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS
1429 /// Individual bit fields
1433 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
1434 /// assertion of external PROCHOT.
1436 UINT32 PROCHOT_Status
:1;
1438 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
1441 UINT32 ThermalStatus
:1;
1444 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
1445 /// is reduced due to running average thermal limit.
1447 UINT32 RunningAverageThermalLimitStatus
:1;
1449 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
1450 /// to a thermal alert from a processor Voltage Regulator.
1452 UINT32 VRThermAlertStatus
:1;
1454 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
1455 /// reduced due to VR TDC limit.
1457 UINT32 VRThermalDesignCurrentStatus
:1;
1459 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
1460 /// electrical or other constraints.
1462 UINT32 OtherStatus
:1;
1465 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
1466 /// set, frequency is reduced due to package/Platform-level power limiting
1471 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
1472 /// set, frequency is reduced due to package/Platform-level power limiting
1478 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1479 /// has asserted since the log bit was last cleared. This log bit will
1480 /// remain set until cleared by software writing 0.
1482 UINT32 PROCHOT_Log
:1;
1484 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1485 /// has asserted since the log bit was last cleared. This log bit will
1486 /// remain set until cleared by software writing 0.
1488 UINT32 ThermalLog
:1;
1491 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
1492 /// the RATL Status bit has asserted since the log bit was last cleared.
1493 /// This log bit will remain set until cleared by software writing 0.
1495 UINT32 RunningAverageThermalLimitLog
:1;
1497 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1498 /// Alert Status bit has asserted since the log bit was last cleared. This
1499 /// log bit will remain set until cleared by software writing 0.
1501 UINT32 VRThermAlertLog
:1;
1503 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
1504 /// VR Therm Alert Status bit has asserted since the log bit was last
1505 /// cleared. This log bit will remain set until cleared by software
1508 UINT32 VRThermalDesignCurrentLog
:1;
1510 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
1511 /// asserted since the log bit was last cleared. This log bit will remain
1512 /// set until cleared by software writing 0.
1517 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
1518 /// indicates that the Package/Platform Level PL1 Power Limiting Status
1519 /// bit has asserted since the log bit was last cleared. This log bit will
1520 /// remain set until cleared by software writing 0.
1524 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
1525 /// indicates that the Package/Platform Level PL2 Power Limiting Status
1526 /// bit has asserted since the log bit was last cleared. This log bit will
1527 /// remain set until cleared by software writing 0.
1531 UINT32 Reserved7
:32;
1534 /// All bit fields as a 32-bit value
1538 /// All bit fields as a 64-bit value
1541 } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
;
1545 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
1546 record registers on the last branch record stack. This part of the stack
1547 contains pointers to the destination instruction. See also: - Last Branch
1548 Record Stack TOS at 1C9H - Section 17.10.
1550 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
1551 @param EAX Lower 32-bits of MSR value.
1552 @param EDX Upper 32-bits of MSR value.
1554 <b>Example usage</b>
1558 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
1559 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
1561 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
1562 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
1563 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
1564 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
1565 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
1566 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
1567 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
1568 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
1569 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
1570 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
1571 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
1572 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
1573 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
1574 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
1575 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
1576 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
1579 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0
1580 #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1
1581 #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2
1582 #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3
1583 #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4
1584 #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5
1585 #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6
1586 #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7
1587 #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8
1588 #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9
1589 #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA
1590 #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB
1591 #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC
1592 #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD
1593 #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE
1594 #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF
1599 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
1600 of last branch record registers on the last branch record stack. This part
1601 of the stack contains flag, TSX-related and elapsed cycle information. See
1602 also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR
1605 @param ECX MSR_SKYLAKE_LBR_INFO_n
1606 @param EAX Lower 32-bits of MSR value.
1607 @param EDX Upper 32-bits of MSR value.
1609 <b>Example usage</b>
1613 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
1614 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
1616 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.
1617 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.
1618 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.
1619 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.
1620 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.
1621 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.
1622 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.
1623 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.
1624 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.
1625 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.
1626 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
1627 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
1628 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
1629 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
1630 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
1631 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
1632 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
1633 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
1634 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
1635 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
1636 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
1637 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
1638 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
1639 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
1640 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
1641 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
1642 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
1643 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
1644 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
1645 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
1646 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
1647 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
1650 #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0
1651 #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1
1652 #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2
1653 #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3
1654 #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4
1655 #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5
1656 #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6
1657 #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7
1658 #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8
1659 #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9
1660 #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA
1661 #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB
1662 #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC
1663 #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD
1664 #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE
1665 #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF
1666 #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0
1667 #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1
1668 #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2
1669 #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3
1670 #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4
1671 #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5
1672 #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6
1673 #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7
1674 #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8
1675 #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9
1676 #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA
1677 #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB
1678 #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC
1679 #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD
1680 #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE
1681 #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF
1686 Package. Uncore fixed counter control (R/W).
1688 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)
1689 @param EAX Lower 32-bits of MSR value.
1690 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
1691 @param EDX Upper 32-bits of MSR value.
1692 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
1694 <b>Example usage</b>
1696 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1698 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);
1699 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1701 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1703 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394
1706 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL
1710 /// Individual bit fields
1713 UINT32 Reserved1
:20;
1715 /// [Bit 20] Enable overflow propagation.
1717 UINT32 EnableOverflow
:1;
1720 /// [Bit 22] Enable counting.
1722 UINT32 EnableCounting
:1;
1724 UINT32 Reserved4
:32;
1727 /// All bit fields as a 32-bit value
1731 /// All bit fields as a 64-bit value
1734 } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
;
1738 Package. Uncore fixed counter.
1740 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)
1741 @param EAX Lower 32-bits of MSR value.
1742 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
1743 @param EDX Upper 32-bits of MSR value.
1744 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
1746 <b>Example usage</b>
1748 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;
1750 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);
1751 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);
1753 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1755 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395
1758 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR
1762 /// Individual bit fields
1766 /// [Bits 31:0] Current count.
1768 UINT32 CurrentCount
:32;
1770 /// [Bits 43:32] Current count.
1772 UINT32 CurrentCountHi
:12;
1776 /// All bit fields as a 64-bit value
1779 } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
;
1783 Package. Uncore C-Box configuration information (R/O).
1785 @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)
1786 @param EAX Lower 32-bits of MSR value.
1787 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
1788 @param EDX Upper 32-bits of MSR value.
1789 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
1791 <b>Example usage</b>
1793 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;
1795 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);
1797 @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1799 #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396
1802 MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG
1806 /// Individual bit fields
1810 /// [Bits 3:0] Specifies the number of C-Box units with programmable
1811 /// counters (including processor cores and processor graphics),.
1814 UINT32 Reserved1
:28;
1815 UINT32 Reserved2
:32;
1818 /// All bit fields as a 32-bit value
1822 /// All bit fields as a 64-bit value
1825 } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER
;
1829 Package. Uncore Arb unit, performance counter 0.
1831 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)
1832 @param EAX Lower 32-bits of MSR value.
1833 @param EDX Upper 32-bits of MSR value.
1835 <b>Example usage</b>
1839 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);
1840 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);
1842 @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1844 #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0
1848 Package. Uncore Arb unit, performance counter 1.
1850 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)
1851 @param EAX Lower 32-bits of MSR value.
1852 @param EDX Upper 32-bits of MSR value.
1854 <b>Example usage</b>
1858 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);
1859 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);
1861 @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1863 #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1
1867 Package. Uncore Arb unit, counter 0 event select MSR.
1869 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1870 @param EAX Lower 32-bits of MSR value.
1871 @param EDX Upper 32-bits of MSR value.
1873 <b>Example usage</b>
1877 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);
1878 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);
1880 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1882 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2
1886 Package. Uncore Arb unit, counter 1 event select MSR.
1888 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1889 @param EAX Lower 32-bits of MSR value.
1890 @param EDX Upper 32-bits of MSR value.
1892 <b>Example usage</b>
1896 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);
1897 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);
1899 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.
1901 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3
1905 Package. Uncore C-Box 0, counter 0 event select MSR.
1907 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
1908 @param EAX Lower 32-bits of MSR value.
1909 @param EDX Upper 32-bits of MSR value.
1911 <b>Example usage</b>
1915 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);
1916 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);
1918 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
1920 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700
1924 Package. Uncore C-Box 0, counter 1 event select MSR.
1926 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
1927 @param EAX Lower 32-bits of MSR value.
1928 @param EDX Upper 32-bits of MSR value.
1930 <b>Example usage</b>
1934 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);
1935 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);
1937 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
1939 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701
1943 Package. Uncore C-Box 0, performance counter 0.
1945 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)
1946 @param EAX Lower 32-bits of MSR value.
1947 @param EDX Upper 32-bits of MSR value.
1949 <b>Example usage</b>
1953 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);
1954 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);
1956 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
1958 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706
1962 Package. Uncore C-Box 0, performance counter 1.
1964 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)
1965 @param EAX Lower 32-bits of MSR value.
1966 @param EDX Upper 32-bits of MSR value.
1968 <b>Example usage</b>
1972 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);
1973 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);
1975 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
1977 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707
1981 Package. Uncore C-Box 1, counter 0 event select MSR.
1983 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
1984 @param EAX Lower 32-bits of MSR value.
1985 @param EDX Upper 32-bits of MSR value.
1987 <b>Example usage</b>
1991 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);
1992 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);
1994 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
1996 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2000 Package. Uncore C-Box 1, counter 1 event select MSR.
2002 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2003 @param EAX Lower 32-bits of MSR value.
2004 @param EDX Upper 32-bits of MSR value.
2006 <b>Example usage</b>
2010 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);
2011 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);
2013 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2015 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2019 Package. Uncore C-Box 1, performance counter 0.
2021 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)
2022 @param EAX Lower 32-bits of MSR value.
2023 @param EDX Upper 32-bits of MSR value.
2025 <b>Example usage</b>
2029 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);
2030 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);
2032 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2034 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716
2038 Package. Uncore C-Box 1, performance counter 1.
2040 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)
2041 @param EAX Lower 32-bits of MSR value.
2042 @param EDX Upper 32-bits of MSR value.
2044 <b>Example usage</b>
2048 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);
2049 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);
2051 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2053 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717
2057 Package. Uncore C-Box 2, counter 0 event select MSR.
2059 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2060 @param EAX Lower 32-bits of MSR value.
2061 @param EDX Upper 32-bits of MSR value.
2063 <b>Example usage</b>
2067 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);
2068 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);
2070 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2072 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2076 Package. Uncore C-Box 2, counter 1 event select MSR.
2078 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2079 @param EAX Lower 32-bits of MSR value.
2080 @param EDX Upper 32-bits of MSR value.
2082 <b>Example usage</b>
2086 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);
2087 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);
2089 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2091 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2095 Package. Uncore C-Box 2, performance counter 0.
2097 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)
2098 @param EAX Lower 32-bits of MSR value.
2099 @param EDX Upper 32-bits of MSR value.
2101 <b>Example usage</b>
2105 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);
2106 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);
2108 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2110 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726
2114 Package. Uncore C-Box 2, performance counter 1.
2116 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)
2117 @param EAX Lower 32-bits of MSR value.
2118 @param EDX Upper 32-bits of MSR value.
2120 <b>Example usage</b>
2124 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);
2125 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);
2127 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2129 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727
2133 Package. Uncore C-Box 3, counter 0 event select MSR.
2135 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2136 @param EAX Lower 32-bits of MSR value.
2137 @param EDX Upper 32-bits of MSR value.
2139 <b>Example usage</b>
2143 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);
2144 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);
2146 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2148 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2152 Package. Uncore C-Box 3, counter 1 event select MSR.
2154 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2155 @param EAX Lower 32-bits of MSR value.
2156 @param EDX Upper 32-bits of MSR value.
2158 <b>Example usage</b>
2162 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);
2163 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);
2165 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2167 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2171 Package. Uncore C-Box 3, performance counter 0.
2173 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)
2174 @param EAX Lower 32-bits of MSR value.
2175 @param EDX Upper 32-bits of MSR value.
2177 <b>Example usage</b>
2181 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);
2182 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);
2184 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2186 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736
2190 Package. Uncore C-Box 3, performance counter 1.
2192 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)
2193 @param EAX Lower 32-bits of MSR value.
2194 @param EDX Upper 32-bits of MSR value.
2196 <b>Example usage</b>
2200 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);
2201 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);
2203 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2205 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737
2209 Package. Uncore PMU global control.
2211 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)
2212 @param EAX Lower 32-bits of MSR value.
2213 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
2214 @param EDX Upper 32-bits of MSR value.
2215 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
2217 <b>Example usage</b>
2219 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
2221 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);
2222 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
2224 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
2226 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01
2229 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL
2233 /// Individual bit fields
2237 /// [Bit 0] Slice 0 select.
2239 UINT32 PMI_Sel_Slice0
:1;
2241 /// [Bit 1] Slice 1 select.
2243 UINT32 PMI_Sel_Slice1
:1;
2245 /// [Bit 2] Slice 2 select.
2247 UINT32 PMI_Sel_Slice2
:1;
2249 /// [Bit 3] Slice 3 select.
2251 UINT32 PMI_Sel_Slice3
:1;
2253 /// [Bit 4] Slice 4select.
2255 UINT32 PMI_Sel_Slice4
:1;
2256 UINT32 Reserved1
:14;
2257 UINT32 Reserved2
:10;
2259 /// [Bit 29] Enable all uncore counters.
2263 /// [Bit 30] Enable wake on PMI.
2267 /// [Bit 31] Enable Freezing counter when overflow.
2270 UINT32 Reserved3
:32;
2273 /// All bit fields as a 32-bit value
2277 /// All bit fields as a 64-bit value
2280 } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2284 Package. Uncore PMU main status.
2286 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)
2287 @param EAX Lower 32-bits of MSR value.
2288 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2289 @param EDX Upper 32-bits of MSR value.
2290 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2292 <b>Example usage</b>
2294 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2296 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);
2297 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2299 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2301 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02
2304 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS
2308 /// Individual bit fields
2312 /// [Bit 0] Fixed counter overflowed.
2316 /// [Bit 1] An ARB counter overflowed.
2321 /// [Bit 3] A CBox counter overflowed (on any slice).
2324 UINT32 Reserved2
:28;
2325 UINT32 Reserved3
:32;
2328 /// All bit fields as a 32-bit value
2332 /// All bit fields as a 64-bit value
2335 } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2339 Package. NPK Address Used by AET Messages (R/W).
2341 @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)
2342 @param EAX Lower 32-bits of MSR value.
2343 Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
2344 @param EDX Upper 32-bits of MSR value.
2345 Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
2347 <b>Example usage</b>
2349 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;
2351 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
2352 AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
2355 #define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080
2358 MSR information returned for MSR index
2359 #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
2363 /// Individual bit fields
2367 /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
2368 /// bit has to be set in order for the AET packets to be directed to NPK
2374 /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
2376 UINT32 ACPIBAR_BASE_ADDRESS
:14;
2378 /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
2383 /// All bit fields as a 64-bit value
2386 } MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
;
2390 Core. Processor Reserved Memory Range Register - Physical Base Control
2393 @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)
2394 @param EAX Lower 32-bits of MSR value.
2395 Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
2396 @param EDX Upper 32-bits of MSR value.
2397 Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
2399 <b>Example usage</b>
2401 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;
2403 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);
2404 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);
2407 #define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4
2410 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE
2414 /// Individual bit fields
2418 /// [Bits 2:0] MemType PRMRR BASE MemType.
2420 UINT32 MemTypePRMRRBASEMemType
:3;
2423 /// [Bits 31:12] Base PRMRR Base Address.
2425 UINT32 BasePRMRRBaseAddress
:20;
2427 /// [Bits 45:32] Base PRMRR Base Address.
2430 UINT32 Reserved2
:18;
2433 /// All bit fields as a 64-bit value
2436 } MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
;
2440 Core. Processor Reserved Memory Range Register - Physical Mask Control
2443 @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)
2444 @param EAX Lower 32-bits of MSR value.
2445 Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
2446 @param EDX Upper 32-bits of MSR value.
2447 Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
2449 <b>Example usage</b>
2451 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;
2453 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);
2454 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);
2457 #define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5
2460 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK
2464 /// Individual bit fields
2467 UINT32 Reserved1
:10;
2469 /// [Bit 10] Lock Lock bit for the PRMRR.
2473 /// [Bit 11] VLD Enable bit for the PRMRR.
2477 /// [Bits 31:12] Mask PRMRR MASK bits.
2481 /// [Bits 45:32] Mask PRMRR MASK bits.
2484 UINT32 Reserved2
:18;
2487 /// All bit fields as a 64-bit value
2490 } MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
;
2494 Core. Valid PRMRR Configurations (R/W).
2496 @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)
2497 @param EAX Lower 32-bits of MSR value.
2498 Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
2499 @param EDX Upper 32-bits of MSR value.
2500 Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
2502 <b>Example usage</b>
2504 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;
2506 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);
2507 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);
2510 #define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB
2513 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG
2517 /// Individual bit fields
2521 /// [Bit 0] 1M supported MEE size.
2526 /// [Bit 5] 32M supported MEE size.
2530 /// [Bit 6] 64M supported MEE size.
2534 /// [Bit 7] 128M supported MEE size.
2537 UINT32 Reserved2
:24;
2538 UINT32 Reserved3
:32;
2541 /// All bit fields as a 32-bit value
2545 /// All bit fields as a 64-bit value
2548 } MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
;
2552 Package. (R/W) The PRMRR range is used to protect Xucode memory from
2553 unauthorized reads and writes. Any IO access to this range is aborted. This
2554 register controls the location of the PRMRR range by indicating its starting
2555 address. It functions in tandem with the PRMRR mask register.
2557 @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)
2558 @param EAX Lower 32-bits of MSR value.
2559 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
2560 @param EDX Upper 32-bits of MSR value.
2561 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
2563 <b>Example usage</b>
2565 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;
2567 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);
2568 AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);
2571 #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4
2574 MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE
2578 /// Individual bit fields
2581 UINT32 Reserved1
:12;
2583 /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the
2584 /// base address memory range which is allocated to PRMRR memory.
2588 /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the
2589 /// base address memory range which is allocated to PRMRR memory.
2592 UINT32 Reserved2
:25;
2595 /// All bit fields as a 64-bit value
2598 } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER
;
2602 Package. (R/W) This register controls the size of the PRMRR range by
2603 indicating which address bits must match the PRMRR base register value.
2605 @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)
2606 @param EAX Lower 32-bits of MSR value.
2607 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
2608 @param EDX Upper 32-bits of MSR value.
2609 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
2611 <b>Example usage</b>
2613 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;
2615 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);
2616 AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);
2619 #define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5
2622 MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK
2626 /// Individual bit fields
2629 UINT32 Reserved1
:10;
2631 /// [Bit 10] Lock Setting this bit locks all writeable settings in this
2632 /// register, including itself.
2636 /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and
2640 UINT32 Reserved2
:20;
2641 UINT32 Reserved3
:32;
2644 /// All bit fields as a 32-bit value
2648 /// All bit fields as a 64-bit value
2651 } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
;
2654 Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits
2655 for the LLC and Ring.
2657 @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)
2658 @param EAX Lower 32-bits of MSR value.
2659 Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
2660 @param EDX Upper 32-bits of MSR value.
2661 Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
2663 <b>Example usage</b>
2665 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;
2667 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);
2668 AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);
2671 #define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620
2674 MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT
2678 /// Individual bit fields
2682 /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the
2688 /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum
2689 /// possible ratio of the LLC/Ring.
2692 UINT32 Reserved2
:17;
2693 UINT32 Reserved3
:32;
2696 /// All bit fields as a 32-bit value
2700 /// All bit fields as a 64-bit value
2703 } MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER
;
2707 Branch Monitoring Global Control (R/W).
2709 @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)
2710 @param EAX Lower 32-bits of MSR value.
2711 Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
2712 @param EDX Upper 32-bits of MSR value.
2713 Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
2715 <b>Example usage</b>
2717 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;
2719 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);
2720 AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);
2723 #define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350
2726 MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL
2730 /// Individual bit fields
2734 /// [Bit 0] EnMonitoring Global enable for branch monitoring.
2736 UINT32 EnMonitoring
:1;
2738 /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold
2739 /// trip. The branch monitoring event handler is signaled via the existing
2740 /// PMI signaling mechanism as programmed from the corresponding local
2745 /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause
2746 /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a
2747 /// triggering condition occurs and this bit is enabled.
2751 /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event
2752 /// triggering and LBR freeze actions are disabled when operating at VMX
2753 /// non-root operation.
2755 UINT32 DisableInGuest
:1;
2758 /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -
2759 /// 1023 are supported. Once the Window counter reaches the WindowSize
2760 /// count both the Window Counter and all Branch Monitoring Counters are
2763 UINT32 WindowSize
:10;
2766 /// [Bits 25:24] WindowCntSel Window event count select: '00 =
2767 /// Instructions retired. '01 = Branch instructions retired '10 = Return
2768 /// instructions retired. '11 = Indirect branch instructions retired.
2770 UINT32 WindowCntSel
:2;
2772 /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring
2773 /// event triggering condition is true only if all enabled counters'
2774 /// threshold conditions are true. When '0', the threshold tripping
2775 /// condition is true if any enabled counters' threshold is true.
2777 UINT32 CntAndMode
:1;
2779 UINT32 Reserved4
:32;
2782 /// All bit fields as a 32-bit value
2786 /// All bit fields as a 64-bit value
2789 } MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
;
2792 Branch Monitoring Global Status (R/W).
2794 @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)
2795 @param EAX Lower 32-bits of MSR value.
2796 Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
2797 @param EDX Upper 32-bits of MSR value.
2798 Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
2800 <b>Example usage</b>
2802 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;
2804 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);
2805 AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);
2808 #define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351
2811 MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS
2815 /// Individual bit fields
2819 /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch
2820 /// Monitoring event signaling is blocked until this bit is cleared by
2823 UINT32 BranchMonitoringEventSignaled
:1;
2825 /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is
2826 /// considered valid for sampling by branch monitoring software.
2831 /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This
2832 /// status bit is sticky and once set requires clearing by software.
2833 /// Counter operation continues independent of the state of the bit.
2837 /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This
2838 /// status bit is sticky and once set requires clearing by software.
2839 /// Counter operation continues independent of the state of the bit.
2844 /// [Bits 25:16] CountWindow The current value of the window counter. The
2845 /// count value is frozen on a valid branch monitoring triggering
2846 /// condition. This is a 10-bit unsigned value.
2848 UINT32 CountWindow
:10;
2851 /// [Bits 39:32] Count0 The current value of counter 0 updated after each
2852 /// occurrence of the event being counted. The count value is frozen on a
2853 /// valid branch monitoring triggering condition (in which case CntrHit0
2854 /// will also be set). This is an 8-bit signed value (2's complement).
2855 /// Heuristic events which only increment will saturate and freeze at
2856 /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
2857 /// value 0x7F (+127) and minimum value 0x80 (-128).
2861 /// [Bits 47:40] Count1 The current value of counter 1 updated after each
2862 /// occurrence of the event being counted. The count value is frozen on a
2863 /// valid branch monitoring triggering condition (in which case CntrHit1
2864 /// will also be set). This is an 8-bit signed value (2's complement).
2865 /// Heuristic events which only increment will saturate and freeze at
2866 /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
2867 /// value 0x7F (+127) and minimum value 0x80 (-128).
2870 UINT32 Reserved4
:16;
2873 /// All bit fields as a 32-bit value
2877 /// All bit fields as a 64-bit value
2880 } MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
;
2884 Package. Package C3 Residency Counter (R/O). Note: C-state values are
2885 processor specific C-state code names, unrelated to MWAIT extension C-state
2886 parameters or ACPI C-states.
2888 @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)
2889 @param EAX Lower 32-bits of MSR value.
2890 @param EDX Upper 32-bits of MSR value.
2892 <b>Example usage</b>
2896 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);
2899 #define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8
2903 Core. Core C1 Residency Counter (R/O). Value since last reset for the Core
2904 C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).
2905 This counter counts in case both of the core's threads are in an idle state
2906 and at least one of the core's thread residency is in a C1 state or in one
2907 of its sub states. The counter is updated only after a core C state exit.
2908 Note: Always reads 0 if core C1 is unsupported. A value of zero indicates
2909 that this processor does not support core C1 or never entered core C1 level
2912 @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)
2913 @param EAX Lower 32-bits of MSR value.
2914 @param EDX Upper 32-bits of MSR value.
2916 <b>Example usage</b>
2920 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);
2923 #define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660
2927 Core. Core C3 Residency Counter (R/O). Will always return 0.
2929 @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)
2930 @param EAX Lower 32-bits of MSR value.
2931 @param EDX Upper 32-bits of MSR value.
2933 <b>Example usage</b>
2937 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);
2940 #define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662
2944 Package. Protected Processor Inventory Number Enable Control (R/W).
2946 @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)
2947 @param EAX Lower 32-bits of MSR value.
2948 Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
2949 @param EDX Upper 32-bits of MSR value.
2950 Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
2952 <b>Example usage</b>
2954 MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;
2956 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);
2957 AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);
2960 #define MSR_SKYLAKE_PPIN_CTL 0x0000004E
2963 MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL
2967 /// Individual bit fields
2971 /// [Bit 0] LockOut (R/WO) See Table 2-25.
2975 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
2977 UINT32 Enable_PPIN
:1;
2978 UINT32 Reserved1
:30;
2979 UINT32 Reserved2
:32;
2982 /// All bit fields as a 32-bit value
2986 /// All bit fields as a 64-bit value
2989 } MSR_SKYLAKE_PPIN_CTL_REGISTER
;
2993 Package. Protected Processor Inventory Number (R/O). Protected Processor
2994 Inventory Number (R/O) See Table 2-25.
2996 @param ECX MSR_SKYLAKE_PPIN (0x0000004F)
2997 @param EAX Lower 32-bits of MSR value.
2998 @param EDX Upper 32-bits of MSR value.
3000 <b>Example usage</b>
3004 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);
3007 #define MSR_SKYLAKE_PPIN 0x0000004F
3011 Package. Platform Information Contains power management and other model
3012 specific features enumeration. See http://biosbits.org.
3014 @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)
3015 @param EAX Lower 32-bits of MSR value.
3016 Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
3017 @param EDX Upper 32-bits of MSR value.
3018 Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
3020 <b>Example usage</b>
3022 MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;
3024 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);
3025 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);
3028 #define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE
3031 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO
3035 /// Individual bit fields
3040 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
3042 UINT32 MaximumNon_TurboRatio
:8;
3045 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
3050 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
3053 UINT32 ProgrammableRatioLimit
:1;
3055 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
3058 UINT32 ProgrammableTDPLimit
:1;
3060 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
3062 UINT32 ProgrammableTJOFFSET
:1;
3066 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
3068 UINT32 MaximumEfficiencyRatio
:8;
3069 UINT32 Reserved6
:16;
3072 /// All bit fields as a 64-bit value
3075 } MSR_SKYLAKE_PLATFORM_INFO_REGISTER
;
3079 Core. C-State Configuration Control (R/W) Note: C-state values are processor
3080 specific C-state code names, unrelated to MWAIT extension C-state parameters
3081 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.
3083 @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)
3084 @param EAX Lower 32-bits of MSR value.
3085 Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
3086 @param EDX Upper 32-bits of MSR value.
3087 Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
3089 <b>Example usage</b>
3091 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
3093 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);
3094 AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
3097 #define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2
3100 MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL
3104 /// Individual bit fields
3108 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
3109 /// processor-specific C-state code name (consuming the least power) for
3110 /// the package. The default is set as factory-configured package Cstate
3111 /// limit. The following C-state code name encodings are supported: 000b:
3112 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
3113 /// 011b: C6 (retention) 111b: No Package C state limits. All C states
3114 /// supported by the processor are available.
3116 UINT32 C_StateLimit
:3;
3119 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
3121 UINT32 MWAITRedirectionEnable
:1;
3124 /// [Bit 15] CFG Lock (R/WO).
3128 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
3129 /// will convert HALT or MWAT(C1) to MWAIT(C6).
3131 UINT32 AutomaticC_StateConversionEnable
:1;
3134 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
3136 UINT32 C3StateAutoDemotionEnable
:1;
3138 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
3140 UINT32 C1StateAutoDemotionEnable
:1;
3142 /// [Bit 27] Enable C3 Undemotion (R/W).
3144 UINT32 EnableC3Undemotion
:1;
3146 /// [Bit 28] Enable C1 Undemotion (R/W).
3148 UINT32 EnableC1Undemotion
:1;
3150 /// [Bit 29] Package C State Demotion Enable (R/W).
3152 UINT32 CStateDemotionEnable
:1;
3154 /// [Bit 30] Package C State UnDemotion Enable (R/W).
3156 UINT32 CStateUnDemotionEnable
:1;
3158 UINT32 Reserved5
:32;
3161 /// All bit fields as a 32-bit value
3165 /// All bit fields as a 64-bit value
3168 } MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
;
3172 Thread. Global Machine Check Capability (R/O).
3174 @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)
3175 @param EAX Lower 32-bits of MSR value.
3176 Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
3177 @param EDX Upper 32-bits of MSR value.
3178 Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
3180 <b>Example usage</b>
3182 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;
3184 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);
3187 #define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179
3190 MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP
3194 /// Individual bit fields
3198 /// [Bits 7:0] Count.
3202 /// [Bit 8] MCG_CTL_P.
3206 /// [Bit 9] MCG_EXT_P.
3210 /// [Bit 10] MCP_CMCI_P.
3212 UINT32 MCP_CMCI_P
:1;
3214 /// [Bit 11] MCG_TES_P.
3219 /// [Bits 23:16] MCG_EXT_CNT.
3221 UINT32 MCG_EXT_CNT
:8;
3223 /// [Bit 24] MCG_SER_P.
3227 /// [Bit 25] MCG_EM_P.
3231 /// [Bit 26] MCG_ELOG_P.
3233 UINT32 MCG_ELOG_P
:1;
3235 UINT32 Reserved3
:32;
3238 /// All bit fields as a 32-bit value
3242 /// All bit fields as a 64-bit value
3245 } MSR_SKYLAKE_IA32_MCG_CAP_REGISTER
;
3249 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
3250 Enhancement. Accessible only while in SMM.
3252 @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)
3253 @param EAX Lower 32-bits of MSR value.
3254 Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
3255 @param EDX Upper 32-bits of MSR value.
3256 Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
3258 <b>Example usage</b>
3260 MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;
3262 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);
3263 AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);
3266 #define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D
3269 MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP
3273 /// Individual bit fields
3276 UINT32 Reserved1
:32;
3277 UINT32 Reserved2
:26;
3279 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
3280 /// SMM code access restriction is supported and a host-space interface is
3281 /// available to SMM handler.
3283 UINT32 SMM_Code_Access_Chk
:1;
3285 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
3286 /// SMM long flow indicator is supported and a host-space interface is
3287 /// available to SMM handler.
3289 UINT32 Long_Flow_Indication
:1;
3293 /// All bit fields as a 64-bit value
3296 } MSR_SKYLAKE_SMM_MCA_CAP_REGISTER
;
3300 Package. Temperature Target.
3302 @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)
3303 @param EAX Lower 32-bits of MSR value.
3304 Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
3305 @param EDX Upper 32-bits of MSR value.
3306 Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
3308 <b>Example usage</b>
3310 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;
3312 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);
3313 AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);
3316 #define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2
3319 MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET
3323 /// Individual bit fields
3326 UINT32 Reserved1
:16;
3328 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
3330 UINT32 TemperatureTarget
:8;
3332 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
3334 UINT32 TCCActivationOffset
:4;
3336 UINT32 Reserved3
:32;
3339 /// All bit fields as a 32-bit value
3343 /// All bit fields as a 64-bit value
3346 } MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER
;
3349 Package. This register defines the active core ranges for each frequency
3350 point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must
3351 be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.
3352 The last valid entry must have NUMCORE >= the number of cores in the SKU. If
3353 any of the rules above are broken, the configuration is silently rejected.
3355 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)
3356 @param EAX Lower 32-bits of MSR value.
3357 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
3358 @param EDX Upper 32-bits of MSR value.
3359 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
3361 <b>Example usage</b>
3363 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;
3365 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);
3366 AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);
3369 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE
3372 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES
3376 /// Individual bit fields
3380 /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency
3385 /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each
3386 /// frequency point.
3390 /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each
3391 /// frequency point.
3395 /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each
3396 /// frequency point.
3400 /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each
3401 /// frequency point.
3405 /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each
3406 /// frequency point.
3410 /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each
3411 /// frequency point.
3415 /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each
3416 /// frequency point.
3421 /// All bit fields as a 64-bit value
3424 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
;
3428 Package. Unit Multipliers Used in RAPL Interfaces (R/O).
3430 @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)
3431 @param EAX Lower 32-bits of MSR value.
3432 Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
3433 @param EDX Upper 32-bits of MSR value.
3434 Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
3436 <b>Example usage</b>
3438 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;
3440 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);
3443 #define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606
3446 MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT
3450 /// Individual bit fields
3454 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
3456 UINT32 PowerUnits
:4;
3459 /// [Bits 12:8] Package. Energy Status Units Energy related information
3460 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
3461 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
3464 UINT32 EnergyStatusUnits
:5;
3467 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
3471 UINT32 Reserved3
:12;
3472 UINT32 Reserved4
:32;
3475 /// All bit fields as a 32-bit value
3479 /// All bit fields as a 64-bit value
3482 } MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER
;
3486 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
3489 @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)
3490 @param EAX Lower 32-bits of MSR value.
3491 @param EDX Upper 32-bits of MSR value.
3493 <b>Example usage</b>
3497 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);
3498 AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);
3501 #define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618
3505 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
3507 @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)
3508 @param EAX Lower 32-bits of MSR value.
3509 Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
3510 @param EDX Upper 32-bits of MSR value.
3511 Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
3513 <b>Example usage</b>
3515 MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;
3517 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);
3520 #define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619
3523 MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS
3527 /// Individual bit fields
3531 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
3532 /// to enable DRAM RAPL mode 0 (Direct VR).
3538 /// All bit fields as a 32-bit value
3542 /// All bit fields as a 64-bit value
3545 } MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER
;
3549 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
3552 @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)
3553 @param EAX Lower 32-bits of MSR value.
3554 @param EDX Upper 32-bits of MSR value.
3556 <b>Example usage</b>
3560 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);
3563 #define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B
3567 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
3569 @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)
3570 @param EAX Lower 32-bits of MSR value.
3571 @param EDX Upper 32-bits of MSR value.
3573 <b>Example usage</b>
3577 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);
3578 AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);
3581 #define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C
3585 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
3586 fields represent the widest possible range of uncore frequencies. Writing to
3587 these fields allows software to control the minimum and the maximum
3588 frequency that hardware will select.
3590 @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)
3591 @param EAX Lower 32-bits of MSR value.
3592 Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
3593 @param EDX Upper 32-bits of MSR value.
3594 Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
3596 <b>Example usage</b>
3598 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
3600 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);
3601 AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
3604 #define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620
3607 MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT
3611 /// Individual bit fields
3615 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
3621 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
3622 /// possible ratio of the LLC/Ring.
3625 UINT32 Reserved2
:17;
3626 UINT32 Reserved3
:32;
3629 /// All bit fields as a 32-bit value
3633 /// All bit fields as a 64-bit value
3636 } MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER
;
3640 Package. Reserved (R/O) Reads return 0.
3642 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
3643 @param EAX Lower 32-bits of MSR value.
3644 @param EDX Upper 32-bits of MSR value.
3646 <b>Example usage</b>
3650 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
3653 #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
3657 THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,
3658 ECX=0):EBX.RDT-M[bit 12] = 1.
3660 @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)
3661 @param EAX Lower 32-bits of MSR value.
3662 Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
3663 @param EDX Upper 32-bits of MSR value.
3664 Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
3666 <b>Example usage</b>
3668 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;
3670 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);
3671 AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);
3674 #define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D
3677 MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL
3681 /// Individual bit fields
3685 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3
3686 /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:
3687 /// Local memory bandwidth monitoring. All other encoding reserved.
3690 UINT32 Reserved1
:24;
3692 /// [Bits 41:32] RMID (RW).
3695 UINT32 Reserved2
:22;
3698 /// All bit fields as a 64-bit value
3701 } MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER
;
3705 THREAD. Resource Association Register (R/W).
3707 @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)
3708 @param EAX Lower 32-bits of MSR value.
3709 Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
3710 @param EDX Upper 32-bits of MSR value.
3711 Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
3713 <b>Example usage</b>
3715 MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;
3717 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);
3718 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);
3721 #define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F
3724 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC
3728 /// Individual bit fields
3732 /// [Bits 9:0] RMID.
3735 UINT32 Reserved1
:22;
3737 /// [Bits 51:32] COS (R/W).
3740 UINT32 Reserved2
:12;
3743 /// All bit fields as a 64-bit value
3746 } MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER
;
3750 Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,
3751 ECX=1):EDX.COS_MAX[15:0] >=0.
3753 @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N
3754 @param EAX Lower 32-bits of MSR value.
3755 Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
3756 @param EDX Upper 32-bits of MSR value.
3757 Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
3759 <b>Example usage</b>
3761 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;
3763 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);
3764 AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);
3767 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90
3768 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91
3769 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92
3770 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93
3771 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94
3772 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95
3773 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96
3774 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97
3775 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98
3776 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99
3777 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A
3778 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B
3779 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C
3780 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D
3781 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E
3782 #define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F
3785 MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N
3789 /// Individual bit fields
3793 /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.
3796 UINT32 Reserved2
:12;
3797 UINT32 Reserved3
:32;
3800 /// All bit fields as a 32-bit value
3804 /// All bit fields as a 64-bit value
3807 } MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER
;