UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  20   May 2018, Volume 4: Model-Specific-Registers (MSR)
  21
  22 **/
  23
  24 #ifndef __XEON_5600_MSR_H__
  25 #define __XEON_5600_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Is Intel(R) Xeon(R) Processor Series 5600?
  31
  32   @param   DisplayFamily  Display Family ID
  33   @param   DisplayModel   Display Model ID
  34
  35   @retval  TRUE   Yes, it is.
  36   @retval  FALSE  No, it isn't.
  37 **/
  38 #define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
  39   (DisplayFamily == 0x06 && \
  40    (                        \
  41     DisplayModel == 0x25 || \
  42     DisplayModel == 0x2C    \
  43     )                       \
  44    )
  45
  46 /**
  47   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  48   handler to handle unsuccessful read of this MSR.
  49
  50   @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
  51   @param  EAX  Lower 32-bits of MSR value.
  52                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  53   @param  EDX  Upper 32-bits of MSR value.
  54                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  55
  56   <b>Example usage</b>
  57   @code
  58   MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
  59
  60   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
  61   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
  62   @endcode
  63   @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  64 **/
  65 #define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C
  66
  67 /**
  68   MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
  69 **/
  70 typedef union {
  71   ///
  72   /// Individual bit fields
  73   ///
  74   struct {
  75     ///
  76     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  77     /// MSR, the configuration of AES instruction set availability is as
  78     /// follows: 11b: AES instructions are not available until next RESET.
  79     /// otherwise, AES instructions are available. Note, AES instruction set
  80     /// is not available if read is unsuccessful. If the configuration is not
  81     /// 01b, AES instruction can be mis-configured if a privileged agent
  82     /// unintentionally writes 11b.
  83     ///
  84     UINT32  AESConfiguration:2;
  85     UINT32  Reserved1:30;
  86     UINT32  Reserved2:32;
  87   } Bits;
  88   ///
  89   /// All bit fields as a 32-bit value
  90   ///
  91   UINT32  Uint32;
  92   ///
  93   /// All bit fields as a 64-bit value
  94   ///
  95   UINT64  Uint64;
  96 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
  97
  98
  99 /**
 100   Thread. Offcore Response Event Select Register (R/W).
 101
 102   @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
 103   @param  EAX  Lower 32-bits of MSR value.
 104   @param  EDX  Upper 32-bits of MSR value.
 105
 106   <b>Example usage</b>
 107   @code
 108   UINT64  Msr;
 109
 110   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
 111   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
 112   @endcode
 113   @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 114 **/
 115 #define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7
 116
 117
 118 /**
 119   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 120   RW if MSR_PLATFORM_INFO.[28] = 1.
 121
 122   @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
 123   @param  EAX  Lower 32-bits of MSR value.
 124                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 125   @param  EDX  Upper 32-bits of MSR value.
 126                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 127
 128   <b>Example usage</b>
 129   @code
 130   MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
 131
 132   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
 133   @endcode
 134   @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 135 **/
 136 #define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD
 137
 138 /**
 139   MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
 140 **/
 141 typedef union {
 142   ///
 143   /// Individual bit fields
 144   ///
 145   struct {
 146     ///
 147     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 148     /// limit of 1 core active.
 149     ///
 150     UINT32  Maximum1C:8;
 151     ///
 152     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 153     /// limit of 2 core active.
 154     ///
 155     UINT32  Maximum2C:8;
 156     ///
 157     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 158     /// limit of 3 core active.
 159     ///
 160     UINT32  Maximum3C:8;
 161     ///
 162     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 163     /// limit of 4 core active.
 164     ///
 165     UINT32  Maximum4C:8;
 166     ///
 167     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 168     /// limit of 5 core active.
 169     ///
 170     UINT32  Maximum5C:8;
 171     ///
 172     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 173     /// limit of 6 core active.
 174     ///
 175     UINT32  Maximum6C:8;
 176     UINT32  Reserved:16;
 177   } Bits;
 178   ///
 179   /// All bit fields as a 64-bit value
 180   ///
 181   UINT64  Uint64;
 182 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
 183
 184
 185 /**
 186   Package. See Table 2-2.
 187
 188   @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
 189   @param  EAX  Lower 32-bits of MSR value.
 190   @param  EDX  Upper 32-bits of MSR value.
 191
 192   <b>Example usage</b>
 193   @code
 194   UINT64  Msr;
 195
 196   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
 197   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
 198   @endcode
 199   @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
 200 **/
 201 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0
 202
 203 #endif