UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
  21
  22 **/
  23
  24 #ifndef __XEON_5600_MSR_H__
  25 #define __XEON_5600_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  31   handler to handle unsuccessful read of this MSR.
  32
  33   @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
  34   @param  EAX  Lower 32-bits of MSR value.
  35                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  36   @param  EDX  Upper 32-bits of MSR value.
  37                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  38
  39   <b>Example usage</b>
  40   @code
  41   MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
  42
  43   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
  44   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
  45   @endcode
  46 **/
  47 #define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C
  48
  49 /**
  50   MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
  51 **/
  52 typedef union {
  53   ///
  54   /// Individual bit fields
  55   ///
  56   struct {
  57     ///
  58     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  59     /// MSR, the configuration of AES instruction set availability is as
  60     /// follows: 11b: AES instructions are not available until next RESET.
  61     /// otherwise, AES instructions are available. Note, AES instruction set
  62     /// is not available if read is unsuccessful. If the configuration is not
  63     /// 01b, AES instruction can be mis-configured if a privileged agent
  64     /// unintentionally writes 11b.
  65     ///
  66     UINT32  AESConfiguration:2;
  67     UINT32  Reserved1:30;
  68     UINT32  Reserved2:32;
  69   } Bits;
  70   ///
  71   /// All bit fields as a 32-bit value
  72   ///
  73   UINT32  Uint32;
  74   ///
  75   /// All bit fields as a 64-bit value
  76   ///
  77   UINT64  Uint64;
  78 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
  79
  80
  81 /**
  82   Thread. Offcore Response Event Select Register (R/W).
  83
  84   @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
  85   @param  EAX  Lower 32-bits of MSR value.
  86   @param  EDX  Upper 32-bits of MSR value.
  87
  88   <b>Example usage</b>
  89   @code
  90   UINT64  Msr;
  91
  92   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
  93   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
  94   @endcode
  95 **/
  96 #define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7
  97
  98
  99 /**
 100   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 101   RW if MSR_PLATFORM_INFO.[28] = 1.
 102
 103   @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
 104   @param  EAX  Lower 32-bits of MSR value.
 105                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 106   @param  EDX  Upper 32-bits of MSR value.
 107                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 108
 109   <b>Example usage</b>
 110   @code
 111   MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
 112
 113   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
 114   @endcode
 115 **/
 116 #define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD
 117
 118 /**
 119   MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
 120 **/
 121 typedef union {
 122   ///
 123   /// Individual bit fields
 124   ///
 125   struct {
 126     ///
 127     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 128     /// limit of 1 core active.
 129     ///
 130     UINT32  Maximum1C:8;
 131     ///
 132     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 133     /// limit of 2 core active.
 134     ///
 135     UINT32  Maximum2C:8;
 136     ///
 137     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 138     /// limit of 3 core active.
 139     ///
 140     UINT32  Maximum3C:8;
 141     ///
 142     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 143     /// limit of 4 core active.
 144     ///
 145     UINT32  Maximum4C:8;
 146     ///
 147     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 148     /// limit of 5 core active.
 149     ///
 150     UINT32  Maximum5C:8;
 151     ///
 152     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 153     /// limit of 6 core active.
 154     ///
 155     UINT32  Maximum6C:8;
 156     UINT32  Reserved:16;
 157   } Bits;
 158   ///
 159   /// All bit fields as a 64-bit value
 160   ///
 161   UINT64  Uint64;
 162 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
 163
 164
 165 /**
 166   Package. See Table 35-2.
 167
 168   @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
 169   @param  EAX  Lower 32-bits of MSR value.
 170   @param  EDX  Upper 32-bits of MSR value.
 171
 172   <b>Example usage</b>
 173   @code
 174   UINT64  Msr;
 175
 176   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
 177   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
 178   @endcode
 179 **/
 180 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0
 181
 182 #endif