2 MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.
24 #ifndef __XEON_5600_MSR_H__
25 #define __XEON_5600_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel(R) Xeon(R) Processor Series 5600?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x25 || \
42 DisplayModel == 0x2C \
47 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
48 handler to handle unsuccessful read of this MSR.
50 @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
51 @param EAX Lower 32-bits of MSR value.
52 Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
53 @param EDX Upper 32-bits of MSR value.
54 Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
58 MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;
60 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
61 AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
63 @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
65 #define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
68 MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
72 /// Individual bit fields
76 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
77 /// MSR, the configuration of AES instruction set availability is as
78 /// follows: 11b: AES instructions are not available until next RESET.
79 /// otherwise, AES instructions are available. Note, AES instruction set
80 /// is not available if read is unsuccessful. If the configuration is not
81 /// 01b, AES instruction can be mis-configured if a privileged agent
82 /// unintentionally writes 11b.
84 UINT32 AESConfiguration
:2;
89 /// All bit fields as a 32-bit value
93 /// All bit fields as a 64-bit value
96 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER
;
100 Thread. Offcore Response Event Select Register (R/W).
102 @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
103 @param EAX Lower 32-bits of MSR value.
104 @param EDX Upper 32-bits of MSR value.
110 Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
111 AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
113 @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
115 #define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
119 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
120 RW if MSR_PLATFORM_INFO.[28] = 1.
122 @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
123 @param EAX Lower 32-bits of MSR value.
124 Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
125 @param EDX Upper 32-bits of MSR value.
126 Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
130 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;
132 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
134 @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
136 #define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
139 MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
143 /// Individual bit fields
147 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
148 /// limit of 1 core active.
152 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
153 /// limit of 2 core active.
157 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
158 /// limit of 3 core active.
162 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
163 /// limit of 4 core active.
167 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
168 /// limit of 5 core active.
172 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
173 /// limit of 6 core active.
179 /// All bit fields as a 64-bit value
182 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
;
186 Package. See Table 35-2.
188 @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
189 @param EAX Lower 32-bits of MSR value.
190 @param EDX Upper 32-bits of MSR value.
196 Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
197 AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
199 @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
201 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0