UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __XEON_E7_MSR_H__
  19 #define __XEON_E7_MSR_H__
  20
  21 #include <Register/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel(R) Xeon(R) Processor E7 Family?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x2F    \
  36     )                       \
  37    )
  38
  39 /**
  40   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  41   handler to handle unsuccessful read of this MSR.
  42
  43   @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
  44   @param  EAX  Lower 32-bits of MSR value.
  45                Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
  46   @param  EDX  Upper 32-bits of MSR value.
  47                Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
  48
  49   <b>Example usage</b>
  50   @code
  51   MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;
  52
  53   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
  54   AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
  55   @endcode
  56   @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  57 **/
  58 #define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C
  59
  60 /**
  61   MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
  62 **/
  63 typedef union {
  64   ///
  65   /// Individual bit fields
  66   ///
  67   struct {
  68     ///
  69     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  70     /// MSR, the configuration of AES instruction set availability is as
  71     /// follows: 11b: AES instructions are not available until next RESET.
  72     /// otherwise, AES instructions are available. Note, AES instruction set
  73     /// is not available if read is unsuccessful. If the configuration is not
  74     /// 01b, AES instruction can be mis-configured if a privileged agent
  75     /// unintentionally writes 11b.
  76     ///
  77     UINT32  AESConfiguration:2;
  78     UINT32  Reserved1:30;
  79     UINT32  Reserved2:32;
  80   } Bits;
  81   ///
  82   /// All bit fields as a 32-bit value
  83   ///
  84   UINT32  Uint32;
  85   ///
  86   /// All bit fields as a 64-bit value
  87   ///
  88   UINT64  Uint64;
  89 } MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
  90
  91
  92 /**
  93   Thread. Offcore Response Event Select Register (R/W).
  94
  95   @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
  96   @param  EAX  Lower 32-bits of MSR value.
  97   @param  EDX  Upper 32-bits of MSR value.
  98
  99   <b>Example usage</b>
 100   @code
 101   UINT64  Msr;
 102
 103   Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
 104   AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
 105   @endcode
 106   @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 107 **/
 108 #define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7
 109
 110
 111 /**
 112   Package. Reserved Attempt to read/write will cause #UD.
 113
 114   @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
 115   @param  EAX  Lower 32-bits of MSR value.
 116   @param  EDX  Upper 32-bits of MSR value.
 117
 118   <b>Example usage</b>
 119   @code
 120   UINT64  Msr;
 121
 122   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
 123   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
 124   @endcode
 125   @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 126 **/
 127 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD
 128
 129
 130 /**
 131   Package. Uncore C-box 8 perfmon local box control MSR.
 132
 133   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
 134   @param  EAX  Lower 32-bits of MSR value.
 135   @param  EDX  Upper 32-bits of MSR value.
 136
 137   <b>Example usage</b>
 138   @code
 139   UINT64  Msr;
 140
 141   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
 142   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
 143   @endcode
 144   @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
 145 **/
 146 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40
 147
 148
 149 /**
 150   Package. Uncore C-box 8 perfmon local box status MSR.
 151
 152   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
 153   @param  EAX  Lower 32-bits of MSR value.
 154   @param  EDX  Upper 32-bits of MSR value.
 155
 156   <b>Example usage</b>
 157   @code
 158   UINT64  Msr;
 159
 160   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
 161   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
 162   @endcode
 163   @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
 164 **/
 165 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41
 166
 167
 168 /**
 169   Package. Uncore C-box 8 perfmon local box overflow control MSR.
 170
 171   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
 172   @param  EAX  Lower 32-bits of MSR value.
 173   @param  EDX  Upper 32-bits of MSR value.
 174
 175   <b>Example usage</b>
 176   @code
 177   UINT64  Msr;
 178
 179   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
 180   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
 181   @endcode
 182   @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
 183 **/
 184 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42
 185
 186
 187 /**
 188   Package. Uncore C-box 8 perfmon event select MSR.
 189
 190   @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
 191   @param  EAX  Lower 32-bits of MSR value.
 192   @param  EDX  Upper 32-bits of MSR value.
 193
 194   <b>Example usage</b>
 195   @code
 196   UINT64  Msr;
 197
 198   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
 199   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
 200   @endcode
 201   @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
 202         MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
 203         MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
 204         MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
 205         MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
 206         MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
 207   @{
 208 **/
 209 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50
 210 #define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52
 211 #define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54
 212 #define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56
 213 #define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58
 214 #define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A
 215 /// @}
 216
 217
 218 /**
 219   Package. Uncore C-box 8 perfmon counter MSR.
 220
 221   @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
 222   @param  EAX  Lower 32-bits of MSR value.
 223   @param  EDX  Upper 32-bits of MSR value.
 224
 225   <b>Example usage</b>
 226   @code
 227   UINT64  Msr;
 228
 229   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
 230   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
 231   @endcode
 232   @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
 233         MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
 234         MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
 235         MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
 236         MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
 237         MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
 238   @{
 239 **/
 240 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51
 241 #define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53
 242 #define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55
 243 #define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57
 244 #define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59
 245 #define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B
 246 /// @}
 247
 248
 249 /**
 250   Package. Uncore C-box 9 perfmon local box control MSR.
 251
 252   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
 253   @param  EAX  Lower 32-bits of MSR value.
 254   @param  EDX  Upper 32-bits of MSR value.
 255
 256   <b>Example usage</b>
 257   @code
 258   UINT64  Msr;
 259
 260   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
 261   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
 262   @endcode
 263   @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
 264 **/
 265 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0
 266
 267
 268 /**
 269   Package. Uncore C-box 9 perfmon local box status MSR.
 270
 271   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
 272   @param  EAX  Lower 32-bits of MSR value.
 273   @param  EDX  Upper 32-bits of MSR value.
 274
 275   <b>Example usage</b>
 276   @code
 277   UINT64  Msr;
 278
 279   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
 280   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
 281   @endcode
 282   @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 283 **/
 284 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1
 285
 286
 287 /**
 288   Package. Uncore C-box 9 perfmon local box overflow control MSR.
 289
 290   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
 291   @param  EAX  Lower 32-bits of MSR value.
 292   @param  EDX  Upper 32-bits of MSR value.
 293
 294   <b>Example usage</b>
 295   @code
 296   UINT64  Msr;
 297
 298   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
 299   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
 300   @endcode
 301   @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
 302 **/
 303 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2
 304
 305
 306 /**
 307   Package. Uncore C-box 9 perfmon event select MSR.
 308
 309   @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn
 310   @param  EAX  Lower 32-bits of MSR value.
 311   @param  EDX  Upper 32-bits of MSR value.
 312
 313   <b>Example usage</b>
 314   @code
 315   UINT64  Msr;
 316
 317   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
 318   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
 319   @endcode
 320   @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
 321         MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
 322         MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
 323         MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
 324         MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
 325         MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
 326   @{
 327 **/
 328 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0
 329 #define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2
 330 #define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4
 331 #define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6
 332 #define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8
 333 #define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA
 334 /// @}
 335
 336
 337 /**
 338   Package. Uncore C-box 9 perfmon counter MSR.
 339
 340   @param  ECX  MSR_XEON_E7_C9_PMON_CTRn
 341   @param  EAX  Lower 32-bits of MSR value.
 342   @param  EDX  Upper 32-bits of MSR value.
 343
 344   <b>Example usage</b>
 345   @code
 346   UINT64  Msr;
 347
 348   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
 349   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
 350   @endcode
 351   @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
 352         MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
 353         MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
 354         MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
 355         MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
 356         MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
 357   @{
 358 **/
 359 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1
 360 #define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3
 361 #define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5
 362 #define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7
 363 #define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9
 364 #define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB
 365 /// @}
 366
 367 #endif