UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
  21
  22 **/
  23
  24 #ifndef __XEON_E7_MSR_H__
  25 #define __XEON_E7_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Is Intel(R) Xeon(R) Processor E7 Family?
  31
  32   @param   DisplayFamily  Display Family ID
  33   @param   DisplayModel   Display Model ID
  34
  35   @retval  TRUE   Yes, it is.
  36   @retval  FALSE  No, it isn't.
  37 **/
  38 #define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
  39   (DisplayFamily == 0x06 && \
  40    (                        \
  41     DisplayModel == 0x2F    \
  42     )                       \
  43    )
  44
  45 /**
  46   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  47   handler to handle unsuccessful read of this MSR.
  48
  49   @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
  50   @param  EAX  Lower 32-bits of MSR value.
  51                Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
  52   @param  EDX  Upper 32-bits of MSR value.
  53                Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
  54
  55   <b>Example usage</b>
  56   @code
  57   MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;
  58
  59   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
  60   AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
  61   @endcode
  62   @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  63 **/
  64 #define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C
  65
  66 /**
  67   MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
  68 **/
  69 typedef union {
  70   ///
  71   /// Individual bit fields
  72   ///
  73   struct {
  74     ///
  75     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  76     /// MSR, the configuration of AES instruction set availability is as
  77     /// follows: 11b: AES instructions are not available until next RESET.
  78     /// otherwise, AES instructions are available. Note, AES instruction set
  79     /// is not available if read is unsuccessful. If the configuration is not
  80     /// 01b, AES instruction can be mis-configured if a privileged agent
  81     /// unintentionally writes 11b.
  82     ///
  83     UINT32  AESConfiguration:2;
  84     UINT32  Reserved1:30;
  85     UINT32  Reserved2:32;
  86   } Bits;
  87   ///
  88   /// All bit fields as a 32-bit value
  89   ///
  90   UINT32  Uint32;
  91   ///
  92   /// All bit fields as a 64-bit value
  93   ///
  94   UINT64  Uint64;
  95 } MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
  96
  97
  98 /**
  99   Thread. Offcore Response Event Select Register (R/W).
 100
 101   @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
 102   @param  EAX  Lower 32-bits of MSR value.
 103   @param  EDX  Upper 32-bits of MSR value.
 104
 105   <b>Example usage</b>
 106   @code
 107   UINT64  Msr;
 108
 109   Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
 110   AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
 111   @endcode
 112   @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 113 **/
 114 #define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7
 115
 116
 117 /**
 118   Package. Reserved Attempt to read/write will cause #UD.
 119
 120   @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
 121   @param  EAX  Lower 32-bits of MSR value.
 122   @param  EDX  Upper 32-bits of MSR value.
 123
 124   <b>Example usage</b>
 125   @code
 126   UINT64  Msr;
 127
 128   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
 129   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
 130   @endcode
 131   @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 132 **/
 133 #define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD
 134
 135
 136 /**
 137   Package. Uncore C-box 8 perfmon local box control MSR.
 138
 139   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
 140   @param  EAX  Lower 32-bits of MSR value.
 141   @param  EDX  Upper 32-bits of MSR value.
 142
 143   <b>Example usage</b>
 144   @code
 145   UINT64  Msr;
 146
 147   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
 148   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
 149   @endcode
 150   @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
 151 **/
 152 #define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40
 153
 154
 155 /**
 156   Package. Uncore C-box 8 perfmon local box status MSR.
 157
 158   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
 159   @param  EAX  Lower 32-bits of MSR value.
 160   @param  EDX  Upper 32-bits of MSR value.
 161
 162   <b>Example usage</b>
 163   @code
 164   UINT64  Msr;
 165
 166   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
 167   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
 168   @endcode
 169   @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
 170 **/
 171 #define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41
 172
 173
 174 /**
 175   Package. Uncore C-box 8 perfmon local box overflow control MSR.
 176
 177   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
 178   @param  EAX  Lower 32-bits of MSR value.
 179   @param  EDX  Upper 32-bits of MSR value.
 180
 181   <b>Example usage</b>
 182   @code
 183   UINT64  Msr;
 184
 185   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
 186   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
 187   @endcode
 188   @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
 189 **/
 190 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42
 191
 192
 193 /**
 194   Package. Uncore C-box 8 perfmon event select MSR.
 195
 196   @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
 197   @param  EAX  Lower 32-bits of MSR value.
 198   @param  EDX  Upper 32-bits of MSR value.
 199
 200   <b>Example usage</b>
 201   @code
 202   UINT64  Msr;
 203
 204   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
 205   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
 206   @endcode
 207   @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
 208         MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
 209         MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
 210         MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
 211         MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
 212         MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
 213   @{
 214 **/
 215 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50
 216 #define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52
 217 #define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54
 218 #define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56
 219 #define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58
 220 #define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A
 221 /// @}
 222
 223
 224 /**
 225   Package. Uncore C-box 8 perfmon counter MSR.
 226
 227   @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
 228   @param  EAX  Lower 32-bits of MSR value.
 229   @param  EDX  Upper 32-bits of MSR value.
 230
 231   <b>Example usage</b>
 232   @code
 233   UINT64  Msr;
 234
 235   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
 236   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
 237   @endcode
 238   @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
 239         MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
 240         MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
 241         MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
 242         MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
 243         MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
 244   @{
 245 **/
 246 #define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51
 247 #define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53
 248 #define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55
 249 #define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57
 250 #define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59
 251 #define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B
 252 /// @}
 253
 254
 255 /**
 256   Package. Uncore C-box 9 perfmon local box control MSR.
 257
 258   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
 259   @param  EAX  Lower 32-bits of MSR value.
 260   @param  EDX  Upper 32-bits of MSR value.
 261
 262   <b>Example usage</b>
 263   @code
 264   UINT64  Msr;
 265
 266   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
 267   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
 268   @endcode
 269   @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
 270 **/
 271 #define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0
 272
 273
 274 /**
 275   Package. Uncore C-box 9 perfmon local box status MSR.
 276
 277   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
 278   @param  EAX  Lower 32-bits of MSR value.
 279   @param  EDX  Upper 32-bits of MSR value.
 280
 281   <b>Example usage</b>
 282   @code
 283   UINT64  Msr;
 284
 285   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
 286   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
 287   @endcode
 288   @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 289 **/
 290 #define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1
 291
 292
 293 /**
 294   Package. Uncore C-box 9 perfmon local box overflow control MSR.
 295
 296   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
 297   @param  EAX  Lower 32-bits of MSR value.
 298   @param  EDX  Upper 32-bits of MSR value.
 299
 300   <b>Example usage</b>
 301   @code
 302   UINT64  Msr;
 303
 304   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
 305   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
 306   @endcode
 307   @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
 308 **/
 309 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2
 310
 311
 312 /**
 313   Package. Uncore C-box 9 perfmon event select MSR.
 314
 315   @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn
 316   @param  EAX  Lower 32-bits of MSR value.
 317   @param  EDX  Upper 32-bits of MSR value.
 318
 319   <b>Example usage</b>
 320   @code
 321   UINT64  Msr;
 322
 323   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
 324   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
 325   @endcode
 326   @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
 327         MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
 328         MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
 329         MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
 330         MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
 331         MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
 332   @{
 333 **/
 334 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0
 335 #define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2
 336 #define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4
 337 #define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6
 338 #define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8
 339 #define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA
 340 /// @}
 341
 342
 343 /**
 344   Package. Uncore C-box 9 perfmon counter MSR.
 345
 346   @param  ECX  MSR_XEON_E7_C9_PMON_CTRn
 347   @param  EAX  Lower 32-bits of MSR value.
 348   @param  EDX  Upper 32-bits of MSR value.
 349
 350   <b>Example usage</b>
 351   @code
 352   UINT64  Msr;
 353
 354   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
 355   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
 356   @endcode
 357   @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
 358         MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
 359         MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
 360         MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
 361         MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
 362         MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
 363   @{
 364 **/
 365 #define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1
 366 #define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3
 367 #define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5
 368 #define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7
 369 #define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9
 370 #define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB
 371 /// @}
 372
 373 #endif