2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __XEON_PHI_MSR_H__
25 #define __XEON_PHI_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Is Intel(R) Xeon(R) Phi(TM) processor Family?
32 @param DisplayFamily Display Family ID
33 @param DisplayModel Display Model ID
35 @retval TRUE Yes, it is.
36 @retval FALSE No, it isn't.
38 #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
39 (DisplayFamily == 0x06 && \
41 DisplayModel == 0x57 || \
42 DisplayModel == 0x85 \
47 Thread. SMI Counter (R/O).
49 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
50 @param EAX Lower 32-bits of MSR value.
51 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
52 @param EDX Upper 32-bits of MSR value.
53 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
57 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
59 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
61 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
63 #define MSR_XEON_PHI_SMI_COUNT 0x00000034
66 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
70 /// Individual bit fields
74 /// [Bits 31:0] SMI Count (R/O).
80 /// All bit fields as a 32-bit value
84 /// All bit fields as a 64-bit value
87 } MSR_XEON_PHI_SMI_COUNT_REGISTER
;
90 Package. Protected Processor Inventory Number Enable Control (R/W).
92 @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)
93 @param EAX Lower 32-bits of MSR value.
94 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
95 @param EDX Upper 32-bits of MSR value.
96 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
100 MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
102 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
103 AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
106 #define MSR_XEON_PHI_PPIN_CTL 0x0000004E
109 MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
113 /// Individual bit fields
117 /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
118 /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
119 /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
120 /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
121 /// privileged inventory initialization agent to access MSR_PPIN. After
122 /// reading MSR_PPIN, the privileged inventory initialization agent should
123 /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
124 /// prevent unauthorized modification to MSR_PPIN_CTL.
128 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
129 /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
130 /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
133 UINT32 Enable_PPIN
:1;
138 /// All bit fields as a 32-bit value
142 /// All bit fields as a 64-bit value
145 } MSR_XEON_PHI_PPIN_CTL_REGISTER
;
149 Package. Protected Processor Inventory Number (R/O). Protected Processor
150 Inventory Number (R/O) A unique value within a given CPUID
151 family/model/stepping signature that a privileged inventory initialization
152 agent can access to identify each physical processor, when access to
153 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
154 MSR_PPIN_CTL[bits 1:0] = '10b'.
156 @param ECX MSR_XEON_PHI_PPIN (0x0000004F)
157 @param EAX Lower 32-bits of MSR value.
158 @param EDX Upper 32-bits of MSR value.
164 Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
167 #define MSR_XEON_PHI_PPIN 0x0000004F
170 Package. Platform Information Contains power management and other model
171 specific features enumeration. See http://biosbits.org.
173 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
174 @param EAX Lower 32-bits of MSR value.
175 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
176 @param EDX Upper 32-bits of MSR value.
177 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
181 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
183 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
184 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
186 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
188 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
191 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
195 /// Individual bit fields
200 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
201 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
204 UINT32 MaximumNonTurboRatio
:8;
207 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
208 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
209 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
210 /// Turbo mode is disabled.
214 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
215 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
216 /// and when set to 0, indicates TDP Limit for Turbo mode is not
223 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
224 /// minimum ratio (maximum efficiency) that the processor can operates, in
227 UINT32 MaximumEfficiencyRatio
:8;
231 /// All bit fields as a 64-bit value
234 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER
;
238 Module. C-State Configuration Control (R/W).
240 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
241 @param EAX Lower 32-bits of MSR value.
242 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
243 @param EDX Upper 32-bits of MSR value.
244 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
248 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
250 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
251 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
253 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
255 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
258 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
262 /// Individual bit fields
266 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
267 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
268 /// Retention 011b: C6 Retention 111b: No limit.
273 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
278 /// [Bit 15] CFG Lock (R/WO).
283 /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
284 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
285 /// auto-demote information.
287 UINT32 C1StateAutoDemotionEnable
:1;
290 /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
291 /// Undemotion from Demoted C1.
293 UINT32 C1StateAutoUndemotionEnable
:1;
295 /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
296 /// Package C state demotion.
298 UINT32 PKGC_StateAutoDemotionEnable
:1;
303 /// All bit fields as a 32-bit value
307 /// All bit fields as a 64-bit value
310 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
;
314 Module. Power Management IO Redirection in C-state (R/W).
316 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
317 @param EAX Lower 32-bits of MSR value.
318 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
319 @param EDX Upper 32-bits of MSR value.
320 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
324 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
326 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
327 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
329 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
331 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
334 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
338 /// Individual bit fields
342 /// [Bits 15:0] LVL_2 Base Address (R/W).
346 /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
347 /// IO-redirection will be executed (0-127). Should be programmed based on
348 /// the number of LVLx registers existing in the chipset.
350 UINT32 CStateRange
:7;
355 /// All bit fields as a 32-bit value
359 /// All bit fields as a 64-bit value
362 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
;
366 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
367 handler to handle unsuccessful read of this MSR.
369 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
370 @param EAX Lower 32-bits of MSR value.
371 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
372 @param EDX Upper 32-bits of MSR value.
373 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
377 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
379 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
380 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
382 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
384 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
387 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
391 /// Individual bit fields
395 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
396 /// MSR, the configuration of AES instruction set availability is as
397 /// follows: 11b: AES instructions are not available until next RESET.
398 /// otherwise, AES instructions are available. Note, AES instruction set
399 /// is not available if read is unsuccessful. If the configuration is not
400 /// 01b, AES instruction can be mis-configured if a privileged agent
401 /// unintentionally writes 11b.
403 UINT32 AESConfiguration
:2;
408 /// All bit fields as a 32-bit value
412 /// All bit fields as a 64-bit value
415 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
;
419 Thread. MISC_FEATURE_ENABLES.
421 @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
422 @param EAX Lower 32-bits of MSR value.
423 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
424 @param EDX Upper 32-bits of MSR value.
425 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
429 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
431 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
432 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
435 #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
438 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
442 /// Individual bit fields
447 /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
448 /// MWAIT instructions do not cause invalid-opcode exceptions when
449 /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
450 /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
451 /// other than C0 or C1, the instruction operates as if EAX indicated the
454 UINT32 UserModeMonitorAndMwait
:1;
459 /// All bit fields as a 32-bit value
463 /// All bit fields as a 64-bit value
466 } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
;
469 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
470 Enhancement. Accessible only while in SMM.
472 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
473 @param EAX Lower 32-bits of MSR value.
474 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
475 @param EDX Upper 32-bits of MSR value.
476 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
480 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
482 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
483 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
485 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
487 #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
490 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
494 /// Individual bit fields
498 /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
499 /// set, that bank supports Enhanced MCA (Default all 0; does not support
502 UINT32 BankSupport
:32;
505 /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
507 UINT32 TargetedSMI
:1;
509 /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
512 UINT32 SMM_CPU_SVRSTR
:1;
514 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
515 /// SMM code access restriction is supported and a host-space interface
516 /// available to SMM handler.
518 UINT32 SMM_Code_Access_Chk
:1;
520 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
521 /// SMM long flow indicator is supported and a host-space interface
522 /// available to SMM handler.
524 UINT32 Long_Flow_Indication
:1;
528 /// All bit fields as a 64-bit value
531 } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
;
535 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
536 functions to be enabled and disabled.
538 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
539 @param EAX Lower 32-bits of MSR value.
540 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
541 @param EDX Upper 32-bits of MSR value.
542 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
546 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
548 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
549 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
551 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
553 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
556 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
560 /// Individual bit fields
564 /// [Bit 0] Fast-Strings Enable.
566 UINT32 FastStrings
:1;
569 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
572 UINT32 AutomaticThermalControlCircuit
:1;
575 /// [Bit 7] Performance Monitoring Available (R).
577 UINT32 PerformanceMonitoring
:1;
580 /// [Bit 11] Branch Trace Storage Unavailable (RO).
584 /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
589 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
594 /// [Bit 18] ENABLE MONITOR FSM (R/W).
599 /// [Bit 22] Limit CPUID Maxval (R/W).
601 UINT32 LimitCpuidMaxval
:1;
603 /// [Bit 23] xTPR Message Disable (R/W).
605 UINT32 xTPR_Message_Disable
:1;
609 /// [Bit 34] XD Bit Disable (R/W).
614 /// [Bit 38] Turbo Mode Disable (R/W).
616 UINT32 TurboModeDisable
:1;
617 UINT32 Reserved10
:25;
620 /// All bit fields as a 64-bit value
623 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
;
629 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
630 @param EAX Lower 32-bits of MSR value.
631 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
632 @param EDX Upper 32-bits of MSR value.
633 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
637 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
639 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
640 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
642 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
644 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
647 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
651 /// Individual bit fields
656 /// [Bits 23:16] Temperature Target (R).
658 UINT32 TemperatureTarget
:8;
660 /// [Bits 29:24] Target Offset (R/W).
662 UINT32 TargetOffset
:6;
667 /// All bit fields as a 32-bit value
671 /// All bit fields as a 64-bit value
674 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
;
678 Miscellaneous Feature Control (R/W).
680 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
681 @param EAX Lower 32-bits of MSR value.
682 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
683 @param EDX Upper 32-bits of MSR value.
684 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
688 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
690 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
691 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
693 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
695 #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
698 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
702 /// Individual bit fields
706 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
707 /// L1 data cache prefetcher.
709 UINT32 DCUHardwarePrefetcherDisable
:1;
711 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
712 /// L2 hardware prefetcher.
714 UINT32 L2HardwarePrefetcherDisable
:1;
719 /// All bit fields as a 32-bit value
723 /// All bit fields as a 64-bit value
726 } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
;
730 Shared. Offcore Response Event Select Register (R/W).
732 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
733 @param EAX Lower 32-bits of MSR value.
734 @param EDX Upper 32-bits of MSR value.
740 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
741 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
743 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
745 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
749 Shared. Offcore Response Event Select Register (R/W).
751 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
752 @param EAX Lower 32-bits of MSR value.
753 @param EDX Upper 32-bits of MSR value.
759 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
760 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
762 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
764 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
768 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
770 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
771 @param EAX Lower 32-bits of MSR value.
772 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
773 @param EDX Upper 32-bits of MSR value.
774 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
778 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
780 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
781 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
783 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
785 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
788 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
792 /// Individual bit fields
797 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
798 /// processor cores which operates under the maximum ratio limit for group
801 UINT32 MaxCoresGroup0
:7;
803 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
804 /// ratio limit when the number of active cores are not more than the
805 /// group 0 maximum core count.
807 UINT32 MaxRatioLimitGroup0
:8;
809 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
810 /// Group 1, which includes the specified number of additional cores plus
811 /// the cores in group 0, operates under the group 1 turbo max ratio limit
812 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
814 UINT32 MaxIncrementalCoresGroup1
:5;
816 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
817 /// integer specifying the ratio decrement relative to the Max ratio limit
820 UINT32 DeltaRatioGroup1
:3;
822 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
823 /// Group 2, which includes the specified number of additional cores plus
824 /// all the cores in group 1, operates under the group 2 turbo max ratio
825 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
827 UINT32 MaxIncrementalCoresGroup2
:5;
829 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
830 /// integer specifying the ratio decrement relative to the Max ratio limit
833 UINT32 DeltaRatioGroup2
:3;
835 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
836 /// Group 3, which includes the specified number of additional cores plus
837 /// all the cores in group 2, operates under the group 3 turbo max ratio
838 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
840 UINT32 MaxIncrementalCoresGroup3
:5;
842 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
843 /// integer specifying the ratio decrement relative to the Max ratio limit
846 UINT32 DeltaRatioGroup3
:3;
848 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
849 /// Group 4, which includes the specified number of additional cores plus
850 /// all the cores in group 3, operates under the group 4 turbo max ratio
851 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
853 UINT32 MaxIncrementalCoresGroup4
:5;
855 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
856 /// integer specifying the ratio decrement relative to the Max ratio limit
859 UINT32 DeltaRatioGroup4
:3;
861 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
862 /// Group 5, which includes the specified number of additional cores plus
863 /// all the cores in group 4, operates under the group 5 turbo max ratio
864 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
866 UINT32 MaxIncrementalCoresGroup5
:5;
868 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
869 /// integer specifying the ratio decrement relative to the Max ratio limit
872 UINT32 DeltaRatioGroup5
:3;
874 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
875 /// Group 6, which includes the specified number of additional cores plus
876 /// all the cores in group 5, operates under the group 6 turbo max ratio
877 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
879 UINT32 MaxIncrementalCoresGroup6
:5;
881 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
882 /// integer specifying the ratio decrement relative to the Max ratio limit
885 UINT32 DeltaRatioGroup6
:3;
888 /// All bit fields as a 64-bit value
891 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
;
895 Thread. Last Branch Record Filtering Select Register (R/W).
897 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
898 @param EAX Lower 32-bits of MSR value.
899 @param EDX Upper 32-bits of MSR value.
905 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
906 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
908 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
910 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8
914 MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
918 /// Individual bit fields
922 /// [Bit 0] CPL_EQ_0.
926 /// [Bit 1] CPL_NEQ_0.
934 /// [Bit 3] NEAR_REL_CALL.
936 UINT32 NEAR_REL_CALL
:1;
938 /// [Bit 4] NEAR_IND_CALL.
940 UINT32 NEAR_IND_CALL
:1;
942 /// [Bit 5] NEAR_RET.
946 /// [Bit 6] NEAR_IND_JMP.
948 UINT32 NEAR_IND_JMP
:1;
950 /// [Bit 7] NEAR_REL_JMP.
952 UINT32 NEAR_REL_JMP
:1;
954 /// [Bit 8] FAR_BRANCH.
961 /// All bit fields as a 32-bit value
965 /// All bit fields as a 64-bit value
968 } MSR_XEON_PHI_LBR_SELECT_REGISTER
;
971 Thread. Last Branch Record Stack TOS (R/W).
973 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
974 @param EAX Lower 32-bits of MSR value.
975 @param EDX Upper 32-bits of MSR value.
981 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
982 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
984 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
986 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
990 Thread. Last Exception Record From Linear IP (R).
992 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
993 @param EAX Lower 32-bits of MSR value.
994 @param EDX Upper 32-bits of MSR value.
1000 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
1002 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
1004 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
1008 Thread. Last Exception Record To Linear IP (R).
1010 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
1011 @param EAX Lower 32-bits of MSR value.
1012 @param EDX Upper 32-bits of MSR value.
1014 <b>Example usage</b>
1018 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
1020 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1022 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
1026 Thread. See Table 2-2.
1028 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
1029 @param EAX Lower 32-bits of MSR value.
1030 @param EDX Upper 32-bits of MSR value.
1032 <b>Example usage</b>
1036 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
1037 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
1039 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1041 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
1045 Package. Note: C-state values are processor specific C-state code names,
1046 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
1047 Residency Counter. (R/O).
1049 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
1050 @param EAX Lower 32-bits of MSR value.
1051 @param EDX Upper 32-bits of MSR value.
1053 <b>Example usage</b>
1057 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
1058 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
1060 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1062 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
1066 Package. Package C6 Residency Counter. (R/O).
1068 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
1069 @param EAX Lower 32-bits of MSR value.
1070 @param EDX Upper 32-bits of MSR value.
1072 <b>Example usage</b>
1076 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
1077 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
1079 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1081 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
1085 Package. Package C7 Residency Counter. (R/O).
1087 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
1088 @param EAX Lower 32-bits of MSR value.
1089 @param EDX Upper 32-bits of MSR value.
1091 <b>Example usage</b>
1095 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
1096 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
1098 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1100 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
1104 Module. Note: C-state values are processor specific C-state code names,
1105 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
1106 Residency Counter. (R/O).
1108 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
1109 @param EAX Lower 32-bits of MSR value.
1110 @param EDX Upper 32-bits of MSR value.
1112 <b>Example usage</b>
1116 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
1117 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
1119 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
1121 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
1125 Module. Module C6 Residency Counter. (R/O).
1127 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
1128 @param EAX Lower 32-bits of MSR value.
1129 @param EDX Upper 32-bits of MSR value.
1131 <b>Example usage</b>
1135 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
1136 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
1138 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
1140 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
1144 Core. Note: C-state values are processor specific C-state code names,
1145 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
1146 Residency Counter. (R/O).
1148 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
1149 @param EAX Lower 32-bits of MSR value.
1150 @param EDX Upper 32-bits of MSR value.
1152 <b>Example usage</b>
1156 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
1157 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
1159 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1161 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
1165 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1167 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1168 @param EAX Lower 32-bits of MSR value.
1169 @param EDX Upper 32-bits of MSR value.
1171 <b>Example usage</b>
1175 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
1177 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1179 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1183 Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
1186 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
1187 @param EAX Lower 32-bits of MSR value.
1188 @param EDX Upper 32-bits of MSR value.
1190 <b>Example usage</b>
1194 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
1196 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1198 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
1202 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1204 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
1205 @param EAX Lower 32-bits of MSR value.
1206 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1207 @param EDX Upper 32-bits of MSR value.
1208 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1210 <b>Example usage</b>
1212 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
1214 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
1216 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1218 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1221 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1225 /// Individual bit fields
1229 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1231 UINT32 PowerUnits
:4;
1234 /// [Bits 12:8] Package. Energy Status Units Energy related information
1235 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1236 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1239 UINT32 EnergyStatusUnits
:5;
1242 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1246 UINT32 Reserved3
:12;
1247 UINT32 Reserved4
:32;
1250 /// All bit fields as a 32-bit value
1254 /// All bit fields as a 64-bit value
1257 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
;
1261 Package. Note: C-state values are processor specific C-state code names,
1262 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1263 Residency Counter. (R/O).
1265 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1266 @param EAX Lower 32-bits of MSR value.
1267 @param EDX Upper 32-bits of MSR value.
1269 <b>Example usage</b>
1273 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1274 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1276 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1278 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1282 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1285 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1286 @param EAX Lower 32-bits of MSR value.
1287 @param EDX Upper 32-bits of MSR value.
1289 <b>Example usage</b>
1293 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1294 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1296 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1298 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1302 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1304 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1305 @param EAX Lower 32-bits of MSR value.
1306 @param EDX Upper 32-bits of MSR value.
1308 <b>Example usage</b>
1312 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1314 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1316 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1320 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1322 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1323 @param EAX Lower 32-bits of MSR value.
1324 @param EDX Upper 32-bits of MSR value.
1326 <b>Example usage</b>
1330 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1332 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1334 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1338 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1341 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1342 @param EAX Lower 32-bits of MSR value.
1343 @param EDX Upper 32-bits of MSR value.
1345 <b>Example usage</b>
1349 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1350 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1352 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1354 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1358 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1361 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1362 @param EAX Lower 32-bits of MSR value.
1363 @param EDX Upper 32-bits of MSR value.
1365 <b>Example usage</b>
1369 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1370 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1372 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1374 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1378 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1380 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1381 @param EAX Lower 32-bits of MSR value.
1382 @param EDX Upper 32-bits of MSR value.
1384 <b>Example usage</b>
1388 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1390 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1392 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1396 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1399 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1400 @param EAX Lower 32-bits of MSR value.
1401 @param EDX Upper 32-bits of MSR value.
1403 <b>Example usage</b>
1407 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1409 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1411 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1415 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1417 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1418 @param EAX Lower 32-bits of MSR value.
1419 @param EDX Upper 32-bits of MSR value.
1421 <b>Example usage</b>
1425 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1426 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1428 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1430 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1434 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
1435 fields represent the widest possible range of uncore frequencies. Writing to
1436 these fields allows software to control the minimum and the maximum
1437 frequency that hardware will select.
1439 @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
1440 @param EAX Lower 32-bits of MSR value.
1441 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1442 @param EDX Upper 32-bits of MSR value.
1443 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1445 <b>Example usage</b>
1447 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
1449 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
1450 AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
1453 #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
1456 MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
1460 /// Individual bit fields
1464 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
1470 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
1471 /// possible ratio of the LLC/Ring.
1474 UINT32 Reserved2
:17;
1475 UINT32 Reserved3
:32;
1478 /// All bit fields as a 32-bit value
1482 /// All bit fields as a 64-bit value
1485 } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
;
1489 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1492 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1493 @param EAX Lower 32-bits of MSR value.
1494 @param EDX Upper 32-bits of MSR value.
1496 <b>Example usage</b>
1500 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1501 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1503 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1505 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1509 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1512 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1513 @param EAX Lower 32-bits of MSR value.
1514 @param EDX Upper 32-bits of MSR value.
1516 <b>Example usage</b>
1520 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1522 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1524 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1528 Package. Base TDP Ratio (R/O) See Table 2-24.
1530 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1531 @param EAX Lower 32-bits of MSR value.
1532 @param EDX Upper 32-bits of MSR value.
1534 <b>Example usage</b>
1538 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1540 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
1542 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1546 Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
1548 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1549 @param EAX Lower 32-bits of MSR value.
1550 @param EDX Upper 32-bits of MSR value.
1552 <b>Example usage</b>
1556 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1558 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
1560 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1564 Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
1566 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1567 @param EAX Lower 32-bits of MSR value.
1568 @param EDX Upper 32-bits of MSR value.
1570 <b>Example usage</b>
1574 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1576 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
1578 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1582 Package. ConfigTDP Control (R/W) See Table 2-24.
1584 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1585 @param EAX Lower 32-bits of MSR value.
1586 @param EDX Upper 32-bits of MSR value.
1588 <b>Example usage</b>
1592 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1593 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1595 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
1597 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1601 Package. ConfigTDP Control (R/W) See Table 2-24.
1603 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1604 @param EAX Lower 32-bits of MSR value.
1605 @param EDX Upper 32-bits of MSR value.
1607 <b>Example usage</b>
1611 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1612 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1614 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1616 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1620 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1621 refers to processor core frequency).
1623 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1624 @param EAX Lower 32-bits of MSR value.
1625 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1626 @param EDX Upper 32-bits of MSR value.
1627 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1629 <b>Example usage</b>
1631 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1633 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1634 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1636 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1638 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1641 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1645 /// Individual bit fields
1649 /// [Bit 0] PROCHOT Status (R0).
1651 UINT32 PROCHOT_Status
:1;
1653 /// [Bit 1] Thermal Status (R0).
1655 UINT32 ThermalStatus
:1;
1658 /// [Bit 6] VR Therm Alert Status (R0).
1660 UINT32 VRThermAlertStatus
:1;
1663 /// [Bit 8] Electrical Design Point Status (R0).
1665 UINT32 ElectricalDesignPointStatus
:1;
1666 UINT32 Reserved3
:23;
1667 UINT32 Reserved4
:32;
1670 /// All bit fields as a 32-bit value
1674 /// All bit fields as a 64-bit value
1677 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
;