UefiCpuPkg/Include/Register/SmramSaveStateMap.h

   1 /** @file
   2 SMRAM Save State Map Definitions.
   3
   4 SMRAM Save State Map definitions based on contents of the
   5 Intel(R) 64 and IA-32 Architectures Software Developer's Manual
   6   Volume 3C, Section 34.4 SMRAM
   7   Volume 3C, Section 34.5 SMI Handler Execution Environment
   8   Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
   9
  10 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
  11 This program and the accompanying materials
  12 are licensed and made available under the terms and conditions of the BSD License
  13 which accompanies this distribution.  The full text of the license may be found at
  14 http://opensource.org/licenses/bsd-license.php
  15
  16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  18
  19 **/
  20
  21 #ifndef __SMRAM_SAVE_STATE_MAP_H__
  22 #define __SMRAM_SAVE_STATE_MAP_H__
  23
  24 ///
  25 /// Default SMBASE address
  26 ///
  27 #define SMM_DEFAULT_SMBASE           0x30000
  28
  29 ///
  30 /// Offset of SMM handler from SMBASE
  31 ///
  32 #define SMM_HANDLER_OFFSET           0x8000
  33
  34 ///
  35 /// Offset of SMRAM Save State Map from SMBASE
  36 ///
  37 #define SMRAM_SAVE_STATE_MAP_OFFSET  0xfc00
  38
  39 #pragma pack (1)
  40
  41 ///
  42 /// 32-bit SMRAM Save State Map
  43 ///
  44 typedef struct {
  45   UINT8   Reserved[0x200];  // 7c00h
  46                             // Padded an extra 0x200 bytes so 32-bit and 64-bit
  47                             // SMRAM Save State Maps are the same size
  48   UINT8   Reserved1[0xf8];  // 7e00h
  49   UINT32  SMBASE;           // 7ef8h
  50   UINT32  SMMRevId;         // 7efch
  51   UINT16  IORestart;        // 7f00h
  52   UINT16  AutoHALTRestart;  // 7f02h
  53   UINT8   Reserved2[0x9C];  // 7f08h
  54   UINT32  IOMemAddr;        // 7fa0h
  55   UINT32  IOMisc;           // 7fa4h
  56   UINT32  _ES;              // 7fa8h
  57   UINT32  _CS;              // 7fach
  58   UINT32  _SS;              // 7fb0h
  59   UINT32  _DS;              // 7fb4h
  60   UINT32  _FS;              // 7fb8h
  61   UINT32  _GS;              // 7fbch
  62   UINT32  Reserved3;        // 7fc0h
  63   UINT32  _TR;              // 7fc4h
  64   UINT32  _DR7;             // 7fc8h
  65   UINT32  _DR6;             // 7fcch
  66   UINT32  _EAX;             // 7fd0h
  67   UINT32  _ECX;             // 7fd4h
  68   UINT32  _EDX;             // 7fd8h
  69   UINT32  _EBX;             // 7fdch
  70   UINT32  _ESP;             // 7fe0h
  71   UINT32  _EBP;             // 7fe4h
  72   UINT32  _ESI;             // 7fe8h
  73   UINT32  _EDI;             // 7fech
  74   UINT32  _EIP;             // 7ff0h
  75   UINT32  _EFLAGS;          // 7ff4h
  76   UINT32  _CR3;             // 7ff8h
  77   UINT32  _CR0;             // 7ffch
  78 } SMRAM_SAVE_STATE_MAP32;
  79
  80 ///
  81 /// 64-bit SMRAM Save State Map
  82 ///
  83 typedef struct {
  84   UINT8   Reserved1[0x1d0];  // 7c00h
  85   UINT32  GdtBaseHiDword;    // 7dd0h
  86   UINT32  LdtBaseHiDword;    // 7dd4h
  87   UINT32  IdtBaseHiDword;    // 7dd8h
  88   UINT8   Reserved2[0xc];    // 7ddch
  89   UINT64  IO_EIP;            // 7de8h
  90   UINT8   Reserved3[0x50];   // 7df0h
  91   UINT32  _CR4;              // 7e40h
  92   UINT8   Reserved4[0x48];   // 7e44h
  93   UINT32  GdtBaseLoDword;    // 7e8ch
  94   UINT32  Reserved5;         // 7e90h
  95   UINT32  IdtBaseLoDword;    // 7e94h
  96   UINT32  Reserved6;         // 7e98h
  97   UINT32  LdtBaseLoDword;    // 7e9ch
  98   UINT8   Reserved7[0x38];   // 7ea0h
  99   UINT64  EptVmxControl;     // 7ed8h
 100   UINT32  EnEptVmxControl;   // 7ee0h
 101   UINT8   Reserved8[0x14];   // 7ee4h
 102   UINT32  SMBASE;            // 7ef8h
 103   UINT32  SMMRevId;          // 7efch
 104   UINT16  IORestart;         // 7f00h
 105   UINT16  AutoHALTRestart;   // 7f02h
 106   UINT8   Reserved9[0x18];   // 7f04h
 107   UINT64  _R15;              // 7f1ch
 108   UINT64  _R14;
 109   UINT64  _R13;
 110   UINT64  _R12;
 111   UINT64  _R11;
 112   UINT64  _R10;
 113   UINT64  _R9;
 114   UINT64  _R8;
 115   UINT64  _RAX;              // 7f5ch
 116   UINT64  _RCX;
 117   UINT64  _RDX;
 118   UINT64  _RBX;
 119   UINT64  _RSP;
 120   UINT64  _RBP;
 121   UINT64  _RSI;
 122   UINT64  _RDI;
 123   UINT64  IOMemAddr;         // 7f9ch
 124   UINT32  IOMisc;            // 7fa4h
 125   UINT32  _ES;               // 7fa8h
 126   UINT32  _CS;
 127   UINT32  _SS;
 128   UINT32  _DS;
 129   UINT32  _FS;
 130   UINT32  _GS;
 131   UINT32  _LDTR;             // 7fc0h
 132   UINT32  _TR;
 133   UINT64  _DR7;              // 7fc8h
 134   UINT64  _DR6;
 135   UINT64  _RIP;              // 7fd8h
 136   UINT64  IA32_EFER;         // 7fe0h
 137   UINT64  _RFLAGS;           // 7fe8h
 138   UINT64  _CR3;              // 7ff0h
 139   UINT64  _CR0;              // 7ff8h
 140 } SMRAM_SAVE_STATE_MAP64;
 141
 142 ///
 143 /// Union of 32-bit and 64-bit SMRAM Save State Maps
 144 ///
 145 typedef union  {
 146   SMRAM_SAVE_STATE_MAP32  x86;
 147   SMRAM_SAVE_STATE_MAP64  x64;
 148 } SMRAM_SAVE_STATE_MAP;
 149
 150 ///
 151 /// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
 152 ///
 153 #define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC  0x30004
 154
 155 ///
 156 /// SMRAM Save State Map IOMisc I/O Length Values
 157 ///
 158 #define  SMM_IO_LENGTH_BYTE             0x01
 159 #define  SMM_IO_LENGTH_WORD             0x02
 160 #define  SMM_IO_LENGTH_DWORD            0x04
 161
 162 ///
 163 /// SMRAM Save State Map IOMisc I/O Instruction Type Values
 164 ///
 165 #define  SMM_IO_TYPE_IN_IMMEDIATE       0x9
 166 #define  SMM_IO_TYPE_IN_DX              0x1
 167 #define  SMM_IO_TYPE_OUT_IMMEDIATE      0x8
 168 #define  SMM_IO_TYPE_OUT_DX             0x0
 169 #define  SMM_IO_TYPE_INS                0x3
 170 #define  SMM_IO_TYPE_OUTS               0x2
 171 #define  SMM_IO_TYPE_REP_INS            0x7
 172 #define  SMM_IO_TYPE_REP_OUTS           0x6
 173
 174 ///
 175 /// SMRAM Save State Map IOMisc structure
 176 ///
 177 typedef union {
 178   struct {
 179     UINT32  SmiFlag:1;
 180     UINT32  Length:3;
 181     UINT32  Type:4;
 182     UINT32  Reserved1:8;
 183     UINT32  Port:16;
 184   } Bits;
 185   UINT32  Uint32;
 186 } SMRAM_SAVE_STATE_IOMISC;
 187
 188 #pragma pack ()
 189
 190 #endif