UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S

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   2 #*
   3 #*   Copyright 2009, Intel Corporation
   4 #*   All rights reserved. This program and the accompanying materials
   5 #*   are licensed and made available under the terms and conditions of the BSD License
   6 #*   which accompanies this distribution.  The full text of the license may be found at
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   9 #*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #*
  12 #*
  13 #------------------------------------------------------------------------------
  14
  15
  16
  17 #
  18 # Float control word initial value:
  19 # all exceptions masked, double-precision, round-to-nearest
  20 #
  21 ASM_PFX(mFpuControlWord): .word     0x027F
  22 #
  23 # Multimedia-extensions control word:
  24 # all exceptions masked, round-to-nearest, flush to zero for masked underflow
  25 #
  26 ASM_PFX(mMmxControlWord): .long     0x01F80
  27
  28 #
  29 # Initializes floating point units for requirement of UEFI specification.
  30 #
  31 # This function initializes floating-point control word to 0x027F (all exceptions
  32 # masked,double-precision, round-to-nearest) and multimedia-extensions control word
  33 # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  34 # for masked underflow).
  35 #
  36 ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
  37 ASM_PFX(InitializeFloatingPointUnits):
  38
  39     pushl   %ebx
  40
  41     #
  42     # Initialize floating point units
  43     #
  44     finit
  45     fldcw   ASM_PFX(mFpuControlWord)
  46
  47     #
  48     # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  49     # whether the processor supports SSE instruction.
  50     #
  51     movl    $1,  %eax
  52     cpuid
  53     btl     $25, %edx
  54     jnc     Done
  55
  56     #
  57     # Set OSFXSR bit 9 in CR4
  58     #
  59     movl    %cr4, %eax
  60     or      $200, %eax
  61     movl    %eax, %cr4
  62
  63     #
  64     # The processor should support SSE instruction and we can use
  65     # ldmxcsr instruction
  66     #
  67     ldmxcsr ASM_PFX(mMmxControlWord)
  68
  69 Done:
  70     popl    %ebx
  71
  72     ret
  73
  74 #END
  75