UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S

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   3 #*   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
   4 #*   This program and the accompanying materials
   5 #*   are licensed and made available under the terms and conditions of the BSD License
   6 #*   which accompanies this distribution.  The full text of the license may be found at
   7 #*   http://opensource.org/licenses/bsd-license.php
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   9 #*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 #*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #*
  12 #*
  13 #------------------------------------------------------------------------------
  14
  15 #
  16 # Float control word initial value:
  17 # all exceptions masked, double-precision, round-to-nearest
  18 #
  19 ASM_PFX(mFpuControlWord): .word     0x027F
  20 #
  21 # Multimedia-extensions control word:
  22 # all exceptions masked, round-to-nearest, flush to zero for masked underflow
  23 #
  24 ASM_PFX(mMmxControlWord): .long     0x01F80
  25
  26 #
  27 # Initializes floating point units for requirement of UEFI specification.
  28 #
  29 # This function initializes floating-point control word to 0x027F (all exceptions
  30 # masked,double-precision, round-to-nearest) and multimedia-extensions control word
  31 # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  32 # for masked underflow).
  33 #
  34 ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
  35 ASM_PFX(InitializeFloatingPointUnits):
  36
  37     pushl   %ebx
  38
  39     #
  40     # Initialize floating point units
  41     #
  42     finit
  43     fldcw   ASM_PFX(mFpuControlWord)
  44
  45     #
  46     # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  47     # whether the processor supports SSE instruction.
  48     #
  49     movl    $1,  %eax
  50     cpuid
  51     btl     $25, %edx
  52     jnc     Done
  53
  54     #
  55     # Set OSFXSR bit 9 in CR4
  56     #
  57     movl    %cr4, %eax
  58     or      $0x200, %eax
  59     movl    %eax, %cr4
  60
  61     #
  62     # The processor should support SSE instruction and we can use
  63     # ldmxcsr instruction
  64     #
  65     ldmxcsr ASM_PFX(mMmxControlWord)
  66
  67 Done:
  68     popl    %ebx
  69
  70     ret
  71
  72 #END
  73