UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.asm

   1 ;------------------------------------------------------------------------------
   2 ;*
   3 ;*   Copyright 2009, Intel Corporation
   4 ;*   All rights reserved. This program and the accompanying materials
   5 ;*   are licensed and made available under the terms and conditions of the BSD License
   6 ;*   which accompanies this distribution.  The full text of the license may be found at
   7 ;*   http://opensource.org/licenses/bsd-license.php
   8 ;*
   9 ;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 ;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 ;*
  12 ;*
  13 ;------------------------------------------------------------------------------
  14
  15
  16     .686
  17     .model  flat,C
  18     .const
  19 ;
  20 ; Float control word initial value:
  21 ; all exceptions masked, double-precision, round-to-nearest
  22 ;
  23 mFpuControlWord       DW      027Fh
  24 ;
  25 ; Multimedia-extensions control word:
  26 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  27 ;
  28 mMmxControlWord       DD      01F80h
  29
  30     .xmm
  31     .code
  32
  33 ;
  34 ; Initializes floating point units for requirement of UEFI specification.
  35 ;
  36 ; This function initializes floating-point control word to 0x027F (all exceptions
  37 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
  38 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  39 ; for masked underflow).
  40 ;
  41 InitializeFloatingPointUnits PROC PUBLIC
  42     ;
  43     ; Initialize floating point units
  44     ;
  45     finit
  46     fldcw   mFpuControlWord
  47
  48     ;
  49     ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  50     ; whether the processor supports SSE instruction.
  51     ;
  52     mov     eax, 1
  53     cpuid
  54     bt      edx, 25
  55     jnc     Done
  56
  57     ;
  58     ; Set OSFXSR bit 9 in CR4
  59     ;
  60     mov     eax, cr4
  61     or      eax, BIT9
  62     mov     cr4, eax
  63
  64     ;
  65     ; The processor should support SSE instruction and we can use
  66     ; ldmxcsr instruction
  67     ;
  68     ldmxcsr mMmxControlWord
  69 Done:
  70
  71     ret
  72
  73 InitializeFloatingPointUnits ENDP
  74
  75 END