UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm

   1 ;------------------------------------------------------------------------------
   2 ;*
   3 ;*   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   4 ;*   This program and the accompanying materials
   5 ;*   are licensed and made available under the terms and conditions of the BSD License
   6 ;*   which accompanies this distribution.  The full text of the license may be found at
   7 ;*   http://opensource.org/licenses/bsd-license.php
   8 ;*
   9 ;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 ;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 ;*
  12 ;*
  13 ;------------------------------------------------------------------------------
  14
  15     SECTION .rdata
  16
  17 ;
  18 ; Float control word initial value:
  19 ; all exceptions masked, double-precision, round-to-nearest
  20 ;
  21 mFpuControlWord: DW 0x27F
  22 ;
  23 ; Multimedia-extensions control word:
  24 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  25 ;
  26 mMmxControlWord: DD 0x1F80
  27
  28     SECTION .text
  29
  30 ;
  31 ; Initializes floating point units for requirement of UEFI specification.
  32 ;
  33 ; This function initializes floating-point control word to 0x027F (all exceptions
  34 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
  35 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  36 ; for masked underflow).
  37 ;
  38 global ASM_PFX(InitializeFloatingPointUnits)
  39 ASM_PFX(InitializeFloatingPointUnits):
  40
  41     push    ebx
  42
  43     ;
  44     ; Initialize floating point units
  45     ;
  46     finit
  47     fldcw   [mFpuControlWord]
  48
  49     ;
  50     ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  51     ; whether the processor supports SSE instruction.
  52     ;
  53     mov     eax, 1
  54     cpuid
  55     bt      edx, 25
  56     jnc     Done
  57
  58     ;
  59     ; Set OSFXSR bit 9 in CR4
  60     ;
  61     mov     eax, cr4
  62     or      eax, BIT9
  63     mov     cr4, eax
  64
  65     ;
  66     ; The processor should support SSE instruction and we can use
  67     ; ldmxcsr instruction
  68     ;
  69     ldmxcsr [mMmxControlWord]
  70 Done:
  71     pop     ebx
  72
  73     ret
  74