UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm

   1 ;------------------------------------------------------------------------------
   2 ;*
   3 ;*   Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   4 ;*   SPDX-License-Identifier: BSD-2-Clause-Patent
   5 ;*
   6 ;*
   7 ;------------------------------------------------------------------------------
   8
   9     SECTION .rodata
  10
  11 ;
  12 ; Float control word initial value:
  13 ; all exceptions masked, double-precision, round-to-nearest
  14 ;
  15 mFpuControlWord: DW 0x27F
  16 ;
  17 ; Multimedia-extensions control word:
  18 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  19 ;
  20 mMmxControlWord: DD 0x1F80
  21
  22     SECTION .text
  23
  24 ;
  25 ; Initializes floating point units for requirement of UEFI specification.
  26 ;
  27 ; This function initializes floating-point control word to 0x027F (all exceptions
  28 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
  29 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  30 ; for masked underflow).
  31 ;
  32 global ASM_PFX(InitializeFloatingPointUnits)
  33 ASM_PFX(InitializeFloatingPointUnits):
  34
  35     push    ebx
  36
  37     ;
  38     ; Initialize floating point units
  39     ;
  40     finit
  41     fldcw   [mFpuControlWord]
  42
  43     ;
  44     ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  45     ; whether the processor supports SSE instruction.
  46     ;
  47     mov     eax, 1
  48     cpuid
  49     bt      edx, 25
  50     jnc     Done
  51
  52     ;
  53     ; Set OSFXSR bit 9 in CR4
  54     ;
  55     mov     eax, cr4
  56     or      eax, BIT9
  57     mov     cr4, eax
  58
  59     ;
  60     ; The processor should support SSE instruction and we can use
  61     ; ldmxcsr instruction
  62     ;
  63     ldmxcsr [mMmxControlWord]
  64 Done:
  65     pop     ebx
  66
  67     ret
  68