UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm

   1 ;------------------------------------------------------------------------------
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   3 ;*   Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
   4 ;*   This program and the accompanying materials
   5 ;*   are licensed and made available under the terms and conditions of the BSD License
   6 ;*   which accompanies this distribution.  The full text of the license may be found at
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   9 ;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 ;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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  12 ;*
  13 ;------------------------------------------------------------------------------
  14
  15     SECTION .rodata
  16 ;
  17 ; Float control word initial value:
  18 ; all exceptions masked, double-extended-precision, round-to-nearest
  19 ;
  20 mFpuControlWord: DW 0x37F
  21 ;
  22 ; Multimedia-extensions control word:
  23 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
  24 ;
  25 mMmxControlWord: DD 0x1F80
  26
  27 DEFAULT REL
  28 SECTION .text
  29
  30 ;
  31 ; Initializes floating point units for requirement of UEFI specification.
  32 ;
  33 ; This function initializes floating-point control word to 0x027F (all exceptions
  34 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
  35 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  36 ; for masked underflow).
  37 ;
  38 global ASM_PFX(InitializeFloatingPointUnits)
  39 ASM_PFX(InitializeFloatingPointUnits):
  40
  41     ;
  42     ; Initialize floating point units
  43     ;
  44     finit
  45     fldcw   [mFpuControlWord]
  46
  47     ;
  48     ; Set OSFXSR bit 9 in CR4
  49     ;
  50     mov     rax, cr4
  51     or      rax, BIT9
  52     mov     cr4, rax
  53
  54     ldmxcsr [mMmxControlWord]
  55
  56     ret
  57