UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c

   1 /** @file
   2   Local APIC Library.
   3
   4   This local APIC library instance supports xAPIC mode only.
   5
   6   Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include <Register/LocalApic.h>
  18
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/LocalApicLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/TimerLib.h>
  24 #include <Library/PcdLib.h>
  25
  26 //
  27 // Library internal functions
  28 //
  29
  30 /**
  31   Read from a local APIC register.
  32
  33   This function reads from a local APIC register either in xAPIC or x2APIC mode.
  34   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  35   accessed using multiple 32-bit loads or stores, so this function only performs
  36   32-bit read.
  37
  38   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
  39                       It must be 16-byte aligned.
  40
  41   @return 32-bit      Value read from the register.
  42 **/
  43 UINT32
  44 EFIAPI
  45 ReadLocalApicReg (
  46   IN UINTN  MmioOffset
  47   )
  48 {
  49   ASSERT ((MmioOffset & 0xf) == 0);
  50   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  51
  52   return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
  53 }
  54
  55 /**
  56   Write to a local APIC register.
  57
  58   This function writes to a local APIC register either in xAPIC or x2APIC mode.
  59   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  60   accessed using multiple 32-bit loads or stores, so this function only performs
  61   32-bit write.
  62
  63   if the register index is invalid or unsupported in current APIC mode, then ASSERT.
  64
  65   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
  66                       It must be 16-byte aligned.
  67   @param  Value       Value to be written to the register.
  68 **/
  69 VOID
  70 EFIAPI
  71 WriteLocalApicReg (
  72   IN UINTN  MmioOffset,
  73   IN UINT32 Value
  74   )
  75 {
  76   ASSERT ((MmioOffset & 0xf) == 0);
  77   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  78
  79   MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
  80 }
  81
  82 /**
  83   Send an IPI by writing to ICR.
  84
  85   This function returns after the IPI has been accepted by the target processor.
  86
  87   @param  IcrLow 32-bit value to be written to the low half of ICR.
  88   @param  ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
  89 **/
  90 VOID
  91 SendIpi (
  92   IN UINT32          IcrLow,
  93   IN UINT32          ApicId
  94   )
  95 {
  96   LOCAL_APIC_ICR_LOW IcrLowReg;
  97
  98   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  99   ASSERT (ApicId <= 0xff);
 100
 101   //
 102   // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
 103   //
 104   WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
 105   WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
 106   do {
 107     IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
 108   } while (IcrLowReg.Bits.DeliveryStatus != 0);
 109 }
 110
 111 //
 112 // Library API implementation functions
 113 //
 114
 115 /**
 116   Get the current local APIC mode.
 117
 118   If local APIC is disabled, then ASSERT.
 119
 120   @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.
 121   @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
 122 **/
 123 UINTN
 124 EFIAPI
 125 GetApicMode (
 126   VOID
 127   )
 128 {
 129   DEBUG_CODE (
 130     {
 131       MSR_IA32_APIC_BASE ApicBaseMsr;
 132
 133       ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 134       //
 135       // Local APIC should have been enabled
 136       //
 137       ASSERT (ApicBaseMsr.Bits.En != 0);
 138       ASSERT (ApicBaseMsr.Bits.Extd == 0);
 139     }
 140   );
 141   return LOCAL_APIC_MODE_XAPIC;
 142 }
 143
 144 /**
 145   Set the current local APIC mode.
 146
 147   If the specified local APIC mode is not valid, then ASSERT.
 148   If the specified local APIC mode can't be set as current, then ASSERT.
 149
 150   @param ApicMode APIC mode to be set.
 151 **/
 152 VOID
 153 EFIAPI
 154 SetApicMode (
 155   IN UINTN  ApicMode
 156   )
 157 {
 158   ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
 159   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 160 }
 161
 162 /**
 163   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
 164
 165   In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
 166   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
 167   the 32-bit local APIC ID is returned as initial APIC ID.
 168
 169   @return  32-bit initial local APIC ID of the executing processor.
 170 **/
 171 UINT32
 172 EFIAPI
 173 GetInitialApicId (
 174   VOID
 175   )
 176 {
 177   UINT32 RegEbx;
 178
 179   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 180
 181   AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
 182   return RegEbx >> 24;
 183 }
 184
 185 /**
 186   Get the local APIC ID of the executing processor.
 187
 188   @return  32-bit local APIC ID of the executing processor.
 189 **/
 190 UINT32
 191 EFIAPI
 192 GetApicId (
 193   VOID
 194   )
 195 {
 196   UINT32 ApicId;
 197
 198   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 199
 200   ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
 201   ApicId >>= 24;
 202   return ApicId;
 203 }
 204
 205 /**
 206   Send a SMI IPI to a specified target processor.
 207
 208   This function returns after the IPI has been accepted by the target processor.
 209
 210   @param  ApicId   Specify the local APIC ID of the target processor.
 211 **/
 212 VOID
 213 EFIAPI
 214 SendSmiIpi (
 215   IN UINT32          ApicId
 216   )
 217 {
 218   LOCAL_APIC_ICR_LOW IcrLow;
 219
 220   IcrLow.Uint32 = 0;
 221   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 222   IcrLow.Bits.Level = 1;
 223   SendIpi (IcrLow.Uint32, ApicId);
 224 }
 225
 226 /**
 227   Send a SMI IPI to all processors excluding self.
 228
 229   This function returns after the IPI has been accepted by the target processors.
 230 **/
 231 VOID
 232 EFIAPI
 233 SendSmiIpiAllExcludingSelf (
 234   VOID
 235   )
 236 {
 237   LOCAL_APIC_ICR_LOW IcrLow;
 238
 239   IcrLow.Uint32 = 0;
 240   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 241   IcrLow.Bits.Level = 1;
 242   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 243   SendIpi (IcrLow.Uint32, 0);
 244 }
 245
 246 /**
 247   Send an INIT IPI to a specified target processor.
 248
 249   This function returns after the IPI has been accepted by the target processor.
 250
 251   @param  ApicId   Specify the local APIC ID of the target processor.
 252 **/
 253 VOID
 254 EFIAPI
 255 SendInitIpi (
 256   IN UINT32          ApicId
 257   )
 258 {
 259   LOCAL_APIC_ICR_LOW IcrLow;
 260
 261   IcrLow.Uint32 = 0;
 262   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 263   IcrLow.Bits.Level = 1;
 264   SendIpi (IcrLow.Uint32, ApicId);
 265 }
 266
 267 /**
 268   Send an INIT IPI to all processors excluding self.
 269
 270   This function returns after the IPI has been accepted by the target processors.
 271 **/
 272 VOID
 273 EFIAPI
 274 SendInitIpiAllExcludingSelf (
 275   VOID
 276   )
 277 {
 278   LOCAL_APIC_ICR_LOW IcrLow;
 279
 280   IcrLow.Uint32 = 0;
 281   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 282   IcrLow.Bits.Level = 1;
 283   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 284   SendIpi (IcrLow.Uint32, 0);
 285 }
 286
 287 /**
 288   Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
 289
 290   This function returns after the IPI has been accepted by the target processor.
 291
 292   if StartupRoutine >= 1M, then ASSERT.
 293   if StartupRoutine is not multiple of 4K, then ASSERT.
 294
 295   @param  ApicId          Specify the local APIC ID of the target processor.
 296   @param  StartupRoutine  Points to a start-up routine which is below 1M physical
 297                           address and 4K aligned.
 298 **/
 299 VOID
 300 EFIAPI
 301 SendInitSipiSipi (
 302   IN UINT32          ApicId,
 303   IN UINT32          StartupRoutine
 304   )
 305 {
 306   LOCAL_APIC_ICR_LOW IcrLow;
 307
 308   ASSERT (StartupRoutine < 0x100000);
 309   ASSERT ((StartupRoutine & 0xfff) == 0);
 310
 311   SendInitIpi (ApicId);
 312   MicroSecondDelay (10);
 313   IcrLow.Uint32 = 0;
 314   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 315   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 316   IcrLow.Bits.Level = 1;
 317   SendIpi (IcrLow.Uint32, ApicId);
 318   MicroSecondDelay (200);
 319   SendIpi (IcrLow.Uint32, ApicId);
 320 }
 321
 322 /**
 323   Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
 324
 325   This function returns after the IPI has been accepted by the target processors.
 326
 327   if StartupRoutine >= 1M, then ASSERT.
 328   if StartupRoutine is not multiple of 4K, then ASSERT.
 329
 330   @param  StartupRoutine    Points to a start-up routine which is below 1M physical
 331                             address and 4K aligned.
 332 **/
 333 VOID
 334 EFIAPI
 335 SendInitSipiSipiAllExcludingSelf (
 336   IN UINT32          StartupRoutine
 337   )
 338 {
 339   LOCAL_APIC_ICR_LOW IcrLow;
 340
 341   ASSERT (StartupRoutine < 0x100000);
 342   ASSERT ((StartupRoutine & 0xfff) == 0);
 343
 344   SendInitIpiAllExcludingSelf ();
 345   MicroSecondDelay (10);
 346   IcrLow.Uint32 = 0;
 347   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 348   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 349   IcrLow.Bits.Level = 1;
 350   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 351   SendIpi (IcrLow.Uint32, 0);
 352   MicroSecondDelay (200);
 353   SendIpi (IcrLow.Uint32, 0);
 354 }
 355
 356 /**
 357   Programming Virtual Wire Mode.
 358
 359   This function programs the local APIC for virtual wire mode following
 360   the example described in chapter A.3 of the MP 1.4 spec.
 361
 362   IOxAPIC is not involved in this type of virtual wire mode.
 363 **/
 364 VOID
 365 EFIAPI
 366 ProgramVirtualWireMode (
 367   VOID
 368   )
 369 {
 370   LOCAL_APIC_SVR      Svr;
 371   LOCAL_APIC_LVT_LINT Lint;
 372
 373   //
 374   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
 375   //
 376   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 377   Svr.Bits.SpuriousVector = 0xf;
 378   Svr.Bits.SoftwareEnable = 1;
 379   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 380
 381   //
 382   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
 383   //
 384   Lint.Uint32 = ReadLocalApicReg (XAPIC_LINT0_VECTOR_OFFSET);
 385   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
 386   Lint.Bits.InputPinPolarity = 0;
 387   Lint.Bits.TriggerMode = 0;
 388   Lint.Bits.Mask = 0;
 389   WriteLocalApicReg (XAPIC_LINT0_VECTOR_OFFSET, Lint.Uint32);
 390
 391   //
 392   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
 393   //
 394   Lint.Uint32 = ReadLocalApicReg (XAPIC_LINT1_VECTOR_OFFSET);
 395   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
 396   Lint.Bits.InputPinPolarity = 0;
 397   Lint.Bits.TriggerMode = 0;
 398   Lint.Bits.Mask = 0;
 399   WriteLocalApicReg (XAPIC_LINT1_VECTOR_OFFSET, Lint.Uint32);
 400 }
 401
 402 /**
 403   Get the divide value from the DCR (Divide Configuration Register) by which
 404   the processor's bus clock is divided to form the time base for the APIC timer.
 405
 406   @return The divide value is one of 1,2,4,8,16,32,64,128.
 407 **/
 408 UINTN
 409 EFIAPI
 410 GetApicTimerDivisor (
 411   VOID
 412   )
 413 {
 414   UINT32         DivideValue;
 415   LOCAL_APIC_DCR Dcr;
 416
 417   Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 418   DivideValue = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
 419   DivideValue = (DivideValue + 1) & 0x7;
 420   return ((UINTN)1) << DivideValue;
 421 }
 422
 423 /**
 424   Read the initial count value from the init-count register.
 425
 426   @return The initial count value read from the init-count register.
 427 **/
 428 UINT32
 429 EFIAPI
 430 GetApicTimerInitCount (
 431   VOID
 432   )
 433 {
 434   return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
 435 }
 436
 437 /**
 438   Read the current count value from the current-count register.
 439
 440   @return The current count value read from the current-count register.
 441 **/
 442 UINT32
 443 EFIAPI
 444 GetApicTimerCurrentCount (
 445   VOID
 446   )
 447 {
 448   return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
 449 }
 450
 451 /**
 452   Initialize the local APIC timer.
 453
 454   The local APIC timer is initialized and enabled.
 455
 456   @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 457                        If it is 0, then use the current divide value in the DCR.
 458   @param InitCount     The initial count value.
 459   @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 460   @param Vector        The timer interrupt vector number.
 461 **/
 462 VOID
 463 EFIAPI
 464 InitializeApicTimer (
 465   IN UINTN   DivideValue,
 466   IN UINT32  InitCount,
 467   IN BOOLEAN PeriodicMode,
 468   IN UINT8   Vector
 469   )
 470 {
 471   LOCAL_APIC_SVR       Svr;
 472   LOCAL_APIC_DCR       Dcr;
 473   LOCAL_APIC_LVT_TIMER LvtTimer;
 474   UINT32               Divisor;
 475
 476   //
 477   // Ensure local APIC is in software-enabled state.
 478   //
 479   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 480   Svr.Bits.SoftwareEnable = 1;
 481   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 482
 483   //
 484   // Program init-count register.
 485   //
 486   WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
 487
 488   if (DivideValue != 0) {
 489     ASSERT (DivideValue <= 128);
 490     ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
 491     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
 492
 493     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 494     Dcr.Bits.DivideValue1 = (Divisor & 0x3);
 495     Dcr.Bits.DivideValue2 = (Divisor >> 2);
 496     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
 497   }
 498
 499   //
 500   // Enable APIC timer interrupt with specified timer mode.
 501   //
 502   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 503   if (PeriodicMode) {
 504     LvtTimer.Bits.TimerMode = 1;
 505   } else {
 506     LvtTimer.Bits.TimerMode = 0;
 507   }
 508   LvtTimer.Bits.Mask = 0;
 509   LvtTimer.Bits.Vector = Vector;
 510   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 511 }
 512
 513 /**
 514   Enable the local APIC timer interrupt.
 515 **/
 516 VOID
 517 EFIAPI
 518 EnableApicTimerInterrupt (
 519   VOID
 520   )
 521 {
 522   LOCAL_APIC_LVT_TIMER LvtTimer;
 523
 524   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 525   LvtTimer.Bits.Mask = 0;
 526   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 527 }
 528
 529 /**
 530   Disable the local APIC timer interrupt.
 531 **/
 532 VOID
 533 EFIAPI
 534 DisableApicTimerInterrupt (
 535   VOID
 536   )
 537 {
 538   LOCAL_APIC_LVT_TIMER LvtTimer;
 539
 540   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 541   LvtTimer.Bits.Mask = 1;
 542   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 543 }
 544
 545 /**
 546   Get the local APIC timer interrupt state.
 547
 548   @retval TRUE  The local APIC timer interrupt is enabled.
 549   @retval FALSE The local APIC timer interrupt is disabled.
 550 **/
 551 BOOLEAN
 552 EFIAPI
 553 GetApicTimerInterruptState (
 554   VOID
 555   )
 556 {
 557   LOCAL_APIC_LVT_TIMER LvtTimer;
 558
 559   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 560   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
 561 }
 562
 563 /**
 564   Send EOI to the local APIC.
 565 **/
 566 VOID
 567 EFIAPI
 568 SendApicEoi (
 569   VOID
 570   )
 571 {
 572   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
 573 }
 574