UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c

   1 /** @file
   2   Local APIC Library.
   3
   4   This local APIC library instance supports xAPIC mode only.
   5
   6   Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include <Register/Cpuid.h>
  18 #include <Register/LocalApic.h>
  19
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/LocalApicLib.h>
  23 #include <Library/IoLib.h>
  24 #include <Library/TimerLib.h>
  25 #include <Library/PcdLib.h>
  26
  27 //
  28 // Library internal functions
  29 //
  30
  31 /**
  32   Determine if the CPU supports the Local APIC Base Address MSR.
  33
  34   @retval TRUE  The CPU supports the Local APIC Base Address MSR.
  35   @retval FALSE The CPU does not support the Local APIC Base Address MSR.
  36
  37 **/
  38 BOOLEAN
  39 LocalApicBaseAddressMsrSupported (
  40   VOID
  41   )
  42 {
  43   UINT32  RegEax;
  44   UINTN   FamilyId;
  45
  46   AsmCpuid (1, &RegEax, NULL, NULL, NULL);
  47   FamilyId = BitFieldRead32 (RegEax, 8, 11);
  48   if (FamilyId == 0x04 || FamilyId == 0x05) {
  49     //
  50     // CPUs with a FamilyId of 0x04 or 0x05 do not support the
  51     // Local APIC Base Address MSR
  52     //
  53     return FALSE;
  54   }
  55   return TRUE;
  56 }
  57
  58 /**
  59   Retrieve the base address of local APIC.
  60
  61   @return The base address of local APIC.
  62
  63 **/
  64 UINTN
  65 EFIAPI
  66 GetLocalApicBaseAddress (
  67   VOID
  68   )
  69 {
  70   MSR_IA32_APIC_BASE  ApicBaseMsr;
  71
  72   if (!LocalApicBaseAddressMsrSupported ()) {
  73     //
  74     // If CPU does not support Local APIC Base Address MSR, then retrieve
  75     // Local APIC Base Address from PCD
  76     //
  77     return PcdGet32 (PcdCpuLocalApicBaseAddress);
  78   }
  79
  80   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  81
  82   return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
  83            (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
  84 }
  85
  86 /**
  87   Set the base address of local APIC.
  88
  89   If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
  90
  91   @param[in] BaseAddress   Local APIC base address to be set.
  92
  93 **/
  94 VOID
  95 EFIAPI
  96 SetLocalApicBaseAddress (
  97   IN UINTN                BaseAddress
  98   )
  99 {
 100   MSR_IA32_APIC_BASE  ApicBaseMsr;
 101
 102   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
 103
 104   if (!LocalApicBaseAddressMsrSupported ()) {
 105     //
 106     // Ignore set request if the CPU does not support APIC Base Address MSR
 107     //
 108     return;
 109   }
 110
 111   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 112
 113   ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
 114   ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
 115
 116   AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
 117 }
 118
 119 /**
 120   Read from a local APIC register.
 121
 122   This function reads from a local APIC register either in xAPIC or x2APIC mode.
 123   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
 124   accessed using multiple 32-bit loads or stores, so this function only performs
 125   32-bit read.
 126
 127   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
 128                       It must be 16-byte aligned.
 129
 130   @return 32-bit      Value read from the register.
 131 **/
 132 UINT32
 133 EFIAPI
 134 ReadLocalApicReg (
 135   IN UINTN  MmioOffset
 136   )
 137 {
 138   ASSERT ((MmioOffset & 0xf) == 0);
 139   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 140
 141   return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
 142 }
 143
 144 /**
 145   Write to a local APIC register.
 146
 147   This function writes to a local APIC register either in xAPIC or x2APIC mode.
 148   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
 149   accessed using multiple 32-bit loads or stores, so this function only performs
 150   32-bit write.
 151
 152   if the register index is invalid or unsupported in current APIC mode, then ASSERT.
 153
 154   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
 155                       It must be 16-byte aligned.
 156   @param  Value       Value to be written to the register.
 157 **/
 158 VOID
 159 EFIAPI
 160 WriteLocalApicReg (
 161   IN UINTN  MmioOffset,
 162   IN UINT32 Value
 163   )
 164 {
 165   ASSERT ((MmioOffset & 0xf) == 0);
 166   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 167
 168   MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
 169 }
 170
 171 /**
 172   Send an IPI by writing to ICR.
 173
 174   This function returns after the IPI has been accepted by the target processor.
 175
 176   @param  IcrLow 32-bit value to be written to the low half of ICR.
 177   @param  ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
 178 **/
 179 VOID
 180 SendIpi (
 181   IN UINT32          IcrLow,
 182   IN UINT32          ApicId
 183   )
 184 {
 185   LOCAL_APIC_ICR_LOW IcrLowReg;
 186   UINT32             IcrHigh;
 187   BOOLEAN            InterruptState;
 188
 189   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 190   ASSERT (ApicId <= 0xff);
 191
 192   InterruptState = SaveAndDisableInterrupts ();
 193
 194   //
 195   // Save existing contents of ICR high 32 bits
 196   //
 197   IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);
 198
 199   //
 200   // Wait for DeliveryStatus clear in case a previous IPI
 201   //  is still being sent
 202   //
 203   do {
 204     IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
 205   } while (IcrLowReg.Bits.DeliveryStatus != 0);
 206
 207   //
 208   // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
 209   //
 210   WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
 211   WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
 212
 213   //
 214   // Wait for DeliveryStatus clear again
 215   //
 216   do {
 217     IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
 218   } while (IcrLowReg.Bits.DeliveryStatus != 0);
 219
 220   //
 221   // And restore old contents of ICR high
 222   //
 223   WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
 224
 225   SetInterruptState (InterruptState);
 226
 227 }
 228
 229 //
 230 // Library API implementation functions
 231 //
 232
 233 /**
 234   Get the current local APIC mode.
 235
 236   If local APIC is disabled, then ASSERT.
 237
 238   @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.
 239   @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
 240 **/
 241 UINTN
 242 EFIAPI
 243 GetApicMode (
 244   VOID
 245   )
 246 {
 247   DEBUG_CODE (
 248     {
 249       MSR_IA32_APIC_BASE  ApicBaseMsr;
 250
 251       //
 252       // Check to see if the CPU supports the APIC Base Address MSR
 253       //
 254       if (LocalApicBaseAddressMsrSupported ()) {
 255         ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 256         //
 257         // Local APIC should have been enabled
 258         //
 259         ASSERT (ApicBaseMsr.Bits.En != 0);
 260         ASSERT (ApicBaseMsr.Bits.Extd == 0);
 261       }
 262     }
 263   );
 264   return LOCAL_APIC_MODE_XAPIC;
 265 }
 266
 267 /**
 268   Set the current local APIC mode.
 269
 270   If the specified local APIC mode is not valid, then ASSERT.
 271   If the specified local APIC mode can't be set as current, then ASSERT.
 272
 273   @param ApicMode APIC mode to be set.
 274
 275   @note  This API must not be called from an interrupt handler or SMI handler.
 276          It may result in unpredictable behavior.
 277 **/
 278 VOID
 279 EFIAPI
 280 SetApicMode (
 281   IN UINTN  ApicMode
 282   )
 283 {
 284   ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
 285   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 286 }
 287
 288 /**
 289   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
 290
 291   In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
 292   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
 293   the 32-bit local APIC ID is returned as initial APIC ID.
 294
 295   @return  32-bit initial local APIC ID of the executing processor.
 296 **/
 297 UINT32
 298 EFIAPI
 299 GetInitialApicId (
 300   VOID
 301   )
 302 {
 303   UINT32 ApicId;
 304   UINT32 MaxCpuIdIndex;
 305   UINT32 RegEbx;
 306
 307   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 308
 309   //
 310   // Get the max index of basic CPUID
 311   //
 312   AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
 313
 314   //
 315   // If CPUID Leaf B is supported,
 316   // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
 317   // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
 318   //
 319   if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
 320     AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
 321     return ApicId;
 322   }
 323
 324   AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
 325   return RegEbx >> 24;
 326 }
 327
 328 /**
 329   Get the local APIC ID of the executing processor.
 330
 331   @return  32-bit local APIC ID of the executing processor.
 332 **/
 333 UINT32
 334 EFIAPI
 335 GetApicId (
 336   VOID
 337   )
 338 {
 339   UINT32 ApicId;
 340
 341   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 342
 343   if ((ApicId = GetInitialApicId ()) < 0x100) {
 344     //
 345     // If the initial local APIC ID is less 0x100, read APIC ID from
 346     // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
 347     //
 348     ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
 349     ApicId >>= 24;
 350   }
 351   return ApicId;
 352 }
 353
 354 /**
 355   Get the value of the local APIC version register.
 356
 357   @return  the value of the local APIC version register.
 358 **/
 359 UINT32
 360 EFIAPI
 361 GetApicVersion (
 362   VOID
 363   )
 364 {
 365   return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
 366 }
 367
 368 /**
 369   Send a Fixed IPI to a specified target processor.
 370
 371   This function returns after the IPI has been accepted by the target processor.
 372
 373   @param  ApicId   The local APIC ID of the target processor.
 374   @param  Vector   The vector number of the interrupt being sent.
 375 **/
 376 VOID
 377 EFIAPI
 378 SendFixedIpi (
 379   IN UINT32          ApicId,
 380   IN UINT8           Vector
 381   )
 382 {
 383   LOCAL_APIC_ICR_LOW IcrLow;
 384
 385   IcrLow.Uint32 = 0;
 386   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 387   IcrLow.Bits.Level = 1;
 388   IcrLow.Bits.Vector = Vector;
 389   SendIpi (IcrLow.Uint32, ApicId);
 390 }
 391
 392 /**
 393   Send a Fixed IPI to all processors excluding self.
 394
 395   This function returns after the IPI has been accepted by the target processors.
 396
 397   @param  Vector   The vector number of the interrupt being sent.
 398 **/
 399 VOID
 400 EFIAPI
 401 SendFixedIpiAllExcludingSelf (
 402   IN UINT8           Vector
 403   )
 404 {
 405   LOCAL_APIC_ICR_LOW IcrLow;
 406
 407   IcrLow.Uint32 = 0;
 408   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 409   IcrLow.Bits.Level = 1;
 410   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 411   IcrLow.Bits.Vector = Vector;
 412   SendIpi (IcrLow.Uint32, 0);
 413 }
 414
 415 /**
 416   Send a SMI IPI to a specified target processor.
 417
 418   This function returns after the IPI has been accepted by the target processor.
 419
 420   @param  ApicId   Specify the local APIC ID of the target processor.
 421 **/
 422 VOID
 423 EFIAPI
 424 SendSmiIpi (
 425   IN UINT32          ApicId
 426   )
 427 {
 428   LOCAL_APIC_ICR_LOW IcrLow;
 429
 430   IcrLow.Uint32 = 0;
 431   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 432   IcrLow.Bits.Level = 1;
 433   SendIpi (IcrLow.Uint32, ApicId);
 434 }
 435
 436 /**
 437   Send a SMI IPI to all processors excluding self.
 438
 439   This function returns after the IPI has been accepted by the target processors.
 440 **/
 441 VOID
 442 EFIAPI
 443 SendSmiIpiAllExcludingSelf (
 444   VOID
 445   )
 446 {
 447   LOCAL_APIC_ICR_LOW IcrLow;
 448
 449   IcrLow.Uint32 = 0;
 450   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 451   IcrLow.Bits.Level = 1;
 452   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 453   SendIpi (IcrLow.Uint32, 0);
 454 }
 455
 456 /**
 457   Send an INIT IPI to a specified target processor.
 458
 459   This function returns after the IPI has been accepted by the target processor.
 460
 461   @param  ApicId   Specify the local APIC ID of the target processor.
 462 **/
 463 VOID
 464 EFIAPI
 465 SendInitIpi (
 466   IN UINT32          ApicId
 467   )
 468 {
 469   LOCAL_APIC_ICR_LOW IcrLow;
 470
 471   IcrLow.Uint32 = 0;
 472   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 473   IcrLow.Bits.Level = 1;
 474   SendIpi (IcrLow.Uint32, ApicId);
 475 }
 476
 477 /**
 478   Send an INIT IPI to all processors excluding self.
 479
 480   This function returns after the IPI has been accepted by the target processors.
 481 **/
 482 VOID
 483 EFIAPI
 484 SendInitIpiAllExcludingSelf (
 485   VOID
 486   )
 487 {
 488   LOCAL_APIC_ICR_LOW IcrLow;
 489
 490   IcrLow.Uint32 = 0;
 491   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 492   IcrLow.Bits.Level = 1;
 493   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 494   SendIpi (IcrLow.Uint32, 0);
 495 }
 496
 497 /**
 498   Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
 499
 500   This function returns after the IPI has been accepted by the target processor.
 501
 502   if StartupRoutine >= 1M, then ASSERT.
 503   if StartupRoutine is not multiple of 4K, then ASSERT.
 504
 505   @param  ApicId          Specify the local APIC ID of the target processor.
 506   @param  StartupRoutine  Points to a start-up routine which is below 1M physical
 507                           address and 4K aligned.
 508 **/
 509 VOID
 510 EFIAPI
 511 SendInitSipiSipi (
 512   IN UINT32          ApicId,
 513   IN UINT32          StartupRoutine
 514   )
 515 {
 516   LOCAL_APIC_ICR_LOW IcrLow;
 517
 518   ASSERT (StartupRoutine < 0x100000);
 519   ASSERT ((StartupRoutine & 0xfff) == 0);
 520
 521   SendInitIpi (ApicId);
 522   MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
 523   IcrLow.Uint32 = 0;
 524   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 525   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 526   IcrLow.Bits.Level = 1;
 527   SendIpi (IcrLow.Uint32, ApicId);
 528   MicroSecondDelay (200);
 529   SendIpi (IcrLow.Uint32, ApicId);
 530 }
 531
 532 /**
 533   Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
 534
 535   This function returns after the IPI has been accepted by the target processors.
 536
 537   if StartupRoutine >= 1M, then ASSERT.
 538   if StartupRoutine is not multiple of 4K, then ASSERT.
 539
 540   @param  StartupRoutine    Points to a start-up routine which is below 1M physical
 541                             address and 4K aligned.
 542 **/
 543 VOID
 544 EFIAPI
 545 SendInitSipiSipiAllExcludingSelf (
 546   IN UINT32          StartupRoutine
 547   )
 548 {
 549   LOCAL_APIC_ICR_LOW IcrLow;
 550
 551   ASSERT (StartupRoutine < 0x100000);
 552   ASSERT ((StartupRoutine & 0xfff) == 0);
 553
 554   SendInitIpiAllExcludingSelf ();
 555   MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
 556   IcrLow.Uint32 = 0;
 557   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 558   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 559   IcrLow.Bits.Level = 1;
 560   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 561   SendIpi (IcrLow.Uint32, 0);
 562   MicroSecondDelay (200);
 563   SendIpi (IcrLow.Uint32, 0);
 564 }
 565
 566 /**
 567   Programming Virtual Wire Mode.
 568
 569   This function programs the local APIC for virtual wire mode following
 570   the example described in chapter A.3 of the MP 1.4 spec.
 571
 572   IOxAPIC is not involved in this type of virtual wire mode.
 573 **/
 574 VOID
 575 EFIAPI
 576 ProgramVirtualWireMode (
 577   VOID
 578   )
 579 {
 580   LOCAL_APIC_SVR      Svr;
 581   LOCAL_APIC_LVT_LINT Lint;
 582
 583   //
 584   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
 585   //
 586   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 587   Svr.Bits.SpuriousVector = 0xf;
 588   Svr.Bits.SoftwareEnable = 1;
 589   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 590
 591   //
 592   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
 593   //
 594   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 595   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
 596   Lint.Bits.InputPinPolarity = 0;
 597   Lint.Bits.TriggerMode = 0;
 598   Lint.Bits.Mask = 0;
 599   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
 600
 601   //
 602   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
 603   //
 604   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 605   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
 606   Lint.Bits.InputPinPolarity = 0;
 607   Lint.Bits.TriggerMode = 0;
 608   Lint.Bits.Mask = 0;
 609   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
 610 }
 611
 612 /**
 613   Disable LINT0 & LINT1 interrupts.
 614
 615   This function sets the mask flag in the LVT LINT0 & LINT1 registers.
 616 **/
 617 VOID
 618 EFIAPI
 619 DisableLvtInterrupts (
 620   VOID
 621   )
 622 {
 623   LOCAL_APIC_LVT_LINT LvtLint;
 624
 625   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 626   LvtLint.Bits.Mask = 1;
 627   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
 628
 629   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 630   LvtLint.Bits.Mask = 1;
 631   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
 632 }
 633
 634 /**
 635   Read the initial count value from the init-count register.
 636
 637   @return The initial count value read from the init-count register.
 638 **/
 639 UINT32
 640 EFIAPI
 641 GetApicTimerInitCount (
 642   VOID
 643   )
 644 {
 645   return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
 646 }
 647
 648 /**
 649   Read the current count value from the current-count register.
 650
 651   @return The current count value read from the current-count register.
 652 **/
 653 UINT32
 654 EFIAPI
 655 GetApicTimerCurrentCount (
 656   VOID
 657   )
 658 {
 659   return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
 660 }
 661
 662 /**
 663   Initialize the local APIC timer.
 664
 665   The local APIC timer is initialized and enabled.
 666
 667   @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 668                        If it is 0, then use the current divide value in the DCR.
 669   @param InitCount     The initial count value.
 670   @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 671   @param Vector        The timer interrupt vector number.
 672 **/
 673 VOID
 674 EFIAPI
 675 InitializeApicTimer (
 676   IN UINTN   DivideValue,
 677   IN UINT32  InitCount,
 678   IN BOOLEAN PeriodicMode,
 679   IN UINT8   Vector
 680   )
 681 {
 682   LOCAL_APIC_SVR       Svr;
 683   LOCAL_APIC_DCR       Dcr;
 684   LOCAL_APIC_LVT_TIMER LvtTimer;
 685   UINT32               Divisor;
 686
 687   //
 688   // Ensure local APIC is in software-enabled state.
 689   //
 690   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 691   Svr.Bits.SoftwareEnable = 1;
 692   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 693
 694   //
 695   // Program init-count register.
 696   //
 697   WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
 698
 699   if (DivideValue != 0) {
 700     ASSERT (DivideValue <= 128);
 701     ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
 702     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
 703
 704     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 705     Dcr.Bits.DivideValue1 = (Divisor & 0x3);
 706     Dcr.Bits.DivideValue2 = (Divisor >> 2);
 707     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
 708   }
 709
 710   //
 711   // Enable APIC timer interrupt with specified timer mode.
 712   //
 713   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 714   if (PeriodicMode) {
 715     LvtTimer.Bits.TimerMode = 1;
 716   } else {
 717     LvtTimer.Bits.TimerMode = 0;
 718   }
 719   LvtTimer.Bits.Mask = 0;
 720   LvtTimer.Bits.Vector = Vector;
 721   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 722 }
 723
 724 /**
 725   Get the state of the local APIC timer.
 726
 727   This function will ASSERT if the local APIC is not software enabled.
 728
 729   @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 730   @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 731   @param Vector        Return the timer interrupt vector number.
 732 **/
 733 VOID
 734 EFIAPI
 735 GetApicTimerState (
 736   OUT UINTN    *DivideValue  OPTIONAL,
 737   OUT BOOLEAN  *PeriodicMode  OPTIONAL,
 738   OUT UINT8    *Vector  OPTIONAL
 739   )
 740 {
 741   UINT32 Divisor;
 742   LOCAL_APIC_DCR Dcr;
 743   LOCAL_APIC_LVT_TIMER LvtTimer;
 744
 745   //
 746   // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
 747   // Vector Register.
 748   // This bit will be 1, if local APIC is software enabled.
 749   //
 750   ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
 751
 752   if (DivideValue != NULL) {
 753     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 754     Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
 755     Divisor = (Divisor + 1) & 0x7;
 756     *DivideValue = ((UINTN)1) << Divisor;
 757   }
 758
 759   if (PeriodicMode != NULL || Vector != NULL) {
 760     LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 761     if (PeriodicMode != NULL) {
 762       if (LvtTimer.Bits.TimerMode == 1) {
 763         *PeriodicMode = TRUE;
 764       } else {
 765         *PeriodicMode = FALSE;
 766       }
 767     }
 768     if (Vector != NULL) {
 769       *Vector = (UINT8) LvtTimer.Bits.Vector;
 770     }
 771   }
 772 }
 773
 774 /**
 775   Enable the local APIC timer interrupt.
 776 **/
 777 VOID
 778 EFIAPI
 779 EnableApicTimerInterrupt (
 780   VOID
 781   )
 782 {
 783   LOCAL_APIC_LVT_TIMER LvtTimer;
 784
 785   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 786   LvtTimer.Bits.Mask = 0;
 787   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 788 }
 789
 790 /**
 791   Disable the local APIC timer interrupt.
 792 **/
 793 VOID
 794 EFIAPI
 795 DisableApicTimerInterrupt (
 796   VOID
 797   )
 798 {
 799   LOCAL_APIC_LVT_TIMER LvtTimer;
 800
 801   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 802   LvtTimer.Bits.Mask = 1;
 803   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 804 }
 805
 806 /**
 807   Get the local APIC timer interrupt state.
 808
 809   @retval TRUE  The local APIC timer interrupt is enabled.
 810   @retval FALSE The local APIC timer interrupt is disabled.
 811 **/
 812 BOOLEAN
 813 EFIAPI
 814 GetApicTimerInterruptState (
 815   VOID
 816   )
 817 {
 818   LOCAL_APIC_LVT_TIMER LvtTimer;
 819
 820   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 821   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
 822 }
 823
 824 /**
 825   Send EOI to the local APIC.
 826 **/
 827 VOID
 828 EFIAPI
 829 SendApicEoi (
 830   VOID
 831   )
 832 {
 833   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
 834 }
 835
 836 /**
 837   Get the 32-bit address that a device should use to send a Message Signaled
 838   Interrupt (MSI) to the Local APIC of the currently executing processor.
 839
 840   @return 32-bit address used to send an MSI to the Local APIC.
 841 **/
 842 UINT32
 843 EFIAPI
 844 GetApicMsiAddress (
 845   VOID
 846   )
 847 {
 848   LOCAL_APIC_MSI_ADDRESS  MsiAddress;
 849
 850   //
 851   // Return address for an MSI interrupt to be delivered only to the APIC ID
 852   // of the currently executing processor.
 853   //
 854   MsiAddress.Uint32             = 0;
 855   MsiAddress.Bits.BaseAddress   = 0xFEE;
 856   MsiAddress.Bits.DestinationId = GetApicId ();
 857   return MsiAddress.Uint32;
 858 }
 859
 860 /**
 861   Get the 64-bit data value that a device should use to send a Message Signaled
 862   Interrupt (MSI) to the Local APIC of the currently executing processor.
 863
 864   If Vector is not in range 0x10..0xFE, then ASSERT().
 865   If DeliveryMode is not supported, then ASSERT().
 866
 867   @param  Vector          The 8-bit interrupt vector associated with the MSI.
 868                           Must be in the range 0x10..0xFE
 869   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
 870                           is handled.  The only supported values are:
 871                             0: LOCAL_APIC_DELIVERY_MODE_FIXED
 872                             1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
 873                             2: LOCAL_APIC_DELIVERY_MODE_SMI
 874                             4: LOCAL_APIC_DELIVERY_MODE_NMI
 875                             5: LOCAL_APIC_DELIVERY_MODE_INIT
 876                             7: LOCAL_APIC_DELIVERY_MODE_EXTINT
 877
 878   @param  LevelTriggered  TRUE specifies a level triggered interrupt.
 879                           FALSE specifies an edge triggered interrupt.
 880   @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
 881                           TRUE specifies a level triggered interrupt that active
 882                           when the interrupt line is asserted.
 883                           FALSE specifies a level triggered interrupt that active
 884                           when the interrupt line is deasserted.
 885
 886   @return 64-bit data value used to send an MSI to the Local APIC.
 887 **/
 888 UINT64
 889 EFIAPI
 890 GetApicMsiValue (
 891   IN UINT8    Vector,
 892   IN UINTN    DeliveryMode,
 893   IN BOOLEAN  LevelTriggered,
 894   IN BOOLEAN  AssertionLevel
 895   )
 896 {
 897   LOCAL_APIC_MSI_DATA  MsiData;
 898
 899   ASSERT (Vector >= 0x10 && Vector <= 0xFE);
 900   ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
 901
 902   MsiData.Uint64            = 0;
 903   MsiData.Bits.Vector       = Vector;
 904   MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
 905   if (LevelTriggered) {
 906     MsiData.Bits.TriggerMode = 1;
 907     if (AssertionLevel) {
 908       MsiData.Bits.Level = 1;
 909     }
 910   }
 911   return MsiData.Uint64;
 912 }