Add DisableLvtInterrupts() for the Local APIC library class.
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
1 /** @file
2 Local APIC Library.
3
4 This local APIC library instance supports xAPIC mode only.
5
6 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include <Register/LocalApic.h>
18
19 #include <Library/BaseLib.h>
20 #include <Library/DebugLib.h>
21 #include <Library/LocalApicLib.h>
22 #include <Library/IoLib.h>
23 #include <Library/TimerLib.h>
24 #include <Library/PcdLib.h>
25
26 //
27 // Library internal functions
28 //
29
30 /**
31 Read from a local APIC register.
32
33 This function reads from a local APIC register either in xAPIC or x2APIC mode.
34 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
35 accessed using multiple 32-bit loads or stores, so this function only performs
36 32-bit read.
37
38 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
39 It must be 16-byte aligned.
40
41 @return 32-bit Value read from the register.
42 **/
43 UINT32
44 EFIAPI
45 ReadLocalApicReg (
46 IN UINTN MmioOffset
47 )
48 {
49 ASSERT ((MmioOffset & 0xf) == 0);
50 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
51
52 return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
53 }
54
55 /**
56 Write to a local APIC register.
57
58 This function writes to a local APIC register either in xAPIC or x2APIC mode.
59 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
60 accessed using multiple 32-bit loads or stores, so this function only performs
61 32-bit write.
62
63 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
64
65 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
66 It must be 16-byte aligned.
67 @param Value Value to be written to the register.
68 **/
69 VOID
70 EFIAPI
71 WriteLocalApicReg (
72 IN UINTN MmioOffset,
73 IN UINT32 Value
74 )
75 {
76 ASSERT ((MmioOffset & 0xf) == 0);
77 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
78
79 MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
80 }
81
82 /**
83 Send an IPI by writing to ICR.
84
85 This function returns after the IPI has been accepted by the target processor.
86
87 @param IcrLow 32-bit value to be written to the low half of ICR.
88 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
89 **/
90 VOID
91 SendIpi (
92 IN UINT32 IcrLow,
93 IN UINT32 ApicId
94 )
95 {
96 LOCAL_APIC_ICR_LOW IcrLowReg;
97
98 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
99 ASSERT (ApicId <= 0xff);
100
101 //
102 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
103 //
104 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
105 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
106 do {
107 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
108 } while (IcrLowReg.Bits.DeliveryStatus != 0);
109 }
110
111 //
112 // Library API implementation functions
113 //
114
115 /**
116 Get the current local APIC mode.
117
118 If local APIC is disabled, then ASSERT.
119
120 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
121 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
122 **/
123 UINTN
124 EFIAPI
125 GetApicMode (
126 VOID
127 )
128 {
129 DEBUG_CODE (
130 {
131 MSR_IA32_APIC_BASE ApicBaseMsr;
132
133 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
134 //
135 // Local APIC should have been enabled
136 //
137 ASSERT (ApicBaseMsr.Bits.En != 0);
138 ASSERT (ApicBaseMsr.Bits.Extd == 0);
139 }
140 );
141 return LOCAL_APIC_MODE_XAPIC;
142 }
143
144 /**
145 Set the current local APIC mode.
146
147 If the specified local APIC mode is not valid, then ASSERT.
148 If the specified local APIC mode can't be set as current, then ASSERT.
149
150 @param ApicMode APIC mode to be set.
151 **/
152 VOID
153 EFIAPI
154 SetApicMode (
155 IN UINTN ApicMode
156 )
157 {
158 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
159 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
160 }
161
162 /**
163 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
164
165 In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
166 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
167 the 32-bit local APIC ID is returned as initial APIC ID.
168
169 @return 32-bit initial local APIC ID of the executing processor.
170 **/
171 UINT32
172 EFIAPI
173 GetInitialApicId (
174 VOID
175 )
176 {
177 UINT32 RegEbx;
178
179 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
180
181 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
182 return RegEbx >> 24;
183 }
184
185 /**
186 Get the local APIC ID of the executing processor.
187
188 @return 32-bit local APIC ID of the executing processor.
189 **/
190 UINT32
191 EFIAPI
192 GetApicId (
193 VOID
194 )
195 {
196 UINT32 ApicId;
197
198 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
199
200 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
201 ApicId >>= 24;
202 return ApicId;
203 }
204
205 /**
206 Get the value of the local APIC version register.
207
208 @return the value of the local APIC version register.
209 **/
210 UINT32
211 EFIAPI
212 GetApicVersion (
213 VOID
214 )
215 {
216 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
217 }
218
219 /**
220 Send a Fixed IPI to a specified target processor.
221
222 This function returns after the IPI has been accepted by the target processor.
223
224 @param ApicId The local APIC ID of the target processor.
225 @param Vector The vector number of the interrupt being sent.
226 **/
227 VOID
228 EFIAPI
229 SendFixedIpi (
230 IN UINT32 ApicId,
231 IN UINT8 Vector
232 )
233 {
234 LOCAL_APIC_ICR_LOW IcrLow;
235
236 IcrLow.Uint32 = 0;
237 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
238 IcrLow.Bits.Level = 1;
239 IcrLow.Bits.Vector = Vector;
240 SendIpi (IcrLow.Uint32, ApicId);
241 }
242
243 /**
244 Send a Fixed IPI to all processors excluding self.
245
246 This function returns after the IPI has been accepted by the target processors.
247
248 @param Vector The vector number of the interrupt being sent.
249 **/
250 VOID
251 EFIAPI
252 SendFixedIpiAllExcludingSelf (
253 IN UINT8 Vector
254 )
255 {
256 LOCAL_APIC_ICR_LOW IcrLow;
257
258 IcrLow.Uint32 = 0;
259 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
260 IcrLow.Bits.Level = 1;
261 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
262 IcrLow.Bits.Vector = Vector;
263 SendIpi (IcrLow.Uint32, 0);
264 }
265
266 /**
267 Send a SMI IPI to a specified target processor.
268
269 This function returns after the IPI has been accepted by the target processor.
270
271 @param ApicId Specify the local APIC ID of the target processor.
272 **/
273 VOID
274 EFIAPI
275 SendSmiIpi (
276 IN UINT32 ApicId
277 )
278 {
279 LOCAL_APIC_ICR_LOW IcrLow;
280
281 IcrLow.Uint32 = 0;
282 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
283 IcrLow.Bits.Level = 1;
284 SendIpi (IcrLow.Uint32, ApicId);
285 }
286
287 /**
288 Send a SMI IPI to all processors excluding self.
289
290 This function returns after the IPI has been accepted by the target processors.
291 **/
292 VOID
293 EFIAPI
294 SendSmiIpiAllExcludingSelf (
295 VOID
296 )
297 {
298 LOCAL_APIC_ICR_LOW IcrLow;
299
300 IcrLow.Uint32 = 0;
301 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
302 IcrLow.Bits.Level = 1;
303 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
304 SendIpi (IcrLow.Uint32, 0);
305 }
306
307 /**
308 Send an INIT IPI to a specified target processor.
309
310 This function returns after the IPI has been accepted by the target processor.
311
312 @param ApicId Specify the local APIC ID of the target processor.
313 **/
314 VOID
315 EFIAPI
316 SendInitIpi (
317 IN UINT32 ApicId
318 )
319 {
320 LOCAL_APIC_ICR_LOW IcrLow;
321
322 IcrLow.Uint32 = 0;
323 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
324 IcrLow.Bits.Level = 1;
325 SendIpi (IcrLow.Uint32, ApicId);
326 }
327
328 /**
329 Send an INIT IPI to all processors excluding self.
330
331 This function returns after the IPI has been accepted by the target processors.
332 **/
333 VOID
334 EFIAPI
335 SendInitIpiAllExcludingSelf (
336 VOID
337 )
338 {
339 LOCAL_APIC_ICR_LOW IcrLow;
340
341 IcrLow.Uint32 = 0;
342 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
343 IcrLow.Bits.Level = 1;
344 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
345 SendIpi (IcrLow.Uint32, 0);
346 }
347
348 /**
349 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
350
351 This function returns after the IPI has been accepted by the target processor.
352
353 if StartupRoutine >= 1M, then ASSERT.
354 if StartupRoutine is not multiple of 4K, then ASSERT.
355
356 @param ApicId Specify the local APIC ID of the target processor.
357 @param StartupRoutine Points to a start-up routine which is below 1M physical
358 address and 4K aligned.
359 **/
360 VOID
361 EFIAPI
362 SendInitSipiSipi (
363 IN UINT32 ApicId,
364 IN UINT32 StartupRoutine
365 )
366 {
367 LOCAL_APIC_ICR_LOW IcrLow;
368
369 ASSERT (StartupRoutine < 0x100000);
370 ASSERT ((StartupRoutine & 0xfff) == 0);
371
372 SendInitIpi (ApicId);
373 MicroSecondDelay (10);
374 IcrLow.Uint32 = 0;
375 IcrLow.Bits.Vector = (StartupRoutine >> 12);
376 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
377 IcrLow.Bits.Level = 1;
378 SendIpi (IcrLow.Uint32, ApicId);
379 MicroSecondDelay (200);
380 SendIpi (IcrLow.Uint32, ApicId);
381 }
382
383 /**
384 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
385
386 This function returns after the IPI has been accepted by the target processors.
387
388 if StartupRoutine >= 1M, then ASSERT.
389 if StartupRoutine is not multiple of 4K, then ASSERT.
390
391 @param StartupRoutine Points to a start-up routine which is below 1M physical
392 address and 4K aligned.
393 **/
394 VOID
395 EFIAPI
396 SendInitSipiSipiAllExcludingSelf (
397 IN UINT32 StartupRoutine
398 )
399 {
400 LOCAL_APIC_ICR_LOW IcrLow;
401
402 ASSERT (StartupRoutine < 0x100000);
403 ASSERT ((StartupRoutine & 0xfff) == 0);
404
405 SendInitIpiAllExcludingSelf ();
406 MicroSecondDelay (10);
407 IcrLow.Uint32 = 0;
408 IcrLow.Bits.Vector = (StartupRoutine >> 12);
409 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
410 IcrLow.Bits.Level = 1;
411 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
412 SendIpi (IcrLow.Uint32, 0);
413 MicroSecondDelay (200);
414 SendIpi (IcrLow.Uint32, 0);
415 }
416
417 /**
418 Programming Virtual Wire Mode.
419
420 This function programs the local APIC for virtual wire mode following
421 the example described in chapter A.3 of the MP 1.4 spec.
422
423 IOxAPIC is not involved in this type of virtual wire mode.
424 **/
425 VOID
426 EFIAPI
427 ProgramVirtualWireMode (
428 VOID
429 )
430 {
431 LOCAL_APIC_SVR Svr;
432 LOCAL_APIC_LVT_LINT Lint;
433
434 //
435 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
436 //
437 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
438 Svr.Bits.SpuriousVector = 0xf;
439 Svr.Bits.SoftwareEnable = 1;
440 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
441
442 //
443 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
444 //
445 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
446 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
447 Lint.Bits.InputPinPolarity = 0;
448 Lint.Bits.TriggerMode = 0;
449 Lint.Bits.Mask = 0;
450 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
451
452 //
453 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
454 //
455 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
456 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
457 Lint.Bits.InputPinPolarity = 0;
458 Lint.Bits.TriggerMode = 0;
459 Lint.Bits.Mask = 0;
460 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
461 }
462
463 /**
464 Disable LINT0 & LINT1 interrupts.
465
466 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
467 **/
468 VOID
469 EFIAPI
470 DisableLvtInterrupts (
471 VOID
472 )
473 {
474 LOCAL_APIC_LVT_LINT LvtLint;
475
476 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
477 LvtLint.Bits.Mask = 1;
478 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
479
480 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
481 LvtLint.Bits.Mask = 1;
482 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
483 }
484
485 /**
486 Read the initial count value from the init-count register.
487
488 @return The initial count value read from the init-count register.
489 **/
490 UINT32
491 EFIAPI
492 GetApicTimerInitCount (
493 VOID
494 )
495 {
496 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
497 }
498
499 /**
500 Read the current count value from the current-count register.
501
502 @return The current count value read from the current-count register.
503 **/
504 UINT32
505 EFIAPI
506 GetApicTimerCurrentCount (
507 VOID
508 )
509 {
510 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
511 }
512
513 /**
514 Initialize the local APIC timer.
515
516 The local APIC timer is initialized and enabled.
517
518 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
519 If it is 0, then use the current divide value in the DCR.
520 @param InitCount The initial count value.
521 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
522 @param Vector The timer interrupt vector number.
523 **/
524 VOID
525 EFIAPI
526 InitializeApicTimer (
527 IN UINTN DivideValue,
528 IN UINT32 InitCount,
529 IN BOOLEAN PeriodicMode,
530 IN UINT8 Vector
531 )
532 {
533 LOCAL_APIC_SVR Svr;
534 LOCAL_APIC_DCR Dcr;
535 LOCAL_APIC_LVT_TIMER LvtTimer;
536 UINT32 Divisor;
537
538 //
539 // Ensure local APIC is in software-enabled state.
540 //
541 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
542 Svr.Bits.SoftwareEnable = 1;
543 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
544
545 //
546 // Program init-count register.
547 //
548 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
549
550 if (DivideValue != 0) {
551 ASSERT (DivideValue <= 128);
552 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
553 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
554
555 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
556 Dcr.Bits.DivideValue1 = (Divisor & 0x3);
557 Dcr.Bits.DivideValue2 = (Divisor >> 2);
558 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
559 }
560
561 //
562 // Enable APIC timer interrupt with specified timer mode.
563 //
564 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
565 if (PeriodicMode) {
566 LvtTimer.Bits.TimerMode = 1;
567 } else {
568 LvtTimer.Bits.TimerMode = 0;
569 }
570 LvtTimer.Bits.Mask = 0;
571 LvtTimer.Bits.Vector = Vector;
572 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
573 }
574
575 /**
576 Get the state of the local APIC timer.
577
578 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
579 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
580 @param Vector Return the timer interrupt vector number.
581 **/
582 VOID
583 EFIAPI
584 GetApicTimerState (
585 OUT UINTN *DivideValue OPTIONAL,
586 OUT BOOLEAN *PeriodicMode OPTIONAL,
587 OUT UINT8 *Vector OPTIONAL
588 )
589 {
590 UINT32 Divisor;
591 LOCAL_APIC_DCR Dcr;
592 LOCAL_APIC_LVT_TIMER LvtTimer;
593
594 if (DivideValue != NULL) {
595 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
596 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
597 Divisor = (Divisor + 1) & 0x7;
598 *DivideValue = ((UINTN)1) << Divisor;
599 }
600
601 if (PeriodicMode != NULL || Vector != NULL) {
602 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
603 if (PeriodicMode != NULL) {
604 if (LvtTimer.Bits.TimerMode == 1) {
605 *PeriodicMode = TRUE;
606 } else {
607 *PeriodicMode = FALSE;
608 }
609 }
610 if (Vector != NULL) {
611 *Vector = (UINT8) LvtTimer.Bits.Vector;
612 }
613 }
614 }
615
616 /**
617 Enable the local APIC timer interrupt.
618 **/
619 VOID
620 EFIAPI
621 EnableApicTimerInterrupt (
622 VOID
623 )
624 {
625 LOCAL_APIC_LVT_TIMER LvtTimer;
626
627 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
628 LvtTimer.Bits.Mask = 0;
629 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
630 }
631
632 /**
633 Disable the local APIC timer interrupt.
634 **/
635 VOID
636 EFIAPI
637 DisableApicTimerInterrupt (
638 VOID
639 )
640 {
641 LOCAL_APIC_LVT_TIMER LvtTimer;
642
643 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
644 LvtTimer.Bits.Mask = 1;
645 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
646 }
647
648 /**
649 Get the local APIC timer interrupt state.
650
651 @retval TRUE The local APIC timer interrupt is enabled.
652 @retval FALSE The local APIC timer interrupt is disabled.
653 **/
654 BOOLEAN
655 EFIAPI
656 GetApicTimerInterruptState (
657 VOID
658 )
659 {
660 LOCAL_APIC_LVT_TIMER LvtTimer;
661
662 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
663 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
664 }
665
666 /**
667 Send EOI to the local APIC.
668 **/
669 VOID
670 EFIAPI
671 SendApicEoi (
672 VOID
673 )
674 {
675 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
676 }
677