8d0fb021092992bac3904fdfc1e8d15e3436078a
[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c
1 /** @file
2 Local APIC Library.
3
4 This local APIC library instance supports xAPIC mode only.
5
6 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include <Register/Cpuid.h>
18 #include <Register/Msr.h>
19 #include <Register/LocalApic.h>
20
21 #include <Library/BaseLib.h>
22 #include <Library/DebugLib.h>
23 #include <Library/LocalApicLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/TimerLib.h>
26 #include <Library/PcdLib.h>
27
28 //
29 // Library internal functions
30 //
31
32 /**
33 Determine if the CPU supports the Local APIC Base Address MSR.
34
35 @retval TRUE The CPU supports the Local APIC Base Address MSR.
36 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
37
38 **/
39 BOOLEAN
40 LocalApicBaseAddressMsrSupported (
41 VOID
42 )
43 {
44 UINT32 RegEax;
45 UINTN FamilyId;
46
47 AsmCpuid (1, &RegEax, NULL, NULL, NULL);
48 FamilyId = BitFieldRead32 (RegEax, 8, 11);
49 if (FamilyId == 0x04 || FamilyId == 0x05) {
50 //
51 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
52 // Local APIC Base Address MSR
53 //
54 return FALSE;
55 }
56 return TRUE;
57 }
58
59 /**
60 Retrieve the base address of local APIC.
61
62 @return The base address of local APIC.
63
64 **/
65 UINTN
66 EFIAPI
67 GetLocalApicBaseAddress (
68 VOID
69 )
70 {
71 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
72
73 if (!LocalApicBaseAddressMsrSupported ()) {
74 //
75 // If CPU does not support Local APIC Base Address MSR, then retrieve
76 // Local APIC Base Address from PCD
77 //
78 return PcdGet32 (PcdCpuLocalApicBaseAddress);
79 }
80
81 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
82
83 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
84 (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
85 }
86
87 /**
88 Set the base address of local APIC.
89
90 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
91
92 @param[in] BaseAddress Local APIC base address to be set.
93
94 **/
95 VOID
96 EFIAPI
97 SetLocalApicBaseAddress (
98 IN UINTN BaseAddress
99 )
100 {
101 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
102
103 ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
104
105 if (!LocalApicBaseAddressMsrSupported ()) {
106 //
107 // Ignore set request if the CPU does not support APIC Base Address MSR
108 //
109 return;
110 }
111
112 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
113
114 ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
115 ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
116
117 AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
118 }
119
120 /**
121 Read from a local APIC register.
122
123 This function reads from a local APIC register either in xAPIC or x2APIC mode.
124 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
125 accessed using multiple 32-bit loads or stores, so this function only performs
126 32-bit read.
127
128 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
129 It must be 16-byte aligned.
130
131 @return 32-bit Value read from the register.
132 **/
133 UINT32
134 EFIAPI
135 ReadLocalApicReg (
136 IN UINTN MmioOffset
137 )
138 {
139 ASSERT ((MmioOffset & 0xf) == 0);
140 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
141
142 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
143 }
144
145 /**
146 Write to a local APIC register.
147
148 This function writes to a local APIC register either in xAPIC or x2APIC mode.
149 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
150 accessed using multiple 32-bit loads or stores, so this function only performs
151 32-bit write.
152
153 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
154
155 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
156 It must be 16-byte aligned.
157 @param Value Value to be written to the register.
158 **/
159 VOID
160 EFIAPI
161 WriteLocalApicReg (
162 IN UINTN MmioOffset,
163 IN UINT32 Value
164 )
165 {
166 ASSERT ((MmioOffset & 0xf) == 0);
167 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
168
169 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
170 }
171
172 /**
173 Send an IPI by writing to ICR.
174
175 This function returns after the IPI has been accepted by the target processor.
176
177 @param IcrLow 32-bit value to be written to the low half of ICR.
178 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
179 **/
180 VOID
181 SendIpi (
182 IN UINT32 IcrLow,
183 IN UINT32 ApicId
184 )
185 {
186 LOCAL_APIC_ICR_LOW IcrLowReg;
187 UINT32 IcrHigh;
188 BOOLEAN InterruptState;
189
190 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
191 ASSERT (ApicId <= 0xff);
192
193 InterruptState = SaveAndDisableInterrupts ();
194
195 //
196 // Save existing contents of ICR high 32 bits
197 //
198 IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);
199
200 //
201 // Wait for DeliveryStatus clear in case a previous IPI
202 // is still being sent
203 //
204 do {
205 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
206 } while (IcrLowReg.Bits.DeliveryStatus != 0);
207
208 //
209 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
210 //
211 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
212 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
213
214 //
215 // Wait for DeliveryStatus clear again
216 //
217 do {
218 IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
219 } while (IcrLowReg.Bits.DeliveryStatus != 0);
220
221 //
222 // And restore old contents of ICR high
223 //
224 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
225
226 SetInterruptState (InterruptState);
227
228 }
229
230 //
231 // Library API implementation functions
232 //
233
234 /**
235 Get the current local APIC mode.
236
237 If local APIC is disabled, then ASSERT.
238
239 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
240 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
241 **/
242 UINTN
243 EFIAPI
244 GetApicMode (
245 VOID
246 )
247 {
248 DEBUG_CODE (
249 {
250 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
251
252 //
253 // Check to see if the CPU supports the APIC Base Address MSR
254 //
255 if (LocalApicBaseAddressMsrSupported ()) {
256 ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
257 //
258 // Local APIC should have been enabled
259 //
260 ASSERT (ApicBaseMsr.Bits.EN != 0);
261 ASSERT (ApicBaseMsr.Bits.EXTD == 0);
262 }
263 }
264 );
265 return LOCAL_APIC_MODE_XAPIC;
266 }
267
268 /**
269 Set the current local APIC mode.
270
271 If the specified local APIC mode is not valid, then ASSERT.
272 If the specified local APIC mode can't be set as current, then ASSERT.
273
274 @param ApicMode APIC mode to be set.
275
276 @note This API must not be called from an interrupt handler or SMI handler.
277 It may result in unpredictable behavior.
278 **/
279 VOID
280 EFIAPI
281 SetApicMode (
282 IN UINTN ApicMode
283 )
284 {
285 ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
286 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
287 }
288
289 /**
290 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
291
292 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
293 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
294 the 32-bit local APIC ID is returned as initial APIC ID.
295
296 @return 32-bit initial local APIC ID of the executing processor.
297 **/
298 UINT32
299 EFIAPI
300 GetInitialApicId (
301 VOID
302 )
303 {
304 UINT32 ApicId;
305 UINT32 MaxCpuIdIndex;
306 UINT32 RegEbx;
307
308 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
309
310 //
311 // Get the max index of basic CPUID
312 //
313 AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
314
315 //
316 // If CPUID Leaf B is supported,
317 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
318 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
319 //
320 if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
321 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
322 return ApicId;
323 }
324
325 AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
326 return RegEbx >> 24;
327 }
328
329 /**
330 Get the local APIC ID of the executing processor.
331
332 @return 32-bit local APIC ID of the executing processor.
333 **/
334 UINT32
335 EFIAPI
336 GetApicId (
337 VOID
338 )
339 {
340 UINT32 ApicId;
341
342 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
343
344 if ((ApicId = GetInitialApicId ()) < 0x100) {
345 //
346 // If the initial local APIC ID is less 0x100, read APIC ID from
347 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
348 //
349 ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
350 ApicId >>= 24;
351 }
352 return ApicId;
353 }
354
355 /**
356 Get the value of the local APIC version register.
357
358 @return the value of the local APIC version register.
359 **/
360 UINT32
361 EFIAPI
362 GetApicVersion (
363 VOID
364 )
365 {
366 return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
367 }
368
369 /**
370 Send a Fixed IPI to a specified target processor.
371
372 This function returns after the IPI has been accepted by the target processor.
373
374 @param ApicId The local APIC ID of the target processor.
375 @param Vector The vector number of the interrupt being sent.
376 **/
377 VOID
378 EFIAPI
379 SendFixedIpi (
380 IN UINT32 ApicId,
381 IN UINT8 Vector
382 )
383 {
384 LOCAL_APIC_ICR_LOW IcrLow;
385
386 IcrLow.Uint32 = 0;
387 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
388 IcrLow.Bits.Level = 1;
389 IcrLow.Bits.Vector = Vector;
390 SendIpi (IcrLow.Uint32, ApicId);
391 }
392
393 /**
394 Send a Fixed IPI to all processors excluding self.
395
396 This function returns after the IPI has been accepted by the target processors.
397
398 @param Vector The vector number of the interrupt being sent.
399 **/
400 VOID
401 EFIAPI
402 SendFixedIpiAllExcludingSelf (
403 IN UINT8 Vector
404 )
405 {
406 LOCAL_APIC_ICR_LOW IcrLow;
407
408 IcrLow.Uint32 = 0;
409 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
410 IcrLow.Bits.Level = 1;
411 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
412 IcrLow.Bits.Vector = Vector;
413 SendIpi (IcrLow.Uint32, 0);
414 }
415
416 /**
417 Send a SMI IPI to a specified target processor.
418
419 This function returns after the IPI has been accepted by the target processor.
420
421 @param ApicId Specify the local APIC ID of the target processor.
422 **/
423 VOID
424 EFIAPI
425 SendSmiIpi (
426 IN UINT32 ApicId
427 )
428 {
429 LOCAL_APIC_ICR_LOW IcrLow;
430
431 IcrLow.Uint32 = 0;
432 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
433 IcrLow.Bits.Level = 1;
434 SendIpi (IcrLow.Uint32, ApicId);
435 }
436
437 /**
438 Send a SMI IPI to all processors excluding self.
439
440 This function returns after the IPI has been accepted by the target processors.
441 **/
442 VOID
443 EFIAPI
444 SendSmiIpiAllExcludingSelf (
445 VOID
446 )
447 {
448 LOCAL_APIC_ICR_LOW IcrLow;
449
450 IcrLow.Uint32 = 0;
451 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
452 IcrLow.Bits.Level = 1;
453 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
454 SendIpi (IcrLow.Uint32, 0);
455 }
456
457 /**
458 Send an INIT IPI to a specified target processor.
459
460 This function returns after the IPI has been accepted by the target processor.
461
462 @param ApicId Specify the local APIC ID of the target processor.
463 **/
464 VOID
465 EFIAPI
466 SendInitIpi (
467 IN UINT32 ApicId
468 )
469 {
470 LOCAL_APIC_ICR_LOW IcrLow;
471
472 IcrLow.Uint32 = 0;
473 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
474 IcrLow.Bits.Level = 1;
475 SendIpi (IcrLow.Uint32, ApicId);
476 }
477
478 /**
479 Send an INIT IPI to all processors excluding self.
480
481 This function returns after the IPI has been accepted by the target processors.
482 **/
483 VOID
484 EFIAPI
485 SendInitIpiAllExcludingSelf (
486 VOID
487 )
488 {
489 LOCAL_APIC_ICR_LOW IcrLow;
490
491 IcrLow.Uint32 = 0;
492 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
493 IcrLow.Bits.Level = 1;
494 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
495 SendIpi (IcrLow.Uint32, 0);
496 }
497
498 /**
499 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
500
501 This function returns after the IPI has been accepted by the target processor.
502
503 if StartupRoutine >= 1M, then ASSERT.
504 if StartupRoutine is not multiple of 4K, then ASSERT.
505
506 @param ApicId Specify the local APIC ID of the target processor.
507 @param StartupRoutine Points to a start-up routine which is below 1M physical
508 address and 4K aligned.
509 **/
510 VOID
511 EFIAPI
512 SendInitSipiSipi (
513 IN UINT32 ApicId,
514 IN UINT32 StartupRoutine
515 )
516 {
517 LOCAL_APIC_ICR_LOW IcrLow;
518
519 ASSERT (StartupRoutine < 0x100000);
520 ASSERT ((StartupRoutine & 0xfff) == 0);
521
522 SendInitIpi (ApicId);
523 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
524 IcrLow.Uint32 = 0;
525 IcrLow.Bits.Vector = (StartupRoutine >> 12);
526 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
527 IcrLow.Bits.Level = 1;
528 SendIpi (IcrLow.Uint32, ApicId);
529 MicroSecondDelay (200);
530 SendIpi (IcrLow.Uint32, ApicId);
531 }
532
533 /**
534 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
535
536 This function returns after the IPI has been accepted by the target processors.
537
538 if StartupRoutine >= 1M, then ASSERT.
539 if StartupRoutine is not multiple of 4K, then ASSERT.
540
541 @param StartupRoutine Points to a start-up routine which is below 1M physical
542 address and 4K aligned.
543 **/
544 VOID
545 EFIAPI
546 SendInitSipiSipiAllExcludingSelf (
547 IN UINT32 StartupRoutine
548 )
549 {
550 LOCAL_APIC_ICR_LOW IcrLow;
551
552 ASSERT (StartupRoutine < 0x100000);
553 ASSERT ((StartupRoutine & 0xfff) == 0);
554
555 SendInitIpiAllExcludingSelf ();
556 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
557 IcrLow.Uint32 = 0;
558 IcrLow.Bits.Vector = (StartupRoutine >> 12);
559 IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
560 IcrLow.Bits.Level = 1;
561 IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
562 SendIpi (IcrLow.Uint32, 0);
563 MicroSecondDelay (200);
564 SendIpi (IcrLow.Uint32, 0);
565 }
566
567 /**
568 Initialize the state of the SoftwareEnable bit in the Local APIC
569 Spurious Interrupt Vector register.
570
571 @param Enable If TRUE, then set SoftwareEnable to 1
572 If FALSE, then set SoftwareEnable to 0.
573
574 **/
575 VOID
576 EFIAPI
577 InitializeLocalApicSoftwareEnable (
578 IN BOOLEAN Enable
579 )
580 {
581 LOCAL_APIC_SVR Svr;
582
583 //
584 // Set local APIC software-enabled bit.
585 //
586 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
587 if (Enable) {
588 if (Svr.Bits.SoftwareEnable == 0) {
589 Svr.Bits.SoftwareEnable = 1;
590 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
591 }
592 } else {
593 if (Svr.Bits.SoftwareEnable == 1) {
594 Svr.Bits.SoftwareEnable = 0;
595 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
596 }
597 }
598 }
599
600 /**
601 Programming Virtual Wire Mode.
602
603 This function programs the local APIC for virtual wire mode following
604 the example described in chapter A.3 of the MP 1.4 spec.
605
606 IOxAPIC is not involved in this type of virtual wire mode.
607 **/
608 VOID
609 EFIAPI
610 ProgramVirtualWireMode (
611 VOID
612 )
613 {
614 LOCAL_APIC_SVR Svr;
615 LOCAL_APIC_LVT_LINT Lint;
616
617 //
618 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
619 //
620 Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
621 Svr.Bits.SpuriousVector = 0xf;
622 Svr.Bits.SoftwareEnable = 1;
623 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
624
625 //
626 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
627 //
628 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
629 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
630 Lint.Bits.InputPinPolarity = 0;
631 Lint.Bits.TriggerMode = 0;
632 Lint.Bits.Mask = 0;
633 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
634
635 //
636 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
637 //
638 Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
639 Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
640 Lint.Bits.InputPinPolarity = 0;
641 Lint.Bits.TriggerMode = 0;
642 Lint.Bits.Mask = 0;
643 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
644 }
645
646 /**
647 Disable LINT0 & LINT1 interrupts.
648
649 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
650 **/
651 VOID
652 EFIAPI
653 DisableLvtInterrupts (
654 VOID
655 )
656 {
657 LOCAL_APIC_LVT_LINT LvtLint;
658
659 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
660 LvtLint.Bits.Mask = 1;
661 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
662
663 LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
664 LvtLint.Bits.Mask = 1;
665 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
666 }
667
668 /**
669 Read the initial count value from the init-count register.
670
671 @return The initial count value read from the init-count register.
672 **/
673 UINT32
674 EFIAPI
675 GetApicTimerInitCount (
676 VOID
677 )
678 {
679 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
680 }
681
682 /**
683 Read the current count value from the current-count register.
684
685 @return The current count value read from the current-count register.
686 **/
687 UINT32
688 EFIAPI
689 GetApicTimerCurrentCount (
690 VOID
691 )
692 {
693 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
694 }
695
696 /**
697 Initialize the local APIC timer.
698
699 The local APIC timer is initialized and enabled.
700
701 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
702 If it is 0, then use the current divide value in the DCR.
703 @param InitCount The initial count value.
704 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
705 @param Vector The timer interrupt vector number.
706 **/
707 VOID
708 EFIAPI
709 InitializeApicTimer (
710 IN UINTN DivideValue,
711 IN UINT32 InitCount,
712 IN BOOLEAN PeriodicMode,
713 IN UINT8 Vector
714 )
715 {
716 LOCAL_APIC_DCR Dcr;
717 LOCAL_APIC_LVT_TIMER LvtTimer;
718 UINT32 Divisor;
719
720 //
721 // Ensure local APIC is in software-enabled state.
722 //
723 InitializeLocalApicSoftwareEnable (TRUE);
724
725 //
726 // Program init-count register.
727 //
728 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
729
730 if (DivideValue != 0) {
731 ASSERT (DivideValue <= 128);
732 ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
733 Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
734
735 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
736 Dcr.Bits.DivideValue1 = (Divisor & 0x3);
737 Dcr.Bits.DivideValue2 = (Divisor >> 2);
738 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
739 }
740
741 //
742 // Enable APIC timer interrupt with specified timer mode.
743 //
744 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
745 if (PeriodicMode) {
746 LvtTimer.Bits.TimerMode = 1;
747 } else {
748 LvtTimer.Bits.TimerMode = 0;
749 }
750 LvtTimer.Bits.Mask = 0;
751 LvtTimer.Bits.Vector = Vector;
752 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
753 }
754
755 /**
756 Get the state of the local APIC timer.
757
758 This function will ASSERT if the local APIC is not software enabled.
759
760 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
761 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
762 @param Vector Return the timer interrupt vector number.
763 **/
764 VOID
765 EFIAPI
766 GetApicTimerState (
767 OUT UINTN *DivideValue OPTIONAL,
768 OUT BOOLEAN *PeriodicMode OPTIONAL,
769 OUT UINT8 *Vector OPTIONAL
770 )
771 {
772 UINT32 Divisor;
773 LOCAL_APIC_DCR Dcr;
774 LOCAL_APIC_LVT_TIMER LvtTimer;
775
776 //
777 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
778 // Vector Register.
779 // This bit will be 1, if local APIC is software enabled.
780 //
781 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
782
783 if (DivideValue != NULL) {
784 Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
785 Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
786 Divisor = (Divisor + 1) & 0x7;
787 *DivideValue = ((UINTN)1) << Divisor;
788 }
789
790 if (PeriodicMode != NULL || Vector != NULL) {
791 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
792 if (PeriodicMode != NULL) {
793 if (LvtTimer.Bits.TimerMode == 1) {
794 *PeriodicMode = TRUE;
795 } else {
796 *PeriodicMode = FALSE;
797 }
798 }
799 if (Vector != NULL) {
800 *Vector = (UINT8) LvtTimer.Bits.Vector;
801 }
802 }
803 }
804
805 /**
806 Enable the local APIC timer interrupt.
807 **/
808 VOID
809 EFIAPI
810 EnableApicTimerInterrupt (
811 VOID
812 )
813 {
814 LOCAL_APIC_LVT_TIMER LvtTimer;
815
816 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
817 LvtTimer.Bits.Mask = 0;
818 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
819 }
820
821 /**
822 Disable the local APIC timer interrupt.
823 **/
824 VOID
825 EFIAPI
826 DisableApicTimerInterrupt (
827 VOID
828 )
829 {
830 LOCAL_APIC_LVT_TIMER LvtTimer;
831
832 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
833 LvtTimer.Bits.Mask = 1;
834 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
835 }
836
837 /**
838 Get the local APIC timer interrupt state.
839
840 @retval TRUE The local APIC timer interrupt is enabled.
841 @retval FALSE The local APIC timer interrupt is disabled.
842 **/
843 BOOLEAN
844 EFIAPI
845 GetApicTimerInterruptState (
846 VOID
847 )
848 {
849 LOCAL_APIC_LVT_TIMER LvtTimer;
850
851 LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
852 return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
853 }
854
855 /**
856 Send EOI to the local APIC.
857 **/
858 VOID
859 EFIAPI
860 SendApicEoi (
861 VOID
862 )
863 {
864 WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
865 }
866
867 /**
868 Get the 32-bit address that a device should use to send a Message Signaled
869 Interrupt (MSI) to the Local APIC of the currently executing processor.
870
871 @return 32-bit address used to send an MSI to the Local APIC.
872 **/
873 UINT32
874 EFIAPI
875 GetApicMsiAddress (
876 VOID
877 )
878 {
879 LOCAL_APIC_MSI_ADDRESS MsiAddress;
880
881 //
882 // Return address for an MSI interrupt to be delivered only to the APIC ID
883 // of the currently executing processor.
884 //
885 MsiAddress.Uint32 = 0;
886 MsiAddress.Bits.BaseAddress = 0xFEE;
887 MsiAddress.Bits.DestinationId = GetApicId ();
888 return MsiAddress.Uint32;
889 }
890
891 /**
892 Get the 64-bit data value that a device should use to send a Message Signaled
893 Interrupt (MSI) to the Local APIC of the currently executing processor.
894
895 If Vector is not in range 0x10..0xFE, then ASSERT().
896 If DeliveryMode is not supported, then ASSERT().
897
898 @param Vector The 8-bit interrupt vector associated with the MSI.
899 Must be in the range 0x10..0xFE
900 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
901 is handled. The only supported values are:
902 0: LOCAL_APIC_DELIVERY_MODE_FIXED
903 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
904 2: LOCAL_APIC_DELIVERY_MODE_SMI
905 4: LOCAL_APIC_DELIVERY_MODE_NMI
906 5: LOCAL_APIC_DELIVERY_MODE_INIT
907 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
908
909 @param LevelTriggered TRUE specifies a level triggered interrupt.
910 FALSE specifies an edge triggered interrupt.
911 @param AssertionLevel Ignored if LevelTriggered is FALSE.
912 TRUE specifies a level triggered interrupt that active
913 when the interrupt line is asserted.
914 FALSE specifies a level triggered interrupt that active
915 when the interrupt line is deasserted.
916
917 @return 64-bit data value used to send an MSI to the Local APIC.
918 **/
919 UINT64
920 EFIAPI
921 GetApicMsiValue (
922 IN UINT8 Vector,
923 IN UINTN DeliveryMode,
924 IN BOOLEAN LevelTriggered,
925 IN BOOLEAN AssertionLevel
926 )
927 {
928 LOCAL_APIC_MSI_DATA MsiData;
929
930 ASSERT (Vector >= 0x10 && Vector <= 0xFE);
931 ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
932
933 MsiData.Uint64 = 0;
934 MsiData.Bits.Vector = Vector;
935 MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
936 if (LevelTriggered) {
937 MsiData.Bits.TriggerMode = 1;
938 if (AssertionLevel) {
939 MsiData.Bits.Level = 1;
940 }
941 }
942 return MsiData.Uint64;
943 }