UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c

   1 /** @file
   2   Local APIC Library.
   3
   4   This local APIC library instance supports xAPIC mode only.
   5
   6   Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include <Register/LocalApic.h>
  18
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/LocalApicLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/TimerLib.h>
  24
  25 //
  26 // Library internal functions
  27 //
  28
  29 /**
  30   Retrieve the base address of local APIC.
  31
  32   @return The base address of local APIC.
  33
  34 **/
  35 UINTN
  36 EFIAPI
  37 GetLocalApicBaseAddress (
  38   VOID
  39   )
  40 {
  41   MSR_IA32_APIC_BASE ApicBaseMsr;
  42
  43   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  44
  45   return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
  46            (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
  47 }
  48
  49 /**
  50   Set the base address of local APIC.
  51
  52   If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
  53
  54   @param[in] BaseAddress   Local APIC base address to be set.
  55
  56 **/
  57 VOID
  58 EFIAPI
  59 SetLocalApicBaseAddress (
  60   IN UINTN                BaseAddress
  61   )
  62 {
  63   MSR_IA32_APIC_BASE ApicBaseMsr;
  64
  65   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
  66
  67   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  68
  69   ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
  70   ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
  71
  72   AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
  73 }
  74
  75 /**
  76   Read from a local APIC register.
  77
  78   This function reads from a local APIC register either in xAPIC or x2APIC mode.
  79   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  80   accessed using multiple 32-bit loads or stores, so this function only performs
  81   32-bit read.
  82
  83   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
  84                       It must be 16-byte aligned.
  85
  86   @return 32-bit      Value read from the register.
  87 **/
  88 UINT32
  89 EFIAPI
  90 ReadLocalApicReg (
  91   IN UINTN  MmioOffset
  92   )
  93 {
  94   ASSERT ((MmioOffset & 0xf) == 0);
  95   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  96
  97   return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
  98 }
  99
 100 /**
 101   Write to a local APIC register.
 102
 103   This function writes to a local APIC register either in xAPIC or x2APIC mode.
 104   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
 105   accessed using multiple 32-bit loads or stores, so this function only performs
 106   32-bit write.
 107
 108   if the register index is invalid or unsupported in current APIC mode, then ASSERT.
 109
 110   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
 111                       It must be 16-byte aligned.
 112   @param  Value       Value to be written to the register.
 113 **/
 114 VOID
 115 EFIAPI
 116 WriteLocalApicReg (
 117   IN UINTN  MmioOffset,
 118   IN UINT32 Value
 119   )
 120 {
 121   ASSERT ((MmioOffset & 0xf) == 0);
 122   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 123
 124   MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
 125 }
 126
 127 /**
 128   Send an IPI by writing to ICR.
 129
 130   This function returns after the IPI has been accepted by the target processor.
 131
 132   @param  IcrLow 32-bit value to be written to the low half of ICR.
 133   @param  ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
 134 **/
 135 VOID
 136 SendIpi (
 137   IN UINT32          IcrLow,
 138   IN UINT32          ApicId
 139   )
 140 {
 141   LOCAL_APIC_ICR_LOW IcrLowReg;
 142
 143   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 144   ASSERT (ApicId <= 0xff);
 145
 146   //
 147   // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
 148   //
 149   WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
 150   WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
 151   do {
 152     IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
 153   } while (IcrLowReg.Bits.DeliveryStatus != 0);
 154 }
 155
 156 //
 157 // Library API implementation functions
 158 //
 159
 160 /**
 161   Get the current local APIC mode.
 162
 163   If local APIC is disabled, then ASSERT.
 164
 165   @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.
 166   @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
 167 **/
 168 UINTN
 169 EFIAPI
 170 GetApicMode (
 171   VOID
 172   )
 173 {
 174   DEBUG_CODE (
 175     {
 176       MSR_IA32_APIC_BASE ApicBaseMsr;
 177
 178       ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 179       //
 180       // Local APIC should have been enabled
 181       //
 182       ASSERT (ApicBaseMsr.Bits.En != 0);
 183       ASSERT (ApicBaseMsr.Bits.Extd == 0);
 184     }
 185   );
 186   return LOCAL_APIC_MODE_XAPIC;
 187 }
 188
 189 /**
 190   Set the current local APIC mode.
 191
 192   If the specified local APIC mode is not valid, then ASSERT.
 193   If the specified local APIC mode can't be set as current, then ASSERT.
 194
 195   @param ApicMode APIC mode to be set.
 196 **/
 197 VOID
 198 EFIAPI
 199 SetApicMode (
 200   IN UINTN  ApicMode
 201   )
 202 {
 203   ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
 204   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 205 }
 206
 207 /**
 208   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
 209
 210   In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
 211   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
 212   the 32-bit local APIC ID is returned as initial APIC ID.
 213
 214   @return  32-bit initial local APIC ID of the executing processor.
 215 **/
 216 UINT32
 217 EFIAPI
 218 GetInitialApicId (
 219   VOID
 220   )
 221 {
 222   UINT32 ApicId;
 223   UINT32 MaxCpuIdIndex;
 224   UINT32 RegEbx;
 225
 226   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 227
 228   //
 229   // Get the max index of basic CPUID
 230   //
 231   AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
 232
 233   //
 234   // If CPUID Leaf B is supported,
 235   // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
 236   // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
 237   //
 238   if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
 239     AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
 240     return ApicId;
 241   }
 242
 243   AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
 244   return RegEbx >> 24;
 245 }
 246
 247 /**
 248   Get the local APIC ID of the executing processor.
 249
 250   @return  32-bit local APIC ID of the executing processor.
 251 **/
 252 UINT32
 253 EFIAPI
 254 GetApicId (
 255   VOID
 256   )
 257 {
 258   UINT32 ApicId;
 259
 260   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 261
 262   if ((ApicId = GetInitialApicId ()) < 0x100) {
 263     //
 264     // If the initial local APIC ID is less 0x100, read APIC ID from
 265     // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
 266     //
 267     ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
 268     ApicId >>= 24;
 269   }
 270   return ApicId;
 271 }
 272
 273 /**
 274   Get the value of the local APIC version register.
 275
 276   @return  the value of the local APIC version register.
 277 **/
 278 UINT32
 279 EFIAPI
 280 GetApicVersion (
 281   VOID
 282   )
 283 {
 284   return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
 285 }
 286
 287 /**
 288   Send a Fixed IPI to a specified target processor.
 289
 290   This function returns after the IPI has been accepted by the target processor.
 291
 292   @param  ApicId   The local APIC ID of the target processor.
 293   @param  Vector   The vector number of the interrupt being sent.
 294 **/
 295 VOID
 296 EFIAPI
 297 SendFixedIpi (
 298   IN UINT32          ApicId,
 299   IN UINT8           Vector
 300   )
 301 {
 302   LOCAL_APIC_ICR_LOW IcrLow;
 303
 304   IcrLow.Uint32 = 0;
 305   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 306   IcrLow.Bits.Level = 1;
 307   IcrLow.Bits.Vector = Vector;
 308   SendIpi (IcrLow.Uint32, ApicId);
 309 }
 310
 311 /**
 312   Send a Fixed IPI to all processors excluding self.
 313
 314   This function returns after the IPI has been accepted by the target processors.
 315
 316   @param  Vector   The vector number of the interrupt being sent.
 317 **/
 318 VOID
 319 EFIAPI
 320 SendFixedIpiAllExcludingSelf (
 321   IN UINT8           Vector
 322   )
 323 {
 324   LOCAL_APIC_ICR_LOW IcrLow;
 325
 326   IcrLow.Uint32 = 0;
 327   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 328   IcrLow.Bits.Level = 1;
 329   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 330   IcrLow.Bits.Vector = Vector;
 331   SendIpi (IcrLow.Uint32, 0);
 332 }
 333
 334 /**
 335   Send a SMI IPI to a specified target processor.
 336
 337   This function returns after the IPI has been accepted by the target processor.
 338
 339   @param  ApicId   Specify the local APIC ID of the target processor.
 340 **/
 341 VOID
 342 EFIAPI
 343 SendSmiIpi (
 344   IN UINT32          ApicId
 345   )
 346 {
 347   LOCAL_APIC_ICR_LOW IcrLow;
 348
 349   IcrLow.Uint32 = 0;
 350   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 351   IcrLow.Bits.Level = 1;
 352   SendIpi (IcrLow.Uint32, ApicId);
 353 }
 354
 355 /**
 356   Send a SMI IPI to all processors excluding self.
 357
 358   This function returns after the IPI has been accepted by the target processors.
 359 **/
 360 VOID
 361 EFIAPI
 362 SendSmiIpiAllExcludingSelf (
 363   VOID
 364   )
 365 {
 366   LOCAL_APIC_ICR_LOW IcrLow;
 367
 368   IcrLow.Uint32 = 0;
 369   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 370   IcrLow.Bits.Level = 1;
 371   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 372   SendIpi (IcrLow.Uint32, 0);
 373 }
 374
 375 /**
 376   Send an INIT IPI to a specified target processor.
 377
 378   This function returns after the IPI has been accepted by the target processor.
 379
 380   @param  ApicId   Specify the local APIC ID of the target processor.
 381 **/
 382 VOID
 383 EFIAPI
 384 SendInitIpi (
 385   IN UINT32          ApicId
 386   )
 387 {
 388   LOCAL_APIC_ICR_LOW IcrLow;
 389
 390   IcrLow.Uint32 = 0;
 391   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 392   IcrLow.Bits.Level = 1;
 393   SendIpi (IcrLow.Uint32, ApicId);
 394 }
 395
 396 /**
 397   Send an INIT IPI to all processors excluding self.
 398
 399   This function returns after the IPI has been accepted by the target processors.
 400 **/
 401 VOID
 402 EFIAPI
 403 SendInitIpiAllExcludingSelf (
 404   VOID
 405   )
 406 {
 407   LOCAL_APIC_ICR_LOW IcrLow;
 408
 409   IcrLow.Uint32 = 0;
 410   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 411   IcrLow.Bits.Level = 1;
 412   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 413   SendIpi (IcrLow.Uint32, 0);
 414 }
 415
 416 /**
 417   Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
 418
 419   This function returns after the IPI has been accepted by the target processor.
 420
 421   if StartupRoutine >= 1M, then ASSERT.
 422   if StartupRoutine is not multiple of 4K, then ASSERT.
 423
 424   @param  ApicId          Specify the local APIC ID of the target processor.
 425   @param  StartupRoutine  Points to a start-up routine which is below 1M physical
 426                           address and 4K aligned.
 427 **/
 428 VOID
 429 EFIAPI
 430 SendInitSipiSipi (
 431   IN UINT32          ApicId,
 432   IN UINT32          StartupRoutine
 433   )
 434 {
 435   LOCAL_APIC_ICR_LOW IcrLow;
 436
 437   ASSERT (StartupRoutine < 0x100000);
 438   ASSERT ((StartupRoutine & 0xfff) == 0);
 439
 440   SendInitIpi (ApicId);
 441   MicroSecondDelay (10);
 442   IcrLow.Uint32 = 0;
 443   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 444   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 445   IcrLow.Bits.Level = 1;
 446   SendIpi (IcrLow.Uint32, ApicId);
 447   MicroSecondDelay (200);
 448   SendIpi (IcrLow.Uint32, ApicId);
 449 }
 450
 451 /**
 452   Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
 453
 454   This function returns after the IPI has been accepted by the target processors.
 455
 456   if StartupRoutine >= 1M, then ASSERT.
 457   if StartupRoutine is not multiple of 4K, then ASSERT.
 458
 459   @param  StartupRoutine    Points to a start-up routine which is below 1M physical
 460                             address and 4K aligned.
 461 **/
 462 VOID
 463 EFIAPI
 464 SendInitSipiSipiAllExcludingSelf (
 465   IN UINT32          StartupRoutine
 466   )
 467 {
 468   LOCAL_APIC_ICR_LOW IcrLow;
 469
 470   ASSERT (StartupRoutine < 0x100000);
 471   ASSERT ((StartupRoutine & 0xfff) == 0);
 472
 473   SendInitIpiAllExcludingSelf ();
 474   MicroSecondDelay (10);
 475   IcrLow.Uint32 = 0;
 476   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 477   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 478   IcrLow.Bits.Level = 1;
 479   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 480   SendIpi (IcrLow.Uint32, 0);
 481   MicroSecondDelay (200);
 482   SendIpi (IcrLow.Uint32, 0);
 483 }
 484
 485 /**
 486   Programming Virtual Wire Mode.
 487
 488   This function programs the local APIC for virtual wire mode following
 489   the example described in chapter A.3 of the MP 1.4 spec.
 490
 491   IOxAPIC is not involved in this type of virtual wire mode.
 492 **/
 493 VOID
 494 EFIAPI
 495 ProgramVirtualWireMode (
 496   VOID
 497   )
 498 {
 499   LOCAL_APIC_SVR      Svr;
 500   LOCAL_APIC_LVT_LINT Lint;
 501
 502   //
 503   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
 504   //
 505   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 506   Svr.Bits.SpuriousVector = 0xf;
 507   Svr.Bits.SoftwareEnable = 1;
 508   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 509
 510   //
 511   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
 512   //
 513   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 514   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
 515   Lint.Bits.InputPinPolarity = 0;
 516   Lint.Bits.TriggerMode = 0;
 517   Lint.Bits.Mask = 0;
 518   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
 519
 520   //
 521   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
 522   //
 523   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 524   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
 525   Lint.Bits.InputPinPolarity = 0;
 526   Lint.Bits.TriggerMode = 0;
 527   Lint.Bits.Mask = 0;
 528   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
 529 }
 530
 531 /**
 532   Disable LINT0 & LINT1 interrupts.
 533
 534   This function sets the mask flag in the LVT LINT0 & LINT1 registers.
 535 **/
 536 VOID
 537 EFIAPI
 538 DisableLvtInterrupts (
 539   VOID
 540   )
 541 {
 542   LOCAL_APIC_LVT_LINT LvtLint;
 543
 544   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 545   LvtLint.Bits.Mask = 1;
 546   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
 547
 548   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 549   LvtLint.Bits.Mask = 1;
 550   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
 551 }
 552
 553 /**
 554   Read the initial count value from the init-count register.
 555
 556   @return The initial count value read from the init-count register.
 557 **/
 558 UINT32
 559 EFIAPI
 560 GetApicTimerInitCount (
 561   VOID
 562   )
 563 {
 564   return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
 565 }
 566
 567 /**
 568   Read the current count value from the current-count register.
 569
 570   @return The current count value read from the current-count register.
 571 **/
 572 UINT32
 573 EFIAPI
 574 GetApicTimerCurrentCount (
 575   VOID
 576   )
 577 {
 578   return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
 579 }
 580
 581 /**
 582   Initialize the local APIC timer.
 583
 584   The local APIC timer is initialized and enabled.
 585
 586   @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 587                        If it is 0, then use the current divide value in the DCR.
 588   @param InitCount     The initial count value.
 589   @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 590   @param Vector        The timer interrupt vector number.
 591 **/
 592 VOID
 593 EFIAPI
 594 InitializeApicTimer (
 595   IN UINTN   DivideValue,
 596   IN UINT32  InitCount,
 597   IN BOOLEAN PeriodicMode,
 598   IN UINT8   Vector
 599   )
 600 {
 601   LOCAL_APIC_SVR       Svr;
 602   LOCAL_APIC_DCR       Dcr;
 603   LOCAL_APIC_LVT_TIMER LvtTimer;
 604   UINT32               Divisor;
 605
 606   //
 607   // Ensure local APIC is in software-enabled state.
 608   //
 609   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 610   Svr.Bits.SoftwareEnable = 1;
 611   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 612
 613   //
 614   // Program init-count register.
 615   //
 616   WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
 617
 618   if (DivideValue != 0) {
 619     ASSERT (DivideValue <= 128);
 620     ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
 621     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
 622
 623     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 624     Dcr.Bits.DivideValue1 = (Divisor & 0x3);
 625     Dcr.Bits.DivideValue2 = (Divisor >> 2);
 626     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
 627   }
 628
 629   //
 630   // Enable APIC timer interrupt with specified timer mode.
 631   //
 632   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 633   if (PeriodicMode) {
 634     LvtTimer.Bits.TimerMode = 1;
 635   } else {
 636     LvtTimer.Bits.TimerMode = 0;
 637   }
 638   LvtTimer.Bits.Mask = 0;
 639   LvtTimer.Bits.Vector = Vector;
 640   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 641 }
 642
 643 /**
 644   Get the state of the local APIC timer.
 645
 646   @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 647   @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 648   @param Vector        Return the timer interrupt vector number.
 649 **/
 650 VOID
 651 EFIAPI
 652 GetApicTimerState (
 653   OUT UINTN    *DivideValue  OPTIONAL,
 654   OUT BOOLEAN  *PeriodicMode  OPTIONAL,
 655   OUT UINT8    *Vector  OPTIONAL
 656   )
 657 {
 658   UINT32 Divisor;
 659   LOCAL_APIC_DCR Dcr;
 660   LOCAL_APIC_LVT_TIMER LvtTimer;
 661
 662   if (DivideValue != NULL) {
 663     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 664     Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
 665     Divisor = (Divisor + 1) & 0x7;
 666     *DivideValue = ((UINTN)1) << Divisor;
 667   }
 668
 669   if (PeriodicMode != NULL || Vector != NULL) {
 670     LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 671     if (PeriodicMode != NULL) {
 672       if (LvtTimer.Bits.TimerMode == 1) {
 673         *PeriodicMode = TRUE;
 674       } else {
 675         *PeriodicMode = FALSE;
 676       }
 677     }
 678     if (Vector != NULL) {
 679       *Vector = (UINT8) LvtTimer.Bits.Vector;
 680     }
 681   }
 682 }
 683
 684 /**
 685   Enable the local APIC timer interrupt.
 686 **/
 687 VOID
 688 EFIAPI
 689 EnableApicTimerInterrupt (
 690   VOID
 691   )
 692 {
 693   LOCAL_APIC_LVT_TIMER LvtTimer;
 694
 695   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 696   LvtTimer.Bits.Mask = 0;
 697   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 698 }
 699
 700 /**
 701   Disable the local APIC timer interrupt.
 702 **/
 703 VOID
 704 EFIAPI
 705 DisableApicTimerInterrupt (
 706   VOID
 707   )
 708 {
 709   LOCAL_APIC_LVT_TIMER LvtTimer;
 710
 711   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 712   LvtTimer.Bits.Mask = 1;
 713   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 714 }
 715
 716 /**
 717   Get the local APIC timer interrupt state.
 718
 719   @retval TRUE  The local APIC timer interrupt is enabled.
 720   @retval FALSE The local APIC timer interrupt is disabled.
 721 **/
 722 BOOLEAN
 723 EFIAPI
 724 GetApicTimerInterruptState (
 725   VOID
 726   )
 727 {
 728   LOCAL_APIC_LVT_TIMER LvtTimer;
 729
 730   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 731   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
 732 }
 733
 734 /**
 735   Send EOI to the local APIC.
 736 **/
 737 VOID
 738 EFIAPI
 739 SendApicEoi (
 740   VOID
 741   )
 742 {
 743   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
 744 }
 745
 746 /**
 747   Get the 32-bit address that a device should use to send a Message Signaled
 748   Interrupt (MSI) to the Local APIC of the currently executing processor.
 749
 750   @return 32-bit address used to send an MSI to the Local APIC.
 751 **/
 752 UINT32
 753 EFIAPI
 754 GetApicMsiAddress (
 755   VOID
 756   )
 757 {
 758   LOCAL_APIC_MSI_ADDRESS  MsiAddress;
 759
 760   //
 761   // Return address for an MSI interrupt to be delivered only to the APIC ID
 762   // of the currently executing processor.
 763   //
 764   MsiAddress.Uint32             = 0;
 765   MsiAddress.Bits.BaseAddress   = 0xFEE;
 766   MsiAddress.Bits.DestinationId = GetApicId ();
 767   return MsiAddress.Uint32;
 768 }
 769
 770 /**
 771   Get the 64-bit data value that a device should use to send a Message Signaled
 772   Interrupt (MSI) to the Local APIC of the currently executing processor.
 773
 774   If Vector is not in range 0x10..0xFE, then ASSERT().
 775   If DeliveryMode is not supported, then ASSERT().
 776
 777   @param  Vector          The 8-bit interrupt vector associated with the MSI.
 778                           Must be in the range 0x10..0xFE
 779   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
 780                           is handled.  The only supported values are:
 781                             0: LOCAL_APIC_DELIVERY_MODE_FIXED
 782                             1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
 783                             2: LOCAL_APIC_DELIVERY_MODE_SMI
 784                             4: LOCAL_APIC_DELIVERY_MODE_NMI
 785                             5: LOCAL_APIC_DELIVERY_MODE_INIT
 786                             7: LOCAL_APIC_DELIVERY_MODE_EXTINT
 787
 788   @param  LevelTriggered  TRUE specifies a level triggered interrupt.
 789                           FALSE specifies an edge triggered interrupt.
 790   @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
 791                           TRUE specifies a level triggered interrupt that active
 792                           when the interrupt line is asserted.
 793                           FALSE specifies a level triggered interrupt that active
 794                           when the interrupt line is deasserted.
 795
 796   @return 64-bit data value used to send an MSI to the Local APIC.
 797 **/
 798 UINT64
 799 EFIAPI
 800 GetApicMsiValue (
 801   IN UINT8    Vector,
 802   IN UINTN    DeliveryMode,
 803   IN BOOLEAN  LevelTriggered,
 804   IN BOOLEAN  AssertionLevel
 805   )
 806 {
 807   LOCAL_APIC_MSI_DATA  MsiData;
 808
 809   ASSERT (Vector >= 0x10 && Vector <= 0xFE);
 810   ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
 811
 812   MsiData.Uint64            = 0;
 813   MsiData.Bits.Vector       = Vector;
 814   MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
 815   if (LevelTriggered) {
 816     MsiData.Bits.TriggerMode = 1;
 817     if (AssertionLevel) {
 818       MsiData.Bits.Level = 1;
 819     }
 820   }
 821   return MsiData.Uint64;
 822 }