4 This local APIC library instance supports xAPIC mode only.
6 Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include <Register/Cpuid.h>
18 #include <Register/LocalApic.h>
20 #include <Library/BaseLib.h>
21 #include <Library/DebugLib.h>
22 #include <Library/LocalApicLib.h>
23 #include <Library/IoLib.h>
24 #include <Library/TimerLib.h>
25 #include <Library/PcdLib.h>
28 // Library internal functions
32 Determine if the CPU supports the Local APIC Base Address MSR.
34 @retval TRUE The CPU supports the Local APIC Base Address MSR.
35 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
39 LocalApicBaseAddressMsrSupported (
46 AsmCpuid (1, &RegEax
, NULL
, NULL
, NULL
);
47 FamilyId
= BitFieldRead32 (RegEax
, 8, 11);
48 if (FamilyId
== 0x04 || FamilyId
== 0x05) {
50 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
51 // Local APIC Base Address MSR
59 Retrieve the base address of local APIC.
61 @return The base address of local APIC.
66 GetLocalApicBaseAddress (
70 MSR_IA32_APIC_BASE ApicBaseMsr
;
72 if (!LocalApicBaseAddressMsrSupported ()) {
74 // If CPU does not support Local APIC Base Address MSR, then retrieve
75 // Local APIC Base Address from PCD
77 return PcdGet32 (PcdCpuLocalApicBaseAddress
);
80 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS
);
82 return (UINTN
)(LShiftU64 ((UINT64
) ApicBaseMsr
.Bits
.ApicBaseHigh
, 32)) +
83 (((UINTN
)ApicBaseMsr
.Bits
.ApicBaseLow
) << 12);
87 Set the base address of local APIC.
89 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
91 @param[in] BaseAddress Local APIC base address to be set.
96 SetLocalApicBaseAddress (
100 MSR_IA32_APIC_BASE ApicBaseMsr
;
102 ASSERT ((BaseAddress
& (SIZE_4KB
- 1)) == 0);
104 if (!LocalApicBaseAddressMsrSupported ()) {
106 // Ignore set request if the CPU does not support APIC Base Address MSR
111 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS
);
113 ApicBaseMsr
.Bits
.ApicBaseLow
= (UINT32
) (BaseAddress
>> 12);
114 ApicBaseMsr
.Bits
.ApicBaseHigh
= (UINT32
) (RShiftU64((UINT64
) BaseAddress
, 32));
116 AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS
, ApicBaseMsr
.Uint64
);
120 Read from a local APIC register.
122 This function reads from a local APIC register either in xAPIC or x2APIC mode.
123 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
124 accessed using multiple 32-bit loads or stores, so this function only performs
127 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
128 It must be 16-byte aligned.
130 @return 32-bit Value read from the register.
138 ASSERT ((MmioOffset
& 0xf) == 0);
139 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
141 return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset
);
145 Write to a local APIC register.
147 This function writes to a local APIC register either in xAPIC or x2APIC mode.
148 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
149 accessed using multiple 32-bit loads or stores, so this function only performs
152 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
154 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
155 It must be 16-byte aligned.
156 @param Value Value to be written to the register.
165 ASSERT ((MmioOffset
& 0xf) == 0);
166 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
168 MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset
, Value
);
172 Send an IPI by writing to ICR.
174 This function returns after the IPI has been accepted by the target processor.
176 @param IcrLow 32-bit value to be written to the low half of ICR.
177 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
185 LOCAL_APIC_ICR_LOW IcrLowReg
;
187 BOOLEAN InterruptState
;
189 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
190 ASSERT (ApicId
<= 0xff);
192 InterruptState
= SaveAndDisableInterrupts ();
195 // Save existing contents of ICR high 32 bits
197 IcrHigh
= ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET
);
200 // Wait for DeliveryStatus clear in case a previous IPI
201 // is still being sent
204 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
205 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
208 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
210 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, ApicId
<< 24);
211 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET
, IcrLow
);
214 // Wait for DeliveryStatus clear again
217 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
218 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
221 // And restore old contents of ICR high
223 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, IcrHigh
);
225 SetInterruptState (InterruptState
);
230 // Library API implementation functions
234 Get the current local APIC mode.
236 If local APIC is disabled, then ASSERT.
238 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
239 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
249 MSR_IA32_APIC_BASE ApicBaseMsr
;
252 // Check to see if the CPU supports the APIC Base Address MSR
254 if (LocalApicBaseAddressMsrSupported ()) {
255 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS
);
257 // Local APIC should have been enabled
259 ASSERT (ApicBaseMsr
.Bits
.En
!= 0);
260 ASSERT (ApicBaseMsr
.Bits
.Extd
== 0);
264 return LOCAL_APIC_MODE_XAPIC
;
268 Set the current local APIC mode.
270 If the specified local APIC mode is not valid, then ASSERT.
271 If the specified local APIC mode can't be set as current, then ASSERT.
273 @param ApicMode APIC mode to be set.
275 @note This API must not be called from an interrupt handler or SMI handler.
276 It may result in unpredictable behavior.
284 ASSERT (ApicMode
== LOCAL_APIC_MODE_XAPIC
);
285 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
289 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
291 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
292 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
293 the 32-bit local APIC ID is returned as initial APIC ID.
295 @return 32-bit initial local APIC ID of the executing processor.
304 UINT32 MaxCpuIdIndex
;
307 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
310 // Get the max index of basic CPUID
312 AsmCpuid (CPUID_SIGNATURE
, &MaxCpuIdIndex
, NULL
, NULL
, NULL
);
315 // If CPUID Leaf B is supported,
316 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
317 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
319 if (MaxCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
320 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY
, 0, NULL
, NULL
, NULL
, &ApicId
);
324 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &RegEbx
, NULL
, NULL
);
329 Get the local APIC ID of the executing processor.
331 @return 32-bit local APIC ID of the executing processor.
341 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
343 if ((ApicId
= GetInitialApicId ()) < 0x100) {
345 // If the initial local APIC ID is less 0x100, read APIC ID from
346 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
348 ApicId
= ReadLocalApicReg (XAPIC_ID_OFFSET
);
355 Get the value of the local APIC version register.
357 @return the value of the local APIC version register.
365 return ReadLocalApicReg (XAPIC_VERSION_OFFSET
);
369 Send a Fixed IPI to a specified target processor.
371 This function returns after the IPI has been accepted by the target processor.
373 @param ApicId The local APIC ID of the target processor.
374 @param Vector The vector number of the interrupt being sent.
383 LOCAL_APIC_ICR_LOW IcrLow
;
386 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
387 IcrLow
.Bits
.Level
= 1;
388 IcrLow
.Bits
.Vector
= Vector
;
389 SendIpi (IcrLow
.Uint32
, ApicId
);
393 Send a Fixed IPI to all processors excluding self.
395 This function returns after the IPI has been accepted by the target processors.
397 @param Vector The vector number of the interrupt being sent.
401 SendFixedIpiAllExcludingSelf (
405 LOCAL_APIC_ICR_LOW IcrLow
;
408 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
409 IcrLow
.Bits
.Level
= 1;
410 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
411 IcrLow
.Bits
.Vector
= Vector
;
412 SendIpi (IcrLow
.Uint32
, 0);
416 Send a SMI IPI to a specified target processor.
418 This function returns after the IPI has been accepted by the target processor.
420 @param ApicId Specify the local APIC ID of the target processor.
428 LOCAL_APIC_ICR_LOW IcrLow
;
431 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
432 IcrLow
.Bits
.Level
= 1;
433 SendIpi (IcrLow
.Uint32
, ApicId
);
437 Send a SMI IPI to all processors excluding self.
439 This function returns after the IPI has been accepted by the target processors.
443 SendSmiIpiAllExcludingSelf (
447 LOCAL_APIC_ICR_LOW IcrLow
;
450 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
451 IcrLow
.Bits
.Level
= 1;
452 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
453 SendIpi (IcrLow
.Uint32
, 0);
457 Send an INIT IPI to a specified target processor.
459 This function returns after the IPI has been accepted by the target processor.
461 @param ApicId Specify the local APIC ID of the target processor.
469 LOCAL_APIC_ICR_LOW IcrLow
;
472 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
473 IcrLow
.Bits
.Level
= 1;
474 SendIpi (IcrLow
.Uint32
, ApicId
);
478 Send an INIT IPI to all processors excluding self.
480 This function returns after the IPI has been accepted by the target processors.
484 SendInitIpiAllExcludingSelf (
488 LOCAL_APIC_ICR_LOW IcrLow
;
491 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
492 IcrLow
.Bits
.Level
= 1;
493 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
494 SendIpi (IcrLow
.Uint32
, 0);
498 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
500 This function returns after the IPI has been accepted by the target processor.
502 if StartupRoutine >= 1M, then ASSERT.
503 if StartupRoutine is not multiple of 4K, then ASSERT.
505 @param ApicId Specify the local APIC ID of the target processor.
506 @param StartupRoutine Points to a start-up routine which is below 1M physical
507 address and 4K aligned.
513 IN UINT32 StartupRoutine
516 LOCAL_APIC_ICR_LOW IcrLow
;
518 ASSERT (StartupRoutine
< 0x100000);
519 ASSERT ((StartupRoutine
& 0xfff) == 0);
521 SendInitIpi (ApicId
);
522 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
524 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
525 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
526 IcrLow
.Bits
.Level
= 1;
527 SendIpi (IcrLow
.Uint32
, ApicId
);
528 MicroSecondDelay (200);
529 SendIpi (IcrLow
.Uint32
, ApicId
);
533 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
535 This function returns after the IPI has been accepted by the target processors.
537 if StartupRoutine >= 1M, then ASSERT.
538 if StartupRoutine is not multiple of 4K, then ASSERT.
540 @param StartupRoutine Points to a start-up routine which is below 1M physical
541 address and 4K aligned.
545 SendInitSipiSipiAllExcludingSelf (
546 IN UINT32 StartupRoutine
549 LOCAL_APIC_ICR_LOW IcrLow
;
551 ASSERT (StartupRoutine
< 0x100000);
552 ASSERT ((StartupRoutine
& 0xfff) == 0);
554 SendInitIpiAllExcludingSelf ();
555 MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds
));
557 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
558 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
559 IcrLow
.Bits
.Level
= 1;
560 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
561 SendIpi (IcrLow
.Uint32
, 0);
562 MicroSecondDelay (200);
563 SendIpi (IcrLow
.Uint32
, 0);
567 Programming Virtual Wire Mode.
569 This function programs the local APIC for virtual wire mode following
570 the example described in chapter A.3 of the MP 1.4 spec.
572 IOxAPIC is not involved in this type of virtual wire mode.
576 ProgramVirtualWireMode (
581 LOCAL_APIC_LVT_LINT Lint
;
584 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
586 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
587 Svr
.Bits
.SpuriousVector
= 0xf;
588 Svr
.Bits
.SoftwareEnable
= 1;
589 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
592 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
594 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
595 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_EXTINT
;
596 Lint
.Bits
.InputPinPolarity
= 0;
597 Lint
.Bits
.TriggerMode
= 0;
599 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, Lint
.Uint32
);
602 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
604 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
605 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_NMI
;
606 Lint
.Bits
.InputPinPolarity
= 0;
607 Lint
.Bits
.TriggerMode
= 0;
609 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, Lint
.Uint32
);
613 Disable LINT0 & LINT1 interrupts.
615 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
619 DisableLvtInterrupts (
623 LOCAL_APIC_LVT_LINT LvtLint
;
625 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
626 LvtLint
.Bits
.Mask
= 1;
627 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, LvtLint
.Uint32
);
629 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
630 LvtLint
.Bits
.Mask
= 1;
631 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, LvtLint
.Uint32
);
635 Read the initial count value from the init-count register.
637 @return The initial count value read from the init-count register.
641 GetApicTimerInitCount (
645 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
);
649 Read the current count value from the current-count register.
651 @return The current count value read from the current-count register.
655 GetApicTimerCurrentCount (
659 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET
);
663 Initialize the local APIC timer.
665 The local APIC timer is initialized and enabled.
667 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
668 If it is 0, then use the current divide value in the DCR.
669 @param InitCount The initial count value.
670 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
671 @param Vector The timer interrupt vector number.
675 InitializeApicTimer (
676 IN UINTN DivideValue
,
678 IN BOOLEAN PeriodicMode
,
684 LOCAL_APIC_LVT_TIMER LvtTimer
;
688 // Ensure local APIC is in software-enabled state.
690 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
691 Svr
.Bits
.SoftwareEnable
= 1;
692 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
695 // Program init-count register.
697 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
, InitCount
);
699 if (DivideValue
!= 0) {
700 ASSERT (DivideValue
<= 128);
701 ASSERT (DivideValue
== GetPowerOfTwo32((UINT32
)DivideValue
));
702 Divisor
= (UINT32
)((HighBitSet32 ((UINT32
)DivideValue
) - 1) & 0x7);
704 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
705 Dcr
.Bits
.DivideValue1
= (Divisor
& 0x3);
706 Dcr
.Bits
.DivideValue2
= (Divisor
>> 2);
707 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
, Dcr
.Uint32
);
711 // Enable APIC timer interrupt with specified timer mode.
713 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
715 LvtTimer
.Bits
.TimerMode
= 1;
717 LvtTimer
.Bits
.TimerMode
= 0;
719 LvtTimer
.Bits
.Mask
= 0;
720 LvtTimer
.Bits
.Vector
= Vector
;
721 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
725 Get the state of the local APIC timer.
727 This function will ASSERT if the local APIC is not software enabled.
729 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
730 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
731 @param Vector Return the timer interrupt vector number.
736 OUT UINTN
*DivideValue OPTIONAL
,
737 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
738 OUT UINT8
*Vector OPTIONAL
743 LOCAL_APIC_LVT_TIMER LvtTimer
;
746 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
748 // This bit will be 1, if local APIC is software enabled.
750 ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET
) & BIT8
) != 0);
752 if (DivideValue
!= NULL
) {
753 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
754 Divisor
= Dcr
.Bits
.DivideValue1
| (Dcr
.Bits
.DivideValue2
<< 2);
755 Divisor
= (Divisor
+ 1) & 0x7;
756 *DivideValue
= ((UINTN
)1) << Divisor
;
759 if (PeriodicMode
!= NULL
|| Vector
!= NULL
) {
760 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
761 if (PeriodicMode
!= NULL
) {
762 if (LvtTimer
.Bits
.TimerMode
== 1) {
763 *PeriodicMode
= TRUE
;
765 *PeriodicMode
= FALSE
;
768 if (Vector
!= NULL
) {
769 *Vector
= (UINT8
) LvtTimer
.Bits
.Vector
;
775 Enable the local APIC timer interrupt.
779 EnableApicTimerInterrupt (
783 LOCAL_APIC_LVT_TIMER LvtTimer
;
785 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
786 LvtTimer
.Bits
.Mask
= 0;
787 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
791 Disable the local APIC timer interrupt.
795 DisableApicTimerInterrupt (
799 LOCAL_APIC_LVT_TIMER LvtTimer
;
801 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
802 LvtTimer
.Bits
.Mask
= 1;
803 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
807 Get the local APIC timer interrupt state.
809 @retval TRUE The local APIC timer interrupt is enabled.
810 @retval FALSE The local APIC timer interrupt is disabled.
814 GetApicTimerInterruptState (
818 LOCAL_APIC_LVT_TIMER LvtTimer
;
820 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
821 return (BOOLEAN
)(LvtTimer
.Bits
.Mask
== 0);
825 Send EOI to the local APIC.
833 WriteLocalApicReg (XAPIC_EOI_OFFSET
, 0);
837 Get the 32-bit address that a device should use to send a Message Signaled
838 Interrupt (MSI) to the Local APIC of the currently executing processor.
840 @return 32-bit address used to send an MSI to the Local APIC.
848 LOCAL_APIC_MSI_ADDRESS MsiAddress
;
851 // Return address for an MSI interrupt to be delivered only to the APIC ID
852 // of the currently executing processor.
854 MsiAddress
.Uint32
= 0;
855 MsiAddress
.Bits
.BaseAddress
= 0xFEE;
856 MsiAddress
.Bits
.DestinationId
= GetApicId ();
857 return MsiAddress
.Uint32
;
861 Get the 64-bit data value that a device should use to send a Message Signaled
862 Interrupt (MSI) to the Local APIC of the currently executing processor.
864 If Vector is not in range 0x10..0xFE, then ASSERT().
865 If DeliveryMode is not supported, then ASSERT().
867 @param Vector The 8-bit interrupt vector associated with the MSI.
868 Must be in the range 0x10..0xFE
869 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
870 is handled. The only supported values are:
871 0: LOCAL_APIC_DELIVERY_MODE_FIXED
872 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
873 2: LOCAL_APIC_DELIVERY_MODE_SMI
874 4: LOCAL_APIC_DELIVERY_MODE_NMI
875 5: LOCAL_APIC_DELIVERY_MODE_INIT
876 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
878 @param LevelTriggered TRUE specifies a level triggered interrupt.
879 FALSE specifies an edge triggered interrupt.
880 @param AssertionLevel Ignored if LevelTriggered is FALSE.
881 TRUE specifies a level triggered interrupt that active
882 when the interrupt line is asserted.
883 FALSE specifies a level triggered interrupt that active
884 when the interrupt line is deasserted.
886 @return 64-bit data value used to send an MSI to the Local APIC.
892 IN UINTN DeliveryMode
,
893 IN BOOLEAN LevelTriggered
,
894 IN BOOLEAN AssertionLevel
897 LOCAL_APIC_MSI_DATA MsiData
;
899 ASSERT (Vector
>= 0x10 && Vector
<= 0xFE);
900 ASSERT (DeliveryMode
< 8 && DeliveryMode
!= 6 && DeliveryMode
!= 3);
903 MsiData
.Bits
.Vector
= Vector
;
904 MsiData
.Bits
.DeliveryMode
= (UINT32
)DeliveryMode
;
905 if (LevelTriggered
) {
906 MsiData
.Bits
.TriggerMode
= 1;
907 if (AssertionLevel
) {
908 MsiData
.Bits
.Level
= 1;
911 return MsiData
.Uint64
;