UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c

   1 /** @file
   2   Local APIC Library.
   3
   4   This local APIC library instance supports xAPIC mode only.
   5
   6   Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
   7   This program and the accompanying materials
   8   are licensed and made available under the terms and conditions of the BSD License
   9   which accompanies this distribution.  The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include <Register/LocalApic.h>
  18
  19 #include <Library/BaseLib.h>
  20 #include <Library/DebugLib.h>
  21 #include <Library/LocalApicLib.h>
  22 #include <Library/IoLib.h>
  23 #include <Library/TimerLib.h>
  24
  25 //
  26 // Library internal functions
  27 //
  28
  29 /**
  30   Retrieve the base address of local APIC.
  31
  32   @return The base address of local APIC.
  33
  34 **/
  35 UINTN
  36 EFIAPI
  37 GetLocalApicBaseAddress (
  38   VOID
  39   )
  40 {
  41   MSR_IA32_APIC_BASE ApicBaseMsr;
  42
  43   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  44
  45   return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
  46            (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
  47 }
  48
  49 /**
  50   Set the base address of local APIC.
  51
  52   If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
  53
  54   @param[in] BaseAddress   Local APIC base address to be set.
  55
  56 **/
  57 VOID
  58 EFIAPI
  59 SetLocalApicBaseAddress (
  60   IN UINTN                BaseAddress
  61   )
  62 {
  63   MSR_IA32_APIC_BASE ApicBaseMsr;
  64
  65   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
  66
  67   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  68
  69   ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
  70   ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
  71
  72   AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
  73 }
  74
  75 /**
  76   Read from a local APIC register.
  77
  78   This function reads from a local APIC register either in xAPIC or x2APIC mode.
  79   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  80   accessed using multiple 32-bit loads or stores, so this function only performs
  81   32-bit read.
  82
  83   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
  84                       It must be 16-byte aligned.
  85
  86   @return 32-bit      Value read from the register.
  87 **/
  88 UINT32
  89 EFIAPI
  90 ReadLocalApicReg (
  91   IN UINTN  MmioOffset
  92   )
  93 {
  94   ASSERT ((MmioOffset & 0xf) == 0);
  95   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
  96
  97   return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
  98 }
  99
 100 /**
 101   Write to a local APIC register.
 102
 103   This function writes to a local APIC register either in xAPIC or x2APIC mode.
 104   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
 105   accessed using multiple 32-bit loads or stores, so this function only performs
 106   32-bit write.
 107
 108   if the register index is invalid or unsupported in current APIC mode, then ASSERT.
 109
 110   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
 111                       It must be 16-byte aligned.
 112   @param  Value       Value to be written to the register.
 113 **/
 114 VOID
 115 EFIAPI
 116 WriteLocalApicReg (
 117   IN UINTN  MmioOffset,
 118   IN UINT32 Value
 119   )
 120 {
 121   ASSERT ((MmioOffset & 0xf) == 0);
 122   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 123
 124   MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
 125 }
 126
 127 /**
 128   Send an IPI by writing to ICR.
 129
 130   This function returns after the IPI has been accepted by the target processor.
 131
 132   @param  IcrLow 32-bit value to be written to the low half of ICR.
 133   @param  ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
 134 **/
 135 VOID
 136 SendIpi (
 137   IN UINT32          IcrLow,
 138   IN UINT32          ApicId
 139   )
 140 {
 141   LOCAL_APIC_ICR_LOW IcrLowReg;
 142
 143   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 144   ASSERT (ApicId <= 0xff);
 145
 146   //
 147   // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
 148   //
 149   WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
 150   WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);
 151   do {
 152     IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);
 153   } while (IcrLowReg.Bits.DeliveryStatus != 0);
 154 }
 155
 156 //
 157 // Library API implementation functions
 158 //
 159
 160 /**
 161   Get the current local APIC mode.
 162
 163   If local APIC is disabled, then ASSERT.
 164
 165   @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.
 166   @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
 167 **/
 168 UINTN
 169 EFIAPI
 170 GetApicMode (
 171   VOID
 172   )
 173 {
 174   DEBUG_CODE (
 175     {
 176       MSR_IA32_APIC_BASE ApicBaseMsr;
 177
 178       ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 179       //
 180       // Local APIC should have been enabled
 181       //
 182       ASSERT (ApicBaseMsr.Bits.En != 0);
 183       ASSERT (ApicBaseMsr.Bits.Extd == 0);
 184     }
 185   );
 186   return LOCAL_APIC_MODE_XAPIC;
 187 }
 188
 189 /**
 190   Set the current local APIC mode.
 191
 192   If the specified local APIC mode is not valid, then ASSERT.
 193   If the specified local APIC mode can't be set as current, then ASSERT.
 194
 195   @param ApicMode APIC mode to be set.
 196 **/
 197 VOID
 198 EFIAPI
 199 SetApicMode (
 200   IN UINTN  ApicMode
 201   )
 202 {
 203   ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);
 204   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 205 }
 206
 207 /**
 208   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
 209
 210   In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
 211   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
 212   the 32-bit local APIC ID is returned as initial APIC ID.
 213
 214   @return  32-bit initial local APIC ID of the executing processor.
 215 **/
 216 UINT32
 217 EFIAPI
 218 GetInitialApicId (
 219   VOID
 220   )
 221 {
 222   UINT32 RegEbx;
 223
 224   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 225
 226   AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
 227   return RegEbx >> 24;
 228 }
 229
 230 /**
 231   Get the local APIC ID of the executing processor.
 232
 233   @return  32-bit local APIC ID of the executing processor.
 234 **/
 235 UINT32
 236 EFIAPI
 237 GetApicId (
 238   VOID
 239   )
 240 {
 241   UINT32 ApicId;
 242
 243   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
 244
 245   ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
 246   ApicId >>= 24;
 247   return ApicId;
 248 }
 249
 250 /**
 251   Get the value of the local APIC version register.
 252
 253   @return  the value of the local APIC version register.
 254 **/
 255 UINT32
 256 EFIAPI
 257 GetApicVersion (
 258   VOID
 259   )
 260 {
 261   return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
 262 }
 263
 264 /**
 265   Send a Fixed IPI to a specified target processor.
 266
 267   This function returns after the IPI has been accepted by the target processor.
 268
 269   @param  ApicId   The local APIC ID of the target processor.
 270   @param  Vector   The vector number of the interrupt being sent.
 271 **/
 272 VOID
 273 EFIAPI
 274 SendFixedIpi (
 275   IN UINT32          ApicId,
 276   IN UINT8           Vector
 277   )
 278 {
 279   LOCAL_APIC_ICR_LOW IcrLow;
 280
 281   IcrLow.Uint32 = 0;
 282   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 283   IcrLow.Bits.Level = 1;
 284   IcrLow.Bits.Vector = Vector;
 285   SendIpi (IcrLow.Uint32, ApicId);
 286 }
 287
 288 /**
 289   Send a Fixed IPI to all processors excluding self.
 290
 291   This function returns after the IPI has been accepted by the target processors.
 292
 293   @param  Vector   The vector number of the interrupt being sent.
 294 **/
 295 VOID
 296 EFIAPI
 297 SendFixedIpiAllExcludingSelf (
 298   IN UINT8           Vector
 299   )
 300 {
 301   LOCAL_APIC_ICR_LOW IcrLow;
 302
 303   IcrLow.Uint32 = 0;
 304   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 305   IcrLow.Bits.Level = 1;
 306   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 307   IcrLow.Bits.Vector = Vector;
 308   SendIpi (IcrLow.Uint32, 0);
 309 }
 310
 311 /**
 312   Send a SMI IPI to a specified target processor.
 313
 314   This function returns after the IPI has been accepted by the target processor.
 315
 316   @param  ApicId   Specify the local APIC ID of the target processor.
 317 **/
 318 VOID
 319 EFIAPI
 320 SendSmiIpi (
 321   IN UINT32          ApicId
 322   )
 323 {
 324   LOCAL_APIC_ICR_LOW IcrLow;
 325
 326   IcrLow.Uint32 = 0;
 327   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 328   IcrLow.Bits.Level = 1;
 329   SendIpi (IcrLow.Uint32, ApicId);
 330 }
 331
 332 /**
 333   Send a SMI IPI to all processors excluding self.
 334
 335   This function returns after the IPI has been accepted by the target processors.
 336 **/
 337 VOID
 338 EFIAPI
 339 SendSmiIpiAllExcludingSelf (
 340   VOID
 341   )
 342 {
 343   LOCAL_APIC_ICR_LOW IcrLow;
 344
 345   IcrLow.Uint32 = 0;
 346   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 347   IcrLow.Bits.Level = 1;
 348   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 349   SendIpi (IcrLow.Uint32, 0);
 350 }
 351
 352 /**
 353   Send an INIT IPI to a specified target processor.
 354
 355   This function returns after the IPI has been accepted by the target processor.
 356
 357   @param  ApicId   Specify the local APIC ID of the target processor.
 358 **/
 359 VOID
 360 EFIAPI
 361 SendInitIpi (
 362   IN UINT32          ApicId
 363   )
 364 {
 365   LOCAL_APIC_ICR_LOW IcrLow;
 366
 367   IcrLow.Uint32 = 0;
 368   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 369   IcrLow.Bits.Level = 1;
 370   SendIpi (IcrLow.Uint32, ApicId);
 371 }
 372
 373 /**
 374   Send an INIT IPI to all processors excluding self.
 375
 376   This function returns after the IPI has been accepted by the target processors.
 377 **/
 378 VOID
 379 EFIAPI
 380 SendInitIpiAllExcludingSelf (
 381   VOID
 382   )
 383 {
 384   LOCAL_APIC_ICR_LOW IcrLow;
 385
 386   IcrLow.Uint32 = 0;
 387   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 388   IcrLow.Bits.Level = 1;
 389   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 390   SendIpi (IcrLow.Uint32, 0);
 391 }
 392
 393 /**
 394   Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
 395
 396   This function returns after the IPI has been accepted by the target processor.
 397
 398   if StartupRoutine >= 1M, then ASSERT.
 399   if StartupRoutine is not multiple of 4K, then ASSERT.
 400
 401   @param  ApicId          Specify the local APIC ID of the target processor.
 402   @param  StartupRoutine  Points to a start-up routine which is below 1M physical
 403                           address and 4K aligned.
 404 **/
 405 VOID
 406 EFIAPI
 407 SendInitSipiSipi (
 408   IN UINT32          ApicId,
 409   IN UINT32          StartupRoutine
 410   )
 411 {
 412   LOCAL_APIC_ICR_LOW IcrLow;
 413
 414   ASSERT (StartupRoutine < 0x100000);
 415   ASSERT ((StartupRoutine & 0xfff) == 0);
 416
 417   SendInitIpi (ApicId);
 418   MicroSecondDelay (10);
 419   IcrLow.Uint32 = 0;
 420   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 421   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 422   IcrLow.Bits.Level = 1;
 423   SendIpi (IcrLow.Uint32, ApicId);
 424   MicroSecondDelay (200);
 425   SendIpi (IcrLow.Uint32, ApicId);
 426 }
 427
 428 /**
 429   Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
 430
 431   This function returns after the IPI has been accepted by the target processors.
 432
 433   if StartupRoutine >= 1M, then ASSERT.
 434   if StartupRoutine is not multiple of 4K, then ASSERT.
 435
 436   @param  StartupRoutine    Points to a start-up routine which is below 1M physical
 437                             address and 4K aligned.
 438 **/
 439 VOID
 440 EFIAPI
 441 SendInitSipiSipiAllExcludingSelf (
 442   IN UINT32          StartupRoutine
 443   )
 444 {
 445   LOCAL_APIC_ICR_LOW IcrLow;
 446
 447   ASSERT (StartupRoutine < 0x100000);
 448   ASSERT ((StartupRoutine & 0xfff) == 0);
 449
 450   SendInitIpiAllExcludingSelf ();
 451   MicroSecondDelay (10);
 452   IcrLow.Uint32 = 0;
 453   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 454   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 455   IcrLow.Bits.Level = 1;
 456   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 457   SendIpi (IcrLow.Uint32, 0);
 458   MicroSecondDelay (200);
 459   SendIpi (IcrLow.Uint32, 0);
 460 }
 461
 462 /**
 463   Programming Virtual Wire Mode.
 464
 465   This function programs the local APIC for virtual wire mode following
 466   the example described in chapter A.3 of the MP 1.4 spec.
 467
 468   IOxAPIC is not involved in this type of virtual wire mode.
 469 **/
 470 VOID
 471 EFIAPI
 472 ProgramVirtualWireMode (
 473   VOID
 474   )
 475 {
 476   LOCAL_APIC_SVR      Svr;
 477   LOCAL_APIC_LVT_LINT Lint;
 478
 479   //
 480   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
 481   //
 482   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 483   Svr.Bits.SpuriousVector = 0xf;
 484   Svr.Bits.SoftwareEnable = 1;
 485   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 486
 487   //
 488   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
 489   //
 490   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 491   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
 492   Lint.Bits.InputPinPolarity = 0;
 493   Lint.Bits.TriggerMode = 0;
 494   Lint.Bits.Mask = 0;
 495   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
 496
 497   //
 498   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
 499   //
 500   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 501   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
 502   Lint.Bits.InputPinPolarity = 0;
 503   Lint.Bits.TriggerMode = 0;
 504   Lint.Bits.Mask = 0;
 505   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
 506 }
 507
 508 /**
 509   Disable LINT0 & LINT1 interrupts.
 510
 511   This function sets the mask flag in the LVT LINT0 & LINT1 registers.
 512 **/
 513 VOID
 514 EFIAPI
 515 DisableLvtInterrupts (
 516   VOID
 517   )
 518 {
 519   LOCAL_APIC_LVT_LINT LvtLint;
 520
 521   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 522   LvtLint.Bits.Mask = 1;
 523   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
 524
 525   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 526   LvtLint.Bits.Mask = 1;
 527   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
 528 }
 529
 530 /**
 531   Read the initial count value from the init-count register.
 532
 533   @return The initial count value read from the init-count register.
 534 **/
 535 UINT32
 536 EFIAPI
 537 GetApicTimerInitCount (
 538   VOID
 539   )
 540 {
 541   return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
 542 }
 543
 544 /**
 545   Read the current count value from the current-count register.
 546
 547   @return The current count value read from the current-count register.
 548 **/
 549 UINT32
 550 EFIAPI
 551 GetApicTimerCurrentCount (
 552   VOID
 553   )
 554 {
 555   return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
 556 }
 557
 558 /**
 559   Initialize the local APIC timer.
 560
 561   The local APIC timer is initialized and enabled.
 562
 563   @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 564                        If it is 0, then use the current divide value in the DCR.
 565   @param InitCount     The initial count value.
 566   @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 567   @param Vector        The timer interrupt vector number.
 568 **/
 569 VOID
 570 EFIAPI
 571 InitializeApicTimer (
 572   IN UINTN   DivideValue,
 573   IN UINT32  InitCount,
 574   IN BOOLEAN PeriodicMode,
 575   IN UINT8   Vector
 576   )
 577 {
 578   LOCAL_APIC_SVR       Svr;
 579   LOCAL_APIC_DCR       Dcr;
 580   LOCAL_APIC_LVT_TIMER LvtTimer;
 581   UINT32               Divisor;
 582
 583   //
 584   // Ensure local APIC is in software-enabled state.
 585   //
 586   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 587   Svr.Bits.SoftwareEnable = 1;
 588   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 589
 590   //
 591   // Program init-count register.
 592   //
 593   WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
 594
 595   if (DivideValue != 0) {
 596     ASSERT (DivideValue <= 128);
 597     ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
 598     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
 599
 600     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 601     Dcr.Bits.DivideValue1 = (Divisor & 0x3);
 602     Dcr.Bits.DivideValue2 = (Divisor >> 2);
 603     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
 604   }
 605
 606   //
 607   // Enable APIC timer interrupt with specified timer mode.
 608   //
 609   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 610   if (PeriodicMode) {
 611     LvtTimer.Bits.TimerMode = 1;
 612   } else {
 613     LvtTimer.Bits.TimerMode = 0;
 614   }
 615   LvtTimer.Bits.Mask = 0;
 616   LvtTimer.Bits.Vector = Vector;
 617   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 618 }
 619
 620 /**
 621   Get the state of the local APIC timer.
 622
 623   @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 624   @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 625   @param Vector        Return the timer interrupt vector number.
 626 **/
 627 VOID
 628 EFIAPI
 629 GetApicTimerState (
 630   OUT UINTN    *DivideValue  OPTIONAL,
 631   OUT BOOLEAN  *PeriodicMode  OPTIONAL,
 632   OUT UINT8    *Vector  OPTIONAL
 633   )
 634 {
 635   UINT32 Divisor;
 636   LOCAL_APIC_DCR Dcr;
 637   LOCAL_APIC_LVT_TIMER LvtTimer;
 638
 639   if (DivideValue != NULL) {
 640     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 641     Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
 642     Divisor = (Divisor + 1) & 0x7;
 643     *DivideValue = ((UINTN)1) << Divisor;
 644   }
 645
 646   if (PeriodicMode != NULL || Vector != NULL) {
 647     LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 648     if (PeriodicMode != NULL) {
 649       if (LvtTimer.Bits.TimerMode == 1) {
 650         *PeriodicMode = TRUE;
 651       } else {
 652         *PeriodicMode = FALSE;
 653       }
 654     }
 655     if (Vector != NULL) {
 656       *Vector = (UINT8) LvtTimer.Bits.Vector;
 657     }
 658   }
 659 }
 660
 661 /**
 662   Enable the local APIC timer interrupt.
 663 **/
 664 VOID
 665 EFIAPI
 666 EnableApicTimerInterrupt (
 667   VOID
 668   )
 669 {
 670   LOCAL_APIC_LVT_TIMER LvtTimer;
 671
 672   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 673   LvtTimer.Bits.Mask = 0;
 674   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 675 }
 676
 677 /**
 678   Disable the local APIC timer interrupt.
 679 **/
 680 VOID
 681 EFIAPI
 682 DisableApicTimerInterrupt (
 683   VOID
 684   )
 685 {
 686   LOCAL_APIC_LVT_TIMER LvtTimer;
 687
 688   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 689   LvtTimer.Bits.Mask = 1;
 690   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 691 }
 692
 693 /**
 694   Get the local APIC timer interrupt state.
 695
 696   @retval TRUE  The local APIC timer interrupt is enabled.
 697   @retval FALSE The local APIC timer interrupt is disabled.
 698 **/
 699 BOOLEAN
 700 EFIAPI
 701 GetApicTimerInterruptState (
 702   VOID
 703   )
 704 {
 705   LOCAL_APIC_LVT_TIMER LvtTimer;
 706
 707   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 708   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
 709 }
 710
 711 /**
 712   Send EOI to the local APIC.
 713 **/
 714 VOID
 715 EFIAPI
 716 SendApicEoi (
 717   VOID
 718   )
 719 {
 720   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
 721 }
 722
 723 /**
 724   Get the 32-bit address that a device should use to send a Message Signaled
 725   Interrupt (MSI) to the Local APIC of the currently executing processor.
 726
 727   @return 32-bit address used to send an MSI to the Local APIC.
 728 **/
 729 UINT32
 730 EFIAPI
 731 GetApicMsiAddress (
 732   VOID
 733   )
 734 {
 735   LOCAL_APIC_MSI_ADDRESS  MsiAddress;
 736
 737   //
 738   // Return address for an MSI interrupt to be delivered only to the APIC ID
 739   // of the currently executing processor.
 740   //
 741   MsiAddress.Uint32             = 0;
 742   MsiAddress.Bits.BaseAddress   = 0xFEE;
 743   MsiAddress.Bits.DestinationId = GetApicId ();
 744   return MsiAddress.Uint32;
 745 }
 746
 747 /**
 748   Get the 64-bit data value that a device should use to send a Message Signaled
 749   Interrupt (MSI) to the Local APIC of the currently executing processor.
 750
 751   If Vector is not in range 0x10..0xFE, then ASSERT().
 752   If DeliveryMode is not supported, then ASSERT().
 753
 754   @param  Vector          The 8-bit interrupt vector associated with the MSI.
 755                           Must be in the range 0x10..0xFE
 756   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
 757                           is handled.  The only supported values are:
 758                             0: LOCAL_APIC_DELIVERY_MODE_FIXED
 759                             1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
 760                             2: LOCAL_APIC_DELIVERY_MODE_SMI
 761                             4: LOCAL_APIC_DELIVERY_MODE_NMI
 762                             5: LOCAL_APIC_DELIVERY_MODE_INIT
 763                             7: LOCAL_APIC_DELIVERY_MODE_EXTINT
 764
 765   @param  LevelTriggered  TRUE specifies a level triggered interrupt.
 766                           FALSE specifies an edge triggered interrupt.
 767   @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
 768                           TRUE specifies a level triggered interrupt that active
 769                           when the interrupt line is asserted.
 770                           FALSE specifies a level triggered interrupt that active
 771                           when the interrupt line is deasserted.
 772
 773   @return 64-bit data value used to send an MSI to the Local APIC.
 774 **/
 775 UINT64
 776 EFIAPI
 777 GetApicMsiValue (
 778   IN UINT8    Vector,
 779   IN UINTN    DeliveryMode,
 780   IN BOOLEAN  LevelTriggered,
 781   IN BOOLEAN  AssertionLevel
 782   )
 783 {
 784   LOCAL_APIC_MSI_DATA  MsiData;
 785
 786   ASSERT (Vector >= 0x10 && Vector <= 0xFE);
 787   ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
 788
 789   MsiData.Uint64            = 0;
 790   MsiData.Bits.Vector       = Vector;
 791   MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
 792   if (LevelTriggered) {
 793     MsiData.Bits.TriggerMode = 1;
 794     if (AssertionLevel) {
 795       MsiData.Bits.Level = 1;
 796     }
 797   }
 798   return MsiData.Uint64;
 799 }