UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c

   1 /** @file
   2   Local APIC Library.
   3
   4   This local APIC library instance supports x2APIC capable processors
   5   which have xAPIC and x2APIC modes.
   6
   7   Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
   8   This program and the accompanying materials
   9   are licensed and made available under the terms and conditions of the BSD License
  10   which accompanies this distribution.  The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17
  18 #include <Register/LocalApic.h>
  19
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/LocalApicLib.h>
  23 #include <Library/IoLib.h>
  24 #include <Library/TimerLib.h>
  25
  26 //
  27 // Library internal functions
  28 //
  29
  30 /**
  31   Retrieve the base address of local APIC.
  32
  33   @return The base address of local APIC.
  34
  35 **/
  36 UINTN
  37 EFIAPI
  38 GetLocalApicBaseAddress (
  39   VOID
  40   )
  41 {
  42   MSR_IA32_APIC_BASE ApicBaseMsr;
  43
  44   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  45
  46   return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
  47            (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
  48 }
  49
  50 /**
  51   Set the base address of local APIC.
  52
  53   If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
  54
  55   @param[in] BaseAddress   Local APIC base address to be set.
  56
  57 **/
  58 VOID
  59 EFIAPI
  60 SetLocalApicBaseAddress (
  61   IN UINTN                BaseAddress
  62   )
  63 {
  64   MSR_IA32_APIC_BASE ApicBaseMsr;
  65
  66   ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
  67
  68   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
  69
  70   ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
  71   ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
  72
  73   AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
  74 }
  75
  76 /**
  77   Read from a local APIC register.
  78
  79   This function reads from a local APIC register either in xAPIC or x2APIC mode.
  80   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
  81   accessed using multiple 32-bit loads or stores, so this function only performs
  82   32-bit read.
  83
  84   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
  85                       It must be 16-byte aligned.
  86
  87   @return 32-bit      Value read from the register.
  88 **/
  89 UINT32
  90 EFIAPI
  91 ReadLocalApicReg (
  92   IN UINTN  MmioOffset
  93   )
  94 {
  95   UINT32 MsrIndex;
  96
  97   ASSERT ((MmioOffset & 0xf) == 0);
  98
  99   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
 100     return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
 101   } else {
 102     //
 103     // DFR is not supported in x2APIC mode.
 104     //
 105     ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
 106     //
 107     // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
 108     // is not supported in this function for simplicity.
 109     //
 110     ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
 111
 112     MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
 113     return AsmReadMsr32 (MsrIndex);
 114   }
 115 }
 116
 117 /**
 118   Write to a local APIC register.
 119
 120   This function writes to a local APIC register either in xAPIC or x2APIC mode.
 121   It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
 122   accessed using multiple 32-bit loads or stores, so this function only performs
 123   32-bit write.
 124
 125   if the register index is invalid or unsupported in current APIC mode, then ASSERT.
 126
 127   @param  MmioOffset  The MMIO offset of the local APIC register in xAPIC mode.
 128                       It must be 16-byte aligned.
 129   @param  Value       Value to be written to the register.
 130 **/
 131 VOID
 132 EFIAPI
 133 WriteLocalApicReg (
 134   IN UINTN  MmioOffset,
 135   IN UINT32 Value
 136   )
 137 {
 138   UINT32 MsrIndex;
 139
 140   ASSERT ((MmioOffset & 0xf) == 0);
 141
 142   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
 143     MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
 144   } else {
 145     //
 146     // DFR is not supported in x2APIC mode.
 147     //
 148     ASSERT (MmioOffset != XAPIC_ICR_DFR_OFFSET);
 149     //
 150     // Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
 151     // is not supported in this function for simplicity.
 152     //
 153     ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
 154     ASSERT (MmioOffset != XAPIC_ICR_LOW_OFFSET);
 155
 156     MsrIndex =  (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
 157     //
 158     // The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
 159     // Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
 160     //
 161     MemoryFence ();
 162     AsmWriteMsr32 (MsrIndex, Value);
 163   }
 164 }
 165
 166 /**
 167   Send an IPI by writing to ICR.
 168
 169   This function returns after the IPI has been accepted by the target processor.
 170
 171   @param  IcrLow 32-bit value to be written to the low half of ICR.
 172   @param  ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
 173 **/
 174 VOID
 175 SendIpi (
 176   IN UINT32          IcrLow,
 177   IN UINT32          ApicId
 178   )
 179 {
 180   UINT64             MsrValue;
 181   LOCAL_APIC_ICR_LOW IcrLowReg;
 182   UINTN              LocalApciBaseAddress;
 183   UINT32             IcrHigh;
 184   BOOLEAN            InterruptState;
 185
 186   //
 187   // Legacy APIC or X2APIC?
 188   //
 189   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
 190     ASSERT (ApicId <= 0xff);
 191
 192     InterruptState = SaveAndDisableInterrupts ();
 193
 194     //
 195     // Get base address of this LAPIC
 196     //
 197     LocalApciBaseAddress = GetLocalApicBaseAddress();
 198
 199     //
 200     // Save existing contents of ICR high 32 bits
 201     //
 202     IcrHigh = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET);
 203
 204     //
 205     // Wait for DeliveryStatus clear in case a previous IPI
 206     //  is still being sent
 207     //
 208     do {
 209       IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
 210     } while (IcrLowReg.Bits.DeliveryStatus != 0);
 211
 212     //
 213     // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
 214     //
 215     MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
 216     MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
 217
 218     //
 219     // Wait for DeliveryStatus clear again
 220     //
 221     do {
 222       IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
 223     } while (IcrLowReg.Bits.DeliveryStatus != 0);
 224
 225     //
 226     // And restore old contents of ICR high
 227     //
 228     MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
 229
 230     SetInterruptState (InterruptState);
 231
 232   } else {
 233     //
 234     // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
 235     // interrupt in x2APIC mode.
 236     //
 237     MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
 238     AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
 239   }
 240 }
 241
 242 //
 243 // Library API implementation functions
 244 //
 245
 246 /**
 247   Get the current local APIC mode.
 248
 249   If local APIC is disabled, then ASSERT.
 250
 251   @retval LOCAL_APIC_MODE_XAPIC  current APIC mode is xAPIC.
 252   @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
 253 **/
 254 UINTN
 255 EFIAPI
 256 GetApicMode (
 257   VOID
 258   )
 259 {
 260   MSR_IA32_APIC_BASE ApicBaseMsr;
 261
 262   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 263   //
 264   // Local APIC should have been enabled
 265   //
 266   ASSERT (ApicBaseMsr.Bits.En != 0);
 267   if (ApicBaseMsr.Bits.Extd != 0) {
 268     return LOCAL_APIC_MODE_X2APIC;
 269   } else {
 270     return LOCAL_APIC_MODE_XAPIC;
 271   }
 272 }
 273
 274 /**
 275   Set the current local APIC mode.
 276
 277   If the specified local APIC mode is not valid, then ASSERT.
 278   If the specified local APIC mode can't be set as current, then ASSERT.
 279
 280   @param ApicMode APIC mode to be set.
 281
 282   @note  This API must not be called from an interrupt handler or SMI handler.
 283          It may result in unpredictable behavior.
 284 **/
 285 VOID
 286 EFIAPI
 287 SetApicMode (
 288   IN UINTN  ApicMode
 289   )
 290 {
 291   UINTN              CurrentMode;
 292   MSR_IA32_APIC_BASE ApicBaseMsr;
 293
 294   CurrentMode = GetApicMode ();
 295   if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {
 296     switch (ApicMode) {
 297       case LOCAL_APIC_MODE_XAPIC:
 298         break;
 299       case LOCAL_APIC_MODE_X2APIC:
 300         ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 301         ApicBaseMsr.Bits.Extd = 1;
 302         AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
 303         break;
 304       default:
 305         ASSERT (FALSE);
 306     }
 307   } else {
 308     switch (ApicMode) {
 309       case LOCAL_APIC_MODE_XAPIC:
 310         //
 311         //  Transition from x2APIC mode to xAPIC mode is a two-step process:
 312         //    x2APIC -> Local APIC disabled -> xAPIC
 313         //
 314         ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
 315         ApicBaseMsr.Bits.Extd = 0;
 316         ApicBaseMsr.Bits.En = 0;
 317         AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
 318         ApicBaseMsr.Bits.En = 1;
 319         AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
 320         break;
 321       case LOCAL_APIC_MODE_X2APIC:
 322         break;
 323       default:
 324         ASSERT (FALSE);
 325     }
 326   }
 327 }
 328
 329 /**
 330   Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
 331
 332   In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
 333   In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
 334   the 32-bit local APIC ID is returned as initial APIC ID.
 335
 336   @return  32-bit initial local APIC ID of the executing processor.
 337 **/
 338 UINT32
 339 EFIAPI
 340 GetInitialApicId (
 341   VOID
 342   )
 343 {
 344   UINT32 ApicId;
 345   UINT32 MaxCpuIdIndex;
 346   UINT32 RegEbx;
 347
 348   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
 349     //
 350     // Get the max index of basic CPUID
 351     //
 352     AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
 353     //
 354     // If CPUID Leaf B is supported,
 355     // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
 356     // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
 357     //
 358     if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
 359       AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);
 360       return ApicId;
 361     }
 362     AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
 363     return RegEbx >> 24;
 364   } else {
 365     return GetApicId ();
 366   }
 367 }
 368
 369 /**
 370   Get the local APIC ID of the executing processor.
 371
 372   @return  32-bit local APIC ID of the executing processor.
 373 **/
 374 UINT32
 375 EFIAPI
 376 GetApicId (
 377   VOID
 378   )
 379 {
 380   UINT32 ApicId;
 381   UINT32 InitApicId;
 382
 383   ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
 384   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
 385     ApicId = ((InitApicId = GetInitialApicId ()) < 0x100) ? (ApicId >> 24) : InitApicId;
 386   }
 387
 388   return ApicId;
 389 }
 390
 391 /**
 392   Get the value of the local APIC version register.
 393
 394   @return  the value of the local APIC version register.
 395 **/
 396 UINT32
 397 EFIAPI
 398 GetApicVersion (
 399   VOID
 400   )
 401 {
 402   return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
 403 }
 404
 405 /**
 406   Send a Fixed IPI to a specified target processor.
 407
 408   This function returns after the IPI has been accepted by the target processor.
 409
 410   @param  ApicId   The local APIC ID of the target processor.
 411   @param  Vector   The vector number of the interrupt being sent.
 412 **/
 413 VOID
 414 EFIAPI
 415 SendFixedIpi (
 416   IN UINT32          ApicId,
 417   IN UINT8           Vector
 418   )
 419 {
 420   LOCAL_APIC_ICR_LOW IcrLow;
 421
 422   IcrLow.Uint32 = 0;
 423   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 424   IcrLow.Bits.Level = 1;
 425   IcrLow.Bits.Vector = Vector;
 426   SendIpi (IcrLow.Uint32, ApicId);
 427 }
 428
 429 /**
 430   Send a Fixed IPI to all processors excluding self.
 431
 432   This function returns after the IPI has been accepted by the target processors.
 433
 434   @param  Vector   The vector number of the interrupt being sent.
 435 **/
 436 VOID
 437 EFIAPI
 438 SendFixedIpiAllExcludingSelf (
 439   IN UINT8           Vector
 440   )
 441 {
 442   LOCAL_APIC_ICR_LOW IcrLow;
 443
 444   IcrLow.Uint32 = 0;
 445   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
 446   IcrLow.Bits.Level = 1;
 447   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 448   IcrLow.Bits.Vector = Vector;
 449   SendIpi (IcrLow.Uint32, 0);
 450 }
 451
 452 /**
 453   Send a SMI IPI to a specified target processor.
 454
 455   This function returns after the IPI has been accepted by the target processor.
 456
 457   @param  ApicId   Specify the local APIC ID of the target processor.
 458 **/
 459 VOID
 460 EFIAPI
 461 SendSmiIpi (
 462   IN UINT32          ApicId
 463   )
 464 {
 465   LOCAL_APIC_ICR_LOW IcrLow;
 466
 467   IcrLow.Uint32 = 0;
 468   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 469   IcrLow.Bits.Level = 1;
 470   SendIpi (IcrLow.Uint32, ApicId);
 471 }
 472
 473 /**
 474   Send a SMI IPI to all processors excluding self.
 475
 476   This function returns after the IPI has been accepted by the target processors.
 477 **/
 478 VOID
 479 EFIAPI
 480 SendSmiIpiAllExcludingSelf (
 481   VOID
 482   )
 483 {
 484   LOCAL_APIC_ICR_LOW IcrLow;
 485
 486   IcrLow.Uint32 = 0;
 487   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
 488   IcrLow.Bits.Level = 1;
 489   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 490   SendIpi (IcrLow.Uint32, 0);
 491 }
 492
 493 /**
 494   Send an INIT IPI to a specified target processor.
 495
 496   This function returns after the IPI has been accepted by the target processor.
 497
 498   @param  ApicId   Specify the local APIC ID of the target processor.
 499 **/
 500 VOID
 501 EFIAPI
 502 SendInitIpi (
 503   IN UINT32          ApicId
 504   )
 505 {
 506   LOCAL_APIC_ICR_LOW IcrLow;
 507
 508   IcrLow.Uint32 = 0;
 509   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 510   IcrLow.Bits.Level = 1;
 511   SendIpi (IcrLow.Uint32, ApicId);
 512 }
 513
 514 /**
 515   Send an INIT IPI to all processors excluding self.
 516
 517   This function returns after the IPI has been accepted by the target processors.
 518 **/
 519 VOID
 520 EFIAPI
 521 SendInitIpiAllExcludingSelf (
 522   VOID
 523   )
 524 {
 525   LOCAL_APIC_ICR_LOW IcrLow;
 526
 527   IcrLow.Uint32 = 0;
 528   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
 529   IcrLow.Bits.Level = 1;
 530   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 531   SendIpi (IcrLow.Uint32, 0);
 532 }
 533
 534 /**
 535   Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
 536
 537   This function returns after the IPI has been accepted by the target processor.
 538
 539   if StartupRoutine >= 1M, then ASSERT.
 540   if StartupRoutine is not multiple of 4K, then ASSERT.
 541
 542   @param  ApicId          Specify the local APIC ID of the target processor.
 543   @param  StartupRoutine  Points to a start-up routine which is below 1M physical
 544                           address and 4K aligned.
 545 **/
 546 VOID
 547 EFIAPI
 548 SendInitSipiSipi (
 549   IN UINT32          ApicId,
 550   IN UINT32          StartupRoutine
 551   )
 552 {
 553   LOCAL_APIC_ICR_LOW IcrLow;
 554
 555   ASSERT (StartupRoutine < 0x100000);
 556   ASSERT ((StartupRoutine & 0xfff) == 0);
 557
 558   SendInitIpi (ApicId);
 559   MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
 560   IcrLow.Uint32 = 0;
 561   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 562   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 563   IcrLow.Bits.Level = 1;
 564   SendIpi (IcrLow.Uint32, ApicId);
 565   MicroSecondDelay (200);
 566   SendIpi (IcrLow.Uint32, ApicId);
 567 }
 568
 569 /**
 570   Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
 571
 572   This function returns after the IPI has been accepted by the target processors.
 573
 574   if StartupRoutine >= 1M, then ASSERT.
 575   if StartupRoutine is not multiple of 4K, then ASSERT.
 576
 577   @param  StartupRoutine    Points to a start-up routine which is below 1M physical
 578                             address and 4K aligned.
 579 **/
 580 VOID
 581 EFIAPI
 582 SendInitSipiSipiAllExcludingSelf (
 583   IN UINT32          StartupRoutine
 584   )
 585 {
 586   LOCAL_APIC_ICR_LOW IcrLow;
 587
 588   ASSERT (StartupRoutine < 0x100000);
 589   ASSERT ((StartupRoutine & 0xfff) == 0);
 590
 591   SendInitIpiAllExcludingSelf ();
 592   MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
 593   IcrLow.Uint32 = 0;
 594   IcrLow.Bits.Vector = (StartupRoutine >> 12);
 595   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
 596   IcrLow.Bits.Level = 1;
 597   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
 598   SendIpi (IcrLow.Uint32, 0);
 599   MicroSecondDelay (200);
 600   SendIpi (IcrLow.Uint32, 0);
 601 }
 602
 603 /**
 604   Programming Virtual Wire Mode.
 605
 606   This function programs the local APIC for virtual wire mode following
 607   the example described in chapter A.3 of the MP 1.4 spec.
 608
 609   IOxAPIC is not involved in this type of virtual wire mode.
 610 **/
 611 VOID
 612 EFIAPI
 613 ProgramVirtualWireMode (
 614   VOID
 615   )
 616 {
 617   LOCAL_APIC_SVR      Svr;
 618   LOCAL_APIC_LVT_LINT Lint;
 619
 620   //
 621   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
 622   //
 623   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 624   Svr.Bits.SpuriousVector = 0xf;
 625   Svr.Bits.SoftwareEnable = 1;
 626   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 627
 628   //
 629   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
 630   //
 631   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 632   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
 633   Lint.Bits.InputPinPolarity = 0;
 634   Lint.Bits.TriggerMode = 0;
 635   Lint.Bits.Mask = 0;
 636   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
 637
 638   //
 639   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
 640   //
 641   Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 642   Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
 643   Lint.Bits.InputPinPolarity = 0;
 644   Lint.Bits.TriggerMode = 0;
 645   Lint.Bits.Mask = 0;
 646   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
 647 }
 648
 649 /**
 650   Disable LINT0 & LINT1 interrupts.
 651
 652   This function sets the mask flag in the LVT LINT0 & LINT1 registers.
 653 **/
 654 VOID
 655 EFIAPI
 656 DisableLvtInterrupts (
 657   VOID
 658   )
 659 {
 660   LOCAL_APIC_LVT_LINT LvtLint;
 661
 662   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
 663   LvtLint.Bits.Mask = 1;
 664   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
 665
 666   LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
 667   LvtLint.Bits.Mask = 1;
 668   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
 669 }
 670
 671 /**
 672   Read the initial count value from the init-count register.
 673
 674   @return The initial count value read from the init-count register.
 675 **/
 676 UINT32
 677 EFIAPI
 678 GetApicTimerInitCount (
 679   VOID
 680   )
 681 {
 682   return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);
 683 }
 684
 685 /**
 686   Read the current count value from the current-count register.
 687
 688   @return The current count value read from the current-count register.
 689 **/
 690 UINT32
 691 EFIAPI
 692 GetApicTimerCurrentCount (
 693   VOID
 694   )
 695 {
 696   return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);
 697 }
 698
 699 /**
 700   Initialize the local APIC timer.
 701
 702   The local APIC timer is initialized and enabled.
 703
 704   @param DivideValue   The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 705                        If it is 0, then use the current divide value in the DCR.
 706   @param InitCount     The initial count value.
 707   @param PeriodicMode  If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 708   @param Vector        The timer interrupt vector number.
 709 **/
 710 VOID
 711 EFIAPI
 712 InitializeApicTimer (
 713   IN UINTN   DivideValue,
 714   IN UINT32  InitCount,
 715   IN BOOLEAN PeriodicMode,
 716   IN UINT8   Vector
 717   )
 718 {
 719   LOCAL_APIC_SVR       Svr;
 720   LOCAL_APIC_DCR       Dcr;
 721   LOCAL_APIC_LVT_TIMER LvtTimer;
 722   UINT32               Divisor;
 723
 724   //
 725   // Ensure local APIC is in software-enabled state.
 726   //
 727   Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
 728   Svr.Bits.SoftwareEnable = 1;
 729   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
 730
 731   //
 732   // Program init-count register.
 733   //
 734   WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);
 735
 736   if (DivideValue != 0) {
 737     ASSERT (DivideValue <= 128);
 738     ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
 739     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
 740
 741     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 742     Dcr.Bits.DivideValue1 = (Divisor & 0x3);
 743     Dcr.Bits.DivideValue2 = (Divisor >> 2);
 744     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
 745   }
 746
 747   //
 748   // Enable APIC timer interrupt with specified timer mode.
 749   //
 750   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 751   if (PeriodicMode) {
 752     LvtTimer.Bits.TimerMode = 1;
 753   } else {
 754     LvtTimer.Bits.TimerMode = 0;
 755   }
 756   LvtTimer.Bits.Mask = 0;
 757   LvtTimer.Bits.Vector = Vector;
 758   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 759 }
 760
 761 /**
 762   Get the state of the local APIC timer.
 763
 764   @param DivideValue   Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
 765   @param PeriodicMode  Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
 766   @param Vector        Return the timer interrupt vector number.
 767 **/
 768 VOID
 769 EFIAPI
 770 GetApicTimerState (
 771   OUT UINTN    *DivideValue  OPTIONAL,
 772   OUT BOOLEAN  *PeriodicMode  OPTIONAL,
 773   OUT UINT8    *Vector  OPTIONAL
 774   )
 775 {
 776   UINT32 Divisor;
 777   LOCAL_APIC_DCR Dcr;
 778   LOCAL_APIC_LVT_TIMER LvtTimer;
 779
 780   if (DivideValue != NULL) {
 781     Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
 782     Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
 783     Divisor = (Divisor + 1) & 0x7;
 784     *DivideValue = ((UINTN)1) << Divisor;
 785   }
 786
 787   if (PeriodicMode != NULL || Vector != NULL) {
 788     LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 789     if (PeriodicMode != NULL) {
 790       if (LvtTimer.Bits.TimerMode == 1) {
 791         *PeriodicMode = TRUE;
 792       } else {
 793         *PeriodicMode = FALSE;
 794       }
 795     }
 796     if (Vector != NULL) {
 797       *Vector = (UINT8) LvtTimer.Bits.Vector;
 798     }
 799   }
 800 }
 801
 802 /**
 803   Enable the local APIC timer interrupt.
 804 **/
 805 VOID
 806 EFIAPI
 807 EnableApicTimerInterrupt (
 808   VOID
 809   )
 810 {
 811   LOCAL_APIC_LVT_TIMER LvtTimer;
 812
 813   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 814   LvtTimer.Bits.Mask = 0;
 815   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 816 }
 817
 818 /**
 819   Disable the local APIC timer interrupt.
 820 **/
 821 VOID
 822 EFIAPI
 823 DisableApicTimerInterrupt (
 824   VOID
 825   )
 826 {
 827   LOCAL_APIC_LVT_TIMER LvtTimer;
 828
 829   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 830   LvtTimer.Bits.Mask = 1;
 831   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
 832 }
 833
 834 /**
 835   Get the local APIC timer interrupt state.
 836
 837   @retval TRUE  The local APIC timer interrupt is enabled.
 838   @retval FALSE The local APIC timer interrupt is disabled.
 839 **/
 840 BOOLEAN
 841 EFIAPI
 842 GetApicTimerInterruptState (
 843   VOID
 844   )
 845 {
 846   LOCAL_APIC_LVT_TIMER LvtTimer;
 847
 848   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
 849   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
 850 }
 851
 852 /**
 853   Send EOI to the local APIC.
 854 **/
 855 VOID
 856 EFIAPI
 857 SendApicEoi (
 858   VOID
 859   )
 860 {
 861   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
 862 }
 863
 864 /**
 865   Get the 32-bit address that a device should use to send a Message Signaled
 866   Interrupt (MSI) to the Local APIC of the currently executing processor.
 867
 868   @return 32-bit address used to send an MSI to the Local APIC.
 869 **/
 870 UINT32
 871 EFIAPI
 872 GetApicMsiAddress (
 873   VOID
 874   )
 875 {
 876   LOCAL_APIC_MSI_ADDRESS  MsiAddress;
 877
 878   //
 879   // Return address for an MSI interrupt to be delivered only to the APIC ID
 880   // of the currently executing processor.
 881   //
 882   MsiAddress.Uint32             = 0;
 883   MsiAddress.Bits.BaseAddress   = 0xFEE;
 884   MsiAddress.Bits.DestinationId = GetApicId ();
 885   return MsiAddress.Uint32;
 886 }
 887
 888 /**
 889   Get the 64-bit data value that a device should use to send a Message Signaled
 890   Interrupt (MSI) to the Local APIC of the currently executing processor.
 891
 892   If Vector is not in range 0x10..0xFE, then ASSERT().
 893   If DeliveryMode is not supported, then ASSERT().
 894
 895   @param  Vector          The 8-bit interrupt vector associated with the MSI.
 896                           Must be in the range 0x10..0xFE
 897   @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI
 898                           is handled.  The only supported values are:
 899                             0: LOCAL_APIC_DELIVERY_MODE_FIXED
 900                             1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
 901                             2: LOCAL_APIC_DELIVERY_MODE_SMI
 902                             4: LOCAL_APIC_DELIVERY_MODE_NMI
 903                             5: LOCAL_APIC_DELIVERY_MODE_INIT
 904                             7: LOCAL_APIC_DELIVERY_MODE_EXTINT
 905
 906   @param  LevelTriggered  TRUE specifies a level triggered interrupt.
 907                           FALSE specifies an edge triggered interrupt.
 908   @param  AssertionLevel  Ignored if LevelTriggered is FALSE.
 909                           TRUE specifies a level triggered interrupt that active
 910                           when the interrupt line is asserted.
 911                           FALSE specifies a level triggered interrupt that active
 912                           when the interrupt line is deasserted.
 913
 914   @return 64-bit data value used to send an MSI to the Local APIC.
 915 **/
 916 UINT64
 917 EFIAPI
 918 GetApicMsiValue (
 919   IN UINT8    Vector,
 920   IN UINTN    DeliveryMode,
 921   IN BOOLEAN  LevelTriggered,
 922   IN BOOLEAN  AssertionLevel
 923   )
 924 {
 925   LOCAL_APIC_MSI_DATA  MsiData;
 926
 927   ASSERT (Vector >= 0x10 && Vector <= 0xFE);
 928   ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
 929
 930   MsiData.Uint64            = 0;
 931   MsiData.Bits.Vector       = Vector;
 932   MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
 933   if (LevelTriggered) {
 934     MsiData.Bits.TriggerMode = 1;
 935     if (AssertionLevel) {
 936       MsiData.Bits.Level = 1;
 937     }
 938   }
 939   return MsiData.Uint64;
 940 }