2 Intel Processor Trace feature.
4 Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
9 #include "CpuCommonFeatures.h"
12 /// This macro define the max entries in the Topa table.
13 /// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
14 /// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
15 /// current table (for circular array) or to the base of another table.
16 /// At least 2 entries are needed because the list of entries must
17 /// be terminated by an entry with the END bit set to 1, so 2
18 /// entries are required to use a single valid entry.
20 #define MAX_TOPA_ENTRY_COUNT 2
24 /// Processor trace output scheme selection.
27 RtitOutputSchemeSingleRange
= 0,
32 BOOLEAN ProcTraceSupported
;
33 BOOLEAN TopaSupported
;
34 BOOLEAN SingleRangeSupported
;
35 } PROC_TRACE_PROCESSOR_DATA
;
38 UINT32 NumberOfProcessors
;
40 UINT8 ProcTraceOutputScheme
;
41 UINT32 ProcTraceMemSize
;
43 UINTN
*ThreadMemRegionTable
;
44 UINTN AllocatedThreads
;
47 UINTN TopaMemArrayCount
;
49 PROC_TRACE_PROCESSOR_DATA
*ProcessorData
;
53 RTIT_TOPA_TABLE_ENTRY TopaEntry
[MAX_TOPA_ENTRY_COUNT
];
54 } PROC_TRACE_TOPA_TABLE
;
57 Prepares for the data used by CPU feature detection and initialization.
59 @param[in] NumberOfProcessors The number of CPUs in the platform.
61 @return Pointer to a buffer of CPU related configuration data.
63 @note This service could be called by BSP only.
67 ProcTraceGetConfigData (
68 IN UINTN NumberOfProcessors
71 PROC_TRACE_DATA
*ConfigData
;
73 ConfigData
= AllocateZeroPool (sizeof (PROC_TRACE_DATA
) + sizeof (PROC_TRACE_PROCESSOR_DATA
) * NumberOfProcessors
);
74 ASSERT (ConfigData
!= NULL
);
75 ConfigData
->ProcessorData
= (PROC_TRACE_PROCESSOR_DATA
*) ((UINT8
*) ConfigData
+ sizeof (PROC_TRACE_DATA
));
77 ConfigData
->NumberOfProcessors
= (UINT32
) NumberOfProcessors
;
78 ConfigData
->ProcTraceMemSize
= PcdGet32 (PcdCpuProcTraceMemSize
);
79 ConfigData
->ProcTraceOutputScheme
= PcdGet8 (PcdCpuProcTraceOutputScheme
);
85 Detects if Intel Processor Trace feature supported on current
88 @param[in] ProcessorNumber The index of the CPU executing this function.
89 @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
90 structure for the CPU executing this function.
91 @param[in] ConfigData A pointer to the configuration buffer returned
92 by CPU_FEATURE_GET_CONFIG_DATA. NULL if
93 CPU_FEATURE_GET_CONFIG_DATA was not provided in
96 @retval TRUE Processor Trace feature is supported.
97 @retval FALSE Processor Trace feature is not supported.
99 @note This service could be called by BSP/APs.
104 IN UINTN ProcessorNumber
,
105 IN REGISTER_CPU_FEATURE_INFORMATION
*CpuInfo
,
106 IN VOID
*ConfigData OPTIONAL
109 PROC_TRACE_DATA
*ProcTraceData
;
110 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx
;
111 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx
;
114 // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
116 ProcTraceData
= (PROC_TRACE_DATA
*) ConfigData
;
117 ASSERT (ProcTraceData
!= NULL
);
118 if ((ProcTraceData
->ProcTraceMemSize
> RtitTopaMemorySize128M
) ||
119 (ProcTraceData
->ProcTraceOutputScheme
> RtitOutputSchemeToPA
)) {
124 // Check if Processor Trace is supported
126 AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS
, 0, NULL
, &Ebx
.Uint32
, NULL
, NULL
);
127 ProcTraceData
->ProcessorData
[ProcessorNumber
].ProcTraceSupported
= (BOOLEAN
) (Ebx
.Bits
.IntelProcessorTrace
== 1);
128 if (!ProcTraceData
->ProcessorData
[ProcessorNumber
].ProcTraceSupported
) {
132 AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE
, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF
, NULL
, NULL
, &Ecx
.Uint32
, NULL
);
133 ProcTraceData
->ProcessorData
[ProcessorNumber
].TopaSupported
= (BOOLEAN
) (Ecx
.Bits
.RTIT
== 1);
134 ProcTraceData
->ProcessorData
[ProcessorNumber
].SingleRangeSupported
= (BOOLEAN
) (Ecx
.Bits
.SingleRangeOutput
== 1);
135 if ((ProcTraceData
->ProcessorData
[ProcessorNumber
].TopaSupported
&& (ProcTraceData
->ProcTraceOutputScheme
== RtitOutputSchemeToPA
)) ||
136 (ProcTraceData
->ProcessorData
[ProcessorNumber
].SingleRangeSupported
&& (ProcTraceData
->ProcTraceOutputScheme
== RtitOutputSchemeSingleRange
))) {
144 Initializes Intel Processor Trace feature to specific state.
146 @param[in] ProcessorNumber The index of the CPU executing this function.
147 @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
148 structure for the CPU executing this function.
149 @param[in] ConfigData A pointer to the configuration buffer returned
150 by CPU_FEATURE_GET_CONFIG_DATA. NULL if
151 CPU_FEATURE_GET_CONFIG_DATA was not provided in
152 RegisterCpuFeature().
153 @param[in] State If TRUE, then the Processor Trace feature must be
155 If FALSE, then the Processor Trace feature must be
158 @retval RETURN_SUCCESS Intel Processor Trace feature is initialized.
163 ProcTraceInitialize (
164 IN UINTN ProcessorNumber
,
165 IN REGISTER_CPU_FEATURE_INFORMATION
*CpuInfo
,
166 IN VOID
*ConfigData
, OPTIONAL
170 UINT32 MemRegionSize
;
173 UINTN MemRegionBaseAddr
;
174 UINTN
*ThreadMemRegionTable
;
176 UINTN TopaTableBaseAddr
;
177 UINTN AlignedAddress
;
179 PROC_TRACE_TOPA_TABLE
*TopaTable
;
180 PROC_TRACE_DATA
*ProcTraceData
;
182 MSR_IA32_RTIT_CTL_REGISTER CtrlReg
;
183 MSR_IA32_RTIT_STATUS_REGISTER StatusReg
;
184 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg
;
185 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg
;
186 RTIT_TOPA_TABLE_ENTRY
*TopaEntryPtr
;
189 // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
190 // MSR_IA32_RTIT_* for thread 0 in each core.
192 if (IS_GOLDMONT_PROCESSOR (CpuInfo
->DisplayFamily
, CpuInfo
->DisplayModel
) ||
193 IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo
->DisplayFamily
, CpuInfo
->DisplayModel
)) {
194 if (CpuInfo
->ProcessorInfo
.Location
.Thread
!= 0) {
195 return RETURN_SUCCESS
;
199 ProcTraceData
= (PROC_TRACE_DATA
*) ConfigData
;
200 ASSERT (ProcTraceData
!= NULL
);
203 // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b
205 CtrlReg
.Uint64
= AsmReadMsr64 (MSR_IA32_RTIT_CTL
);
206 if (CtrlReg
.Bits
.TraceEn
!= 0) {
208 /// Clear bit 0 in MSR IA32_RTIT_CTL (570)
210 CtrlReg
.Bits
.TraceEn
= 0;
211 CPU_REGISTER_TABLE_WRITE64 (
219 /// Clear MSR IA32_RTIT_STS (571h) to all zeros
221 StatusReg
.Uint64
= 0x0;
222 CPU_REGISTER_TABLE_WRITE64 (
225 MSR_IA32_RTIT_STATUS
,
231 return RETURN_SUCCESS
;
234 MemRegionBaseAddr
= 0;
237 if (ProcTraceData
->ThreadMemRegionTable
== NULL
) {
239 DEBUG ((DEBUG_INFO
, "Initialize Processor Trace\n"));
243 /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
245 MemRegionSize
= (UINT32
) (1 << (ProcTraceData
->ProcTraceMemSize
+ 12));
247 DEBUG ((DEBUG_INFO
, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize
));
252 // Let BSP allocate and create the necessary memory region (Aligned to the size of
253 // the memory region from setup option(ProcTraceMemSize) which is an integral multiple of 4kB)
254 // for the all the enabled threads for storing Processor Trace debug data. Then Configure the trace
255 // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
256 // aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 clear.
258 ThreadMemRegionTable
= (UINTN
*) AllocatePool (ProcTraceData
->NumberOfProcessors
* sizeof (UINTN
*));
259 if (ThreadMemRegionTable
== NULL
) {
260 DEBUG ((DEBUG_ERROR
, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
261 return RETURN_OUT_OF_RESOURCES
;
263 ProcTraceData
->ThreadMemRegionTable
= ThreadMemRegionTable
;
265 for (Index
= 0; Index
< ProcTraceData
->NumberOfProcessors
; Index
++, ProcTraceData
->AllocatedThreads
++) {
266 Pages
= EFI_SIZE_TO_PAGES (MemRegionSize
);
267 Alignment
= MemRegionSize
;
268 AlignedAddress
= (UINTN
) AllocateAlignedReservedPages (Pages
, Alignment
);
269 if (AlignedAddress
== 0) {
270 DEBUG ((DEBUG_ERROR
, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData
->AllocatedThreads
));
273 // Could not allocate for BSP even
275 FreePool ((VOID
*) ThreadMemRegionTable
);
276 ThreadMemRegionTable
= NULL
;
277 return RETURN_OUT_OF_RESOURCES
;
282 ThreadMemRegionTable
[Index
] = AlignedAddress
;
283 DEBUG ((DEBUG_INFO
, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index
, (UINT64
) ThreadMemRegionTable
[Index
]));
286 DEBUG ((DEBUG_INFO
, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData
->AllocatedThreads
));
287 MemRegionBaseAddr
= ThreadMemRegionTable
[0];
289 if (ProcessorNumber
< ProcTraceData
->AllocatedThreads
) {
290 MemRegionBaseAddr
= ProcTraceData
->ThreadMemRegionTable
[ProcessorNumber
];
292 return RETURN_SUCCESS
;
297 /// Check Processor Trace output scheme: Single Range output or ToPA table
301 // Single Range output scheme
303 if (ProcTraceData
->ProcessorData
[ProcessorNumber
].SingleRangeSupported
&&
304 (ProcTraceData
->ProcTraceOutputScheme
== RtitOutputSchemeSingleRange
)) {
306 DEBUG ((DEBUG_INFO
, "ProcTrace: Enabling Single Range Output scheme \n"));
310 // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
312 CtrlReg
.Uint64
= AsmReadMsr64 (MSR_IA32_RTIT_CTL
);
313 CtrlReg
.Bits
.ToPA
= 0;
314 CPU_REGISTER_TABLE_WRITE64 (
322 // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
324 OutputBaseReg
.Bits
.Base
= (MemRegionBaseAddr
>> 7) & 0x01FFFFFF;
325 OutputBaseReg
.Bits
.BaseHi
= RShiftU64 ((UINT64
) MemRegionBaseAddr
, 32) & 0xFFFFFFFF;
326 CPU_REGISTER_TABLE_WRITE64 (
329 MSR_IA32_RTIT_OUTPUT_BASE
,
334 // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
336 OutputMaskPtrsReg
.Bits
.MaskOrTableOffset
= ((MemRegionSize
- 1) >> 7) & 0x01FFFFFF;
337 OutputMaskPtrsReg
.Bits
.OutputOffset
= RShiftU64 (MemRegionSize
- 1, 32) & 0xFFFFFFFF;
338 CPU_REGISTER_TABLE_WRITE64 (
341 MSR_IA32_RTIT_OUTPUT_MASK_PTRS
,
342 OutputMaskPtrsReg
.Uint64
347 // ToPA(Table of physical address) scheme
349 if (ProcTraceData
->ProcessorData
[ProcessorNumber
].TopaSupported
&&
350 (ProcTraceData
->ProcTraceOutputScheme
== RtitOutputSchemeToPA
)) {
352 // Create ToPA structure aligned at 4KB for each logical thread
353 // with at least 2 entries by 8 bytes size each. The first entry
354 // should have the trace output base address in bits 47:12, 6:9
355 // for Size, bits 4,2 and 0 must be cleared. The second entry
356 // should have the base address of the table location in bits
357 // 47:12, bits 4 and 2 must be cleared and bit 0 must be set.
360 DEBUG ((DEBUG_INFO
, "ProcTrace: Enabling ToPA scheme \n"));
362 // Let BSP allocate ToPA table mem for all threads
364 TopaMemArray
= (UINTN
*) AllocatePool (ProcTraceData
->AllocatedThreads
* sizeof (UINTN
*));
365 if (TopaMemArray
== NULL
) {
366 DEBUG ((DEBUG_ERROR
, "ProcTrace: Allocate mem for ToPA Failed\n"));
367 return RETURN_OUT_OF_RESOURCES
;
369 ProcTraceData
->TopaMemArray
= TopaMemArray
;
371 for (Index
= 0; Index
< ProcTraceData
->AllocatedThreads
; Index
++) {
372 Pages
= EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE
));
374 AlignedAddress
= (UINTN
) AllocateAlignedReservedPages (Pages
, Alignment
);
375 if (AlignedAddress
== 0) {
376 if (Index
< ProcTraceData
->AllocatedThreads
) {
377 ProcTraceData
->AllocatedThreads
= Index
;
379 DEBUG ((DEBUG_ERROR
, "ProcTrace: Out of mem, allocating ToPA mem only for %d threads\n", ProcTraceData
->AllocatedThreads
));
382 // Could not allocate for BSP
384 FreePool ((VOID
*) TopaMemArray
);
386 return RETURN_OUT_OF_RESOURCES
;
391 TopaMemArray
[Index
] = AlignedAddress
;
392 DEBUG ((DEBUG_INFO
, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index
, (UINT64
) TopaMemArray
[Index
]));
395 DEBUG ((DEBUG_INFO
, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData
->AllocatedThreads
));
397 // BSP gets the first block
399 TopaTableBaseAddr
= TopaMemArray
[0];
402 // Count for currently executing AP.
404 if (ProcessorNumber
< ProcTraceData
->AllocatedThreads
) {
405 TopaTableBaseAddr
= ProcTraceData
->TopaMemArray
[ProcessorNumber
];
407 return RETURN_SUCCESS
;
411 TopaTable
= (PROC_TRACE_TOPA_TABLE
*) TopaTableBaseAddr
;
412 TopaEntryPtr
= &TopaTable
->TopaEntry
[0];
413 TopaEntryPtr
->Bits
.Base
= (MemRegionBaseAddr
>> 12) & 0x000FFFFF;
414 TopaEntryPtr
->Bits
.BaseHi
= RShiftU64 ((UINT64
) MemRegionBaseAddr
, 32) & 0xFFFFFFFF;
415 TopaEntryPtr
->Bits
.Size
= ProcTraceData
->ProcTraceMemSize
;
416 TopaEntryPtr
->Bits
.END
= 0;
418 TopaEntryPtr
= &TopaTable
->TopaEntry
[1];
419 TopaEntryPtr
->Bits
.Base
= (TopaTableBaseAddr
>> 12) & 0x000FFFFF;
420 TopaEntryPtr
->Bits
.BaseHi
= RShiftU64 ((UINT64
) TopaTableBaseAddr
, 32) & 0xFFFFFFFF;
421 TopaEntryPtr
->Bits
.END
= 1;
424 // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
426 OutputBaseReg
.Bits
.Base
= (TopaTableBaseAddr
>> 7) & 0x01FFFFFF;
427 OutputBaseReg
.Bits
.BaseHi
= RShiftU64 ((UINT64
) TopaTableBaseAddr
, 32) & 0xFFFFFFFF;
428 CPU_REGISTER_TABLE_WRITE64 (
431 MSR_IA32_RTIT_OUTPUT_BASE
,
436 // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
438 OutputMaskPtrsReg
.Bits
.MaskOrTableOffset
= 0;
439 OutputMaskPtrsReg
.Bits
.OutputOffset
= 0;
440 CPU_REGISTER_TABLE_WRITE64 (
443 MSR_IA32_RTIT_OUTPUT_MASK_PTRS
,
444 OutputMaskPtrsReg
.Uint64
447 // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
449 CtrlReg
.Uint64
= AsmReadMsr64 (MSR_IA32_RTIT_CTL
);
450 CtrlReg
.Bits
.ToPA
= 1;
451 CPU_REGISTER_TABLE_WRITE64 (
460 /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
462 CtrlReg
.Uint64
= AsmReadMsr64 (MSR_IA32_RTIT_CTL
);
464 CtrlReg
.Bits
.User
= 1;
465 CtrlReg
.Bits
.BranchEn
= 1;
466 CtrlReg
.Bits
.TraceEn
= 1;
467 CPU_REGISTER_TABLE_WRITE64 (
474 return RETURN_SUCCESS
;