UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c

   1 /** @file
   2   Intel Processor Trace feature.
   3
   4   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "CpuCommonFeatures.h"
  16
  17 ///
  18 /// This macro define the max entries in the Topa table.
  19 /// Each entry in the table contains some attribute bits, a pointer to an output region, and the size of the region.
  20 /// The last entry in the table may hold a pointer to the next table. This pointer can either point to the top of the
  21 /// current table (for circular array) or to the base of another table.
  22 /// At least 2 entries are needed because the list of entries must
  23 /// be terminated by an entry with the END bit set to 1, so 2
  24 /// entries are required to use a single valid entry.
  25 ///
  26 #define MAX_TOPA_ENTRY_COUNT         2
  27
  28
  29 ///
  30 /// Processor trace output scheme selection.
  31 ///
  32 typedef enum {
  33   RtitOutputSchemeSingleRange = 0,
  34   RtitOutputSchemeToPA
  35 } RTIT_OUTPUT_SCHEME;
  36
  37 typedef struct  {
  38   BOOLEAN  ProcTraceSupported;
  39   BOOLEAN  TopaSupported;
  40   BOOLEAN  SingleRangeSupported;
  41 } PROC_TRACE_PROCESSOR_DATA;
  42
  43 typedef struct  {
  44   UINT32                      NumberOfProcessors;
  45
  46   UINT8                       ProcTraceOutputScheme;
  47   UINT32                      ProcTraceMemSize;
  48
  49   UINTN                       *ThreadMemRegionTable;
  50   UINTN                       AllocatedThreads;
  51
  52   UINTN                       *TopaMemArray;
  53   UINTN                       TopaMemArrayCount;
  54
  55   PROC_TRACE_PROCESSOR_DATA   *ProcessorData;
  56 } PROC_TRACE_DATA;
  57
  58 typedef struct {
  59   RTIT_TOPA_TABLE_ENTRY    TopaEntry[MAX_TOPA_ENTRY_COUNT];
  60 } PROC_TRACE_TOPA_TABLE;
  61
  62 /**
  63   Prepares for the data used by CPU feature detection and initialization.
  64
  65   @param[in]  NumberOfProcessors  The number of CPUs in the platform.
  66
  67   @return  Pointer to a buffer of CPU related configuration data.
  68
  69   @note This service could be called by BSP only.
  70 **/
  71 VOID *
  72 EFIAPI
  73 ProcTraceGetConfigData (
  74   IN UINTN  NumberOfProcessors
  75   )
  76 {
  77   PROC_TRACE_DATA  *ConfigData;
  78
  79   ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
  80   ASSERT (ConfigData != NULL);
  81   ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));
  82
  83   ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;
  84   ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
  85   ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
  86
  87   return ConfigData;
  88 }
  89
  90 /**
  91   Detects if Intel Processor Trace feature supported on current
  92   processor.
  93
  94   @param[in]  ProcessorNumber  The index of the CPU executing this function.
  95   @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION
  96                                structure for the CPU executing this function.
  97   @param[in]  ConfigData       A pointer to the configuration buffer returned
  98                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if
  99                                CPU_FEATURE_GET_CONFIG_DATA was not provided in
 100                                RegisterCpuFeature().
 101
 102   @retval TRUE     Processor Trace feature is supported.
 103   @retval FALSE    Processor Trace feature is not supported.
 104
 105   @note This service could be called by BSP/APs.
 106 **/
 107 BOOLEAN
 108 EFIAPI
 109 ProcTraceSupport (
 110   IN UINTN                             ProcessorNumber,
 111   IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
 112   IN VOID                              *ConfigData  OPTIONAL
 113   )
 114 {
 115   PROC_TRACE_DATA                             *ProcTraceData;
 116   CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
 117   CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX   Ecx;
 118
 119   //
 120   // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
 121   //
 122   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
 123   if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
 124       (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {
 125     return FALSE;
 126   }
 127
 128   //
 129   // Check if Processor Trace is supported
 130   //
 131   AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
 132   ProcTraceData->ProcessorData[ProcessorNumber].ProcTraceSupported = (BOOLEAN) (Ebx.Bits.IntelProcessorTrace == 1);
 133   if (!ProcTraceData->ProcessorData[ProcessorNumber].ProcTraceSupported) {
 134     return FALSE;
 135   }
 136
 137   AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
 138   ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);
 139   ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);
 140   if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
 141       (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {
 142     return TRUE;
 143   }
 144
 145   return FALSE;
 146 }
 147
 148 /**
 149   Initializes Intel Processor Trace feature to specific state.
 150
 151   @param[in]  ProcessorNumber  The index of the CPU executing this function.
 152   @param[in]  CpuInfo          A pointer to the REGISTER_CPU_FEATURE_INFORMATION
 153                                structure for the CPU executing this function.
 154   @param[in]  ConfigData       A pointer to the configuration buffer returned
 155                                by CPU_FEATURE_GET_CONFIG_DATA.  NULL if
 156                                CPU_FEATURE_GET_CONFIG_DATA was not provided in
 157                                RegisterCpuFeature().
 158   @param[in]  State            If TRUE, then the Processor Trace feature must be
 159                                enabled.
 160                                If FALSE, then the Processor Trace feature must be
 161                                disabled.
 162
 163   @retval RETURN_SUCCESS       Intel Processor Trace feature is initialized.
 164
 165 **/
 166 RETURN_STATUS
 167 EFIAPI
 168 ProcTraceInitialize (
 169   IN UINTN                             ProcessorNumber,
 170   IN REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo,
 171   IN VOID                              *ConfigData,  OPTIONAL
 172   IN BOOLEAN                           State
 173   )
 174 {
 175   UINT32                               MemRegionSize;
 176   UINTN                                Pages;
 177   UINTN                                Alignment;
 178   UINTN                                MemRegionBaseAddr;
 179   UINTN                                *ThreadMemRegionTable;
 180   UINTN                                Index;
 181   UINTN                                TopaTableBaseAddr;
 182   UINTN                                AlignedAddress;
 183   UINTN                                *TopaMemArray;
 184   PROC_TRACE_TOPA_TABLE                *TopaTable;
 185   PROC_TRACE_DATA                      *ProcTraceData;
 186   BOOLEAN                              FirstIn;
 187   MSR_IA32_RTIT_CTL_REGISTER           CtrlReg;
 188   MSR_IA32_RTIT_STATUS_REGISTER        StatusReg;
 189   MSR_IA32_RTIT_OUTPUT_BASE_REGISTER   OutputBaseReg;
 190   MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  OutputMaskPtrsReg;
 191   RTIT_TOPA_TABLE_ENTRY                *TopaEntryPtr;
 192
 193   ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
 194
 195   MemRegionBaseAddr = 0;
 196   FirstIn = FALSE;
 197
 198   if (ProcTraceData->ThreadMemRegionTable == NULL) {
 199     FirstIn = TRUE;
 200     DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n"));
 201   }
 202
 203   ///
 204   /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
 205   ///
 206   MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
 207   if (FirstIn) {
 208     DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
 209   }
 210
 211   //
 212   // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CTL[0]==1b
 213   //
 214   CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 215   if (CtrlReg.Bits.TraceEn != 0) {
 216     ///
 217     /// Clear bit 0 in MSR IA32_RTIT_CTL (570)
 218     ///
 219     CtrlReg.Bits.TraceEn = 0;
 220     CPU_REGISTER_TABLE_WRITE64 (
 221       ProcessorNumber,
 222       Msr,
 223       MSR_IA32_RTIT_CTL,
 224       CtrlReg.Uint64
 225       );
 226
 227     ///
 228     /// Clear MSR IA32_RTIT_STS (571h) to all zeros
 229     ///
 230     StatusReg.Uint64 = 0x0;
 231     CPU_REGISTER_TABLE_WRITE64 (
 232       ProcessorNumber,
 233       Msr,
 234       MSR_IA32_RTIT_STATUS,
 235       StatusReg.Uint64
 236       );
 237   }
 238
 239   if (FirstIn) {
 240     //
 241     //   Let BSP allocate and create the necessary memory region (Aligned to the size of
 242     //   the memory region from setup option(ProcTraceMemSize) which is an integral multiple of 4kB)
 243     //   for the all the enabled threads for storing Processor Trace debug data. Then Configure the trace
 244     //   address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
 245     //   aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 clear.
 246     //
 247     ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
 248     if (ThreadMemRegionTable == NULL) {
 249       DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
 250       return RETURN_OUT_OF_RESOURCES;
 251     }
 252     ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
 253
 254     for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
 255       Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
 256       Alignment = MemRegionSize;
 257       AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
 258       if (AlignedAddress == 0) {
 259         DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
 260         if (Index == 0) {
 261           //
 262           // Could not allocate for BSP even
 263           //
 264           FreePool ((VOID *) ThreadMemRegionTable);
 265           ThreadMemRegionTable = NULL;
 266           return RETURN_OUT_OF_RESOURCES;
 267         }
 268         break;
 269       }
 270
 271       ThreadMemRegionTable[Index] = AlignedAddress;
 272       DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));
 273     }
 274
 275     DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
 276     MemRegionBaseAddr = ThreadMemRegionTable[0];
 277   } else {
 278     if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
 279       MemRegionBaseAddr = ProcTraceData->ThreadMemRegionTable[ProcessorNumber];
 280     } else {
 281       return RETURN_SUCCESS;
 282     }
 283   }
 284
 285   ///
 286   /// Check Processor Trace output scheme: Single Range output or ToPA table
 287   ///
 288
 289   //
 290   //  Single Range output scheme
 291   //
 292   if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
 293       (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
 294     if (FirstIn) {
 295       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
 296     }
 297
 298     //
 299     // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
 300     //
 301     CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 302     CtrlReg.Bits.ToPA = 0;
 303     CPU_REGISTER_TABLE_WRITE64 (
 304       ProcessorNumber,
 305       Msr,
 306       MSR_IA32_RTIT_CTL,
 307       CtrlReg.Uint64
 308       );
 309
 310     //
 311     // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
 312     //
 313     OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
 314     OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
 315     CPU_REGISTER_TABLE_WRITE64 (
 316       ProcessorNumber,
 317       Msr,
 318       MSR_IA32_RTIT_OUTPUT_BASE,
 319       OutputBaseReg.Uint64
 320       );
 321
 322     //
 323     // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
 324     //
 325     OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;
 326     OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 ((UINT64) (MemRegionSize - 1), 32) & 0xFFFFFFFF;
 327     CPU_REGISTER_TABLE_WRITE64 (
 328       ProcessorNumber,
 329       Msr,
 330       MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
 331       OutputMaskPtrsReg.Uint64
 332       );
 333   }
 334
 335   //
 336   //  ToPA(Table of physical address) scheme
 337   //
 338   if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
 339       (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
 340     //
 341     //  Create ToPA structure aligned at 4KB for each logical thread
 342     //  with at least 2 entries by 8 bytes size each. The first entry
 343     //  should have the trace output base address in bits 47:12, 6:9
 344     //  for Size, bits 4,2 and 0 must be cleared. The second entry
 345     //  should have the base address of the table location in bits
 346     //  47:12, bits 4 and 2 must be cleared and bit 0 must be set.
 347     //
 348     if (FirstIn) {
 349       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n"));
 350       //
 351       // Let BSP allocate ToPA table mem for all threads
 352       //
 353       TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
 354       if (TopaMemArray == NULL) {
 355         DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
 356         return RETURN_OUT_OF_RESOURCES;
 357       }
 358       ProcTraceData->TopaMemArray = TopaMemArray;
 359
 360       for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
 361         Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
 362         Alignment = 0x1000;
 363         AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
 364         if (AlignedAddress == 0) {
 365           if (Index < ProcTraceData->AllocatedThreads) {
 366             ProcTraceData->AllocatedThreads = Index;
 367           }
 368           DEBUG ((DEBUG_ERROR, "ProcTrace:  Out of mem, allocating ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
 369           if (Index == 0) {
 370             //
 371             // Could not allocate for BSP
 372             //
 373             FreePool ((VOID *) TopaMemArray);
 374             TopaMemArray = NULL;
 375             return RETURN_OUT_OF_RESOURCES;
 376           }
 377           break;
 378         }
 379
 380         TopaMemArray[Index] = AlignedAddress;
 381         DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index,  (UINT64) TopaMemArray[Index]));
 382       }
 383
 384       DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
 385       //
 386       // BSP gets the first block
 387       //
 388       TopaTableBaseAddr = TopaMemArray[0];
 389     } else {
 390       //
 391       // Count for currently executing AP.
 392       //
 393       if (ProcessorNumber < ProcTraceData->AllocatedThreads) {
 394         TopaTableBaseAddr = ProcTraceData->TopaMemArray[ProcessorNumber];
 395       } else {
 396         return RETURN_SUCCESS;
 397       }
 398     }
 399
 400     TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;
 401     TopaEntryPtr = &TopaTable->TopaEntry[0];
 402     TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
 403     TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
 404     TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
 405     TopaEntryPtr->Bits.END = 0;
 406
 407     TopaEntryPtr = &TopaTable->TopaEntry[1];
 408     TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
 409     TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
 410     TopaEntryPtr->Bits.END = 1;
 411
 412     //
 413     // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
 414     //
 415     OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
 416     OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
 417     CPU_REGISTER_TABLE_WRITE64 (
 418       ProcessorNumber,
 419       Msr,
 420       MSR_IA32_RTIT_OUTPUT_BASE,
 421       OutputBaseReg.Uint64
 422       );
 423
 424     //
 425     // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
 426     //
 427     OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;
 428     OutputMaskPtrsReg.Bits.OutputOffset = 0;
 429     CPU_REGISTER_TABLE_WRITE64 (
 430       ProcessorNumber,
 431       Msr,
 432       MSR_IA32_RTIT_OUTPUT_MASK_PTRS,
 433       OutputMaskPtrsReg.Uint64
 434       );
 435     //
 436     // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8)
 437     //
 438     CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 439     CtrlReg.Bits.ToPA = 1;
 440     CPU_REGISTER_TABLE_WRITE64 (
 441       ProcessorNumber,
 442       Msr,
 443       MSR_IA32_RTIT_CTL,
 444       CtrlReg.Uint64
 445       );
 446   }
 447
 448   ///
 449   /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
 450   ///
 451   CtrlReg.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
 452   CtrlReg.Bits.OS = 1;
 453   CtrlReg.Bits.User = 1;
 454   CtrlReg.Bits.BranchEn = 1;
 455   if (!State) {
 456     CtrlReg.Bits.TraceEn = 0;
 457   } else {
 458     CtrlReg.Bits.TraceEn = 1;
 459   }
 460   CPU_REGISTER_TABLE_WRITE64 (
 461     ProcessorNumber,
 462     Msr,
 463     MSR_IA32_RTIT_CTL,
 464     CtrlReg.Uint64
 465     );
 466
 467   return RETURN_SUCCESS;
 468 }