UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   MpFuncs.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   This is the assembly code for MP support
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 %include "MpEqu.inc"
  22 extern ASM_PFX(InitializeFloatingPointUnits)
  23
  24 DEFAULT REL
  25
  26 SECTION .text
  27
  28 ;-------------------------------------------------------------------------------------
  29 ;RendezvousFunnelProc  procedure follows. All APs execute their procedure. This
  30 ;procedure serializes all the AP processors through an Init sequence. It must be
  31 ;noted that APs arrive here very raw...ie: real mode, no stack.
  32 ;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
  33 ;IS IN MACHINE CODE.
  34 ;-------------------------------------------------------------------------------------
  35 global ASM_PFX(RendezvousFunnelProc)
  36 ASM_PFX(RendezvousFunnelProc):
  37 RendezvousFunnelProcStart:
  38 ; At this point CS = 0x(vv00) and ip= 0x0.
  39 ; Save BIST information to ebp firstly
  40
  41 BITS 16
  42     mov        ebp, eax                        ; Save BIST information
  43
  44     mov        ax, cs
  45     mov        ds, ax
  46     mov        es, ax
  47     mov        ss, ax
  48     xor        ax, ax
  49     mov        fs, ax
  50     mov        gs, ax
  51
  52     mov        si,  BufferStartLocation
  53     mov        ebx, [si]
  54
  55     mov        di,  ModeOffsetLocation
  56     mov        eax, [di]
  57     mov        di,  CodeSegmentLocation
  58     mov        edx, [di]
  59     mov        di,  ax
  60     sub        di,  02h
  61     mov        [di],dx                         ; Patch long mode CS
  62     sub        di,  04h
  63     add        eax, ebx
  64     mov        [di],eax                        ; Patch address
  65
  66     mov        si, GdtrLocation
  67 o32 lgdt       [cs:si]
  68
  69     mov        si, IdtrLocation
  70 o32 lidt       [cs:si]
  71
  72     mov        si, EnableExecuteDisableLocation
  73     cmp        byte [si], 0
  74     jz         SkipEnableExecuteDisableBit
  75
  76     ;
  77     ; Enable execute disable bit
  78     ;
  79     mov        ecx, 0c0000080h             ; EFER MSR number
  80     rdmsr                                  ; Read EFER
  81     bts        eax, 11                     ; Enable Execute Disable Bit
  82     wrmsr                                  ; Write EFER
  83
  84 SkipEnableExecuteDisableBit:
  85
  86     mov        di,  DataSegmentLocation
  87     mov        edi, [di]                   ; Save long mode DS in edi
  88
  89     mov        si, Cr3Location             ; Save CR3 in ecx
  90     mov        ecx, [si]
  91
  92     xor        ax,  ax
  93     mov        ds,  ax                     ; Clear data segment
  94
  95     mov        eax, cr0                    ; Get control register 0
  96     or         eax, 000000003h             ; Set PE bit (bit #0) & MP
  97     mov        cr0, eax
  98
  99     mov        eax, cr4
 100     bts        eax, 5
 101     mov        cr4, eax
 102
 103     mov        cr3, ecx                    ; Load CR3
 104
 105     mov        ecx, 0c0000080h             ; EFER MSR number
 106     rdmsr                                  ; Read EFER
 107     bts        eax, 8                      ; Set LME=1
 108     wrmsr                                  ; Write EFER
 109
 110     mov        eax, cr0                    ; Read CR0
 111     bts        eax, 31                     ; Set PG=1
 112     mov        cr0, eax                    ; Write CR0
 113
 114     jmp        0:strict dword 0  ; far jump to long mode
 115 BITS 64
 116 LongModeStart:
 117     mov        eax, edi
 118     mov        ds,  ax
 119     mov        es,  ax
 120     mov        ss,  ax
 121
 122     mov        esi, ebx
 123     lea        edi, [esi + InitFlagLocation]
 124     cmp        qword [edi], 1       ; ApInitConfig
 125     jnz        GetApicId
 126
 127     ; AP init
 128     mov        edi, esi
 129     add        edi, LockLocation
 130     mov        rax, NotVacantFlag
 131
 132 TestLock:
 133     xchg       qword [edi], rax
 134     cmp        rax, NotVacantFlag
 135     jz         TestLock
 136
 137     lea        ecx, [esi + NumApsExecutingLocation]
 138     inc        dword [ecx]
 139     mov        ebx, [ecx]
 140
 141 Releaselock:
 142     mov        rax, VacantFlag
 143     xchg       qword [edi], rax
 144     ; program stack
 145     mov        edi, esi
 146     add        edi, StackSizeLocation
 147     mov        eax, dword [edi]
 148     mov        ecx, ebx
 149     inc        ecx
 150     mul        ecx                               ; EAX = StackSize * (CpuNumber + 1)
 151     mov        edi, esi
 152     add        edi, StackStartAddressLocation
 153     add        rax, qword [edi]
 154     mov        rsp, rax
 155     jmp        CProcedureInvoke
 156
 157 GetApicId:
 158     mov        eax, 0
 159     cpuid
 160     cmp        eax, 0bh
 161     jnb        X2Apic
 162     ; Processor is not x2APIC capable, so get 8-bit APIC ID
 163     mov        eax, 1
 164     cpuid
 165     shr        ebx, 24
 166     mov        edx, ebx
 167     jmp        GetProcessorNumber
 168
 169 X2Apic:
 170     ; Processor is x2APIC capable, so get 32-bit x2APIC ID
 171     mov        eax, 0bh
 172     xor        ecx, ecx
 173     cpuid
 174     ; edx save x2APIC ID
 175
 176 GetProcessorNumber:
 177     ;
 178     ; Get processor number for this AP
 179     ; Note that BSP may become an AP due to SwitchBsp()
 180     ;
 181     xor         ebx, ebx
 182     lea         eax, [esi + CpuInfoLocation]
 183     mov         edi, [eax]
 184
 185 GetNextProcNumber:
 186     cmp         dword [edi], edx                      ; APIC ID match?
 187     jz          ProgramStack
 188     add         edi, 20
 189     inc         ebx
 190     jmp         GetNextProcNumber
 191
 192 ProgramStack:
 193     mov         rsp, qword [edi + 12]
 194
 195 CProcedureInvoke:
 196     push       rbp               ; Push BIST data at top of AP stack
 197     xor        rbp, rbp          ; Clear ebp for call stack trace
 198     push       rbp
 199     mov        rbp, rsp
 200
 201     mov        rax, ASM_PFX(InitializeFloatingPointUnits)
 202     sub        rsp, 20h
 203     call       rax               ; Call assembly function to initialize FPU per UEFI spec
 204     add        rsp, 20h
 205
 206     mov        edx, ebx          ; edx is NumApsExecuting
 207     mov        ecx, esi
 208     add        ecx, LockLocation ; rcx is address of exchange info data buffer
 209
 210     mov        edi, esi
 211     add        edi, ApProcedureLocation
 212     mov        rax, qword [edi]
 213
 214     sub        rsp, 20h
 215     call       rax               ; Invoke C function
 216     add        rsp, 20h
 217     jmp        $                 ; Should never reach here
 218
 219 RendezvousFunnelProcEnd:
 220
 221 ;-------------------------------------------------------------------------------------
 222 ;  AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment);
 223 ;-------------------------------------------------------------------------------------
 224 global ASM_PFX(AsmRelocateApLoop)
 225 ASM_PFX(AsmRelocateApLoop):
 226 AsmRelocateApLoopStart:
 227     push       rcx
 228     push       rdx
 229
 230     lea        rsi, [PmEntry]    ; rsi <- The start address of transition code
 231
 232     push       r8
 233     push       rsi
 234     DB         0x48
 235     retf
 236 BITS 32
 237 PmEntry:
 238     mov        eax, cr0
 239     btr        eax, 31           ; Clear CR0.PG
 240     mov        cr0, eax          ; Disable paging and caches
 241
 242     mov        ebx, edx          ; Save EntryPoint to rbx, for rdmsr will overwrite rdx
 243     mov        ecx, 0xc0000080
 244     rdmsr
 245     and        ah, ~ 1           ; Clear LME
 246     wrmsr
 247     mov        eax, cr4
 248     and        al, ~ (1 << 5)    ; Clear PAE
 249     mov        cr4, eax
 250
 251     pop        edx
 252     add        esp, 4
 253     pop        ecx,
 254     add        esp, 4
 255     cmp        cl, 1              ; Check mwait-monitor support
 256     jnz        HltLoop
 257     mov        ebx, edx           ; Save C-State to ebx
 258 MwaitLoop:
 259     mov        eax, esp           ; Set Monitor Address
 260     xor        ecx, ecx           ; ecx = 0
 261     xor        edx, edx           ; edx = 0
 262     monitor
 263     shl        ebx, 4
 264     mov        eax, ebx           ; Mwait Cx, Target C-State per eax[7:4]
 265     mwait
 266     jmp        MwaitLoop
 267 HltLoop:
 268     cli
 269     hlt
 270     jmp        HltLoop
 271     ret
 272 BITS 64
 273 AsmRelocateApLoopEnd:
 274
 275 ;-------------------------------------------------------------------------------------
 276 ;  AsmGetAddressMap (&AddressMap);
 277 ;-------------------------------------------------------------------------------------
 278 global ASM_PFX(AsmGetAddressMap)
 279 ASM_PFX(AsmGetAddressMap):
 280     mov        rax, ASM_PFX(RendezvousFunnelProc)
 281     mov        qword [rcx], rax
 282     mov        qword [rcx +  8h], LongModeStart - RendezvousFunnelProcStart
 283     mov        qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
 284     mov        rax, ASM_PFX(AsmRelocateApLoop)
 285     mov        qword [rcx + 18h], rax
 286     mov        qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
 287     ret
 288
 289 ;-------------------------------------------------------------------------------------
 290 ;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
 291 ;about to become an AP. It switches its stack with the current AP.
 292 ;AsmExchangeRole (IN   CPU_EXCHANGE_INFO    *MyInfo, IN   CPU_EXCHANGE_INFO    *OthersInfo);
 293 ;-------------------------------------------------------------------------------------
 294 global ASM_PFX(AsmExchangeRole)
 295 ASM_PFX(AsmExchangeRole):
 296     ; DO NOT call other functions in this function, since 2 CPU may use 1 stack
 297     ; at the same time. If 1 CPU try to call a function, stack will be corrupted.
 298
 299     push       rax
 300     push       rbx
 301     push       rcx
 302     push       rdx
 303     push       rsi
 304     push       rdi
 305     push       rbp
 306     push       r8
 307     push       r9
 308     push       r10
 309     push       r11
 310     push       r12
 311     push       r13
 312     push       r14
 313     push       r15
 314
 315     mov        rax, cr0
 316     push       rax
 317
 318     mov        rax, cr4
 319     push       rax
 320
 321     ; rsi contains MyInfo pointer
 322     mov        rsi, rcx
 323
 324     ; rdi contains OthersInfo pointer
 325     mov        rdi, rdx
 326
 327     ;Store EFLAGS, GDTR and IDTR regiter to stack
 328     pushfq
 329     sgdt       [rsi + 16]
 330     sidt       [rsi + 26]
 331
 332     ; Store the its StackPointer
 333     mov        [rsi + 8], rsp
 334
 335     ; update its switch state to STORED
 336     mov        byte [rsi], CPU_SWITCH_STATE_STORED
 337
 338 WaitForOtherStored:
 339     ; wait until the other CPU finish storing its state
 340     cmp        byte [rdi], CPU_SWITCH_STATE_STORED
 341     jz         OtherStored
 342     pause
 343     jmp        WaitForOtherStored
 344
 345 OtherStored:
 346     ; Since another CPU already stored its state, load them
 347     ; load GDTR value
 348     lgdt       [rdi + 16]
 349
 350     ; load IDTR value
 351     lidt       [rdi + 26]
 352
 353     ; load its future StackPointer
 354     mov        rsp, [rdi + 8]
 355
 356     ; update the other CPU's switch state to LOADED
 357     mov        byte [rdi], CPU_SWITCH_STATE_LOADED
 358
 359 WaitForOtherLoaded:
 360     ; wait until the other CPU finish loading new state,
 361     ; otherwise the data in stack may corrupt
 362     cmp        byte [rsi], CPU_SWITCH_STATE_LOADED
 363     jz         OtherLoaded
 364     pause
 365     jmp        WaitForOtherLoaded
 366
 367 OtherLoaded:
 368     ; since the other CPU already get the data it want, leave this procedure
 369     popfq
 370
 371     pop        rax
 372     mov        cr4, rax
 373
 374     pop        rax
 375     mov        cr0, rax
 376
 377     pop        r15
 378     pop        r14
 379     pop        r13
 380     pop        r12
 381     pop        r11
 382     pop        r10
 383     pop        r9
 384     pop        r8
 385     pop        rbp
 386     pop        rdi
 387     pop        rsi
 388     pop        rdx
 389     pop        rcx
 390     pop        rbx
 391     pop        rax
 392
 393     ret