ddf90e2a8c0fea3e035a642958549f5020d16889
[mirror_edk2.git] / UefiCpuPkg / Library / MtrrLib / MtrrLib.c
1 /** @file
2 MTRR setting library
3
4 @par Note:
5 Most of services in this library instance are suggested to be invoked by BSP only,
6 except for MtrrSetAllMtrrs() which is used to sync BSP's MTRR setting to APs.
7
8 Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #include <Uefi.h>
20 #include <Register/Cpuid.h>
21 #include <Register/Msr.h>
22
23 #include <Library/MtrrLib.h>
24 #include <Library/BaseLib.h>
25 #include <Library/CpuLib.h>
26 #include <Library/BaseMemoryLib.h>
27 #include <Library/DebugLib.h>
28
29 #define OR_SEED 0x0101010101010101ull
30 #define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull
31 #define MAX_WEIGHT MAX_UINT8
32 #define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB)
33 #define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);
34
35 #define M(x,y) ((x) * VectorCount + (y))
36 #define O(x,y) ((y) * VectorCount + (x))
37
38 //
39 // Context to save and restore when MTRRs are programmed
40 //
41 typedef struct {
42 UINTN Cr4;
43 BOOLEAN InterruptState;
44 } MTRR_CONTEXT;
45
46 typedef struct {
47 UINT64 Address;
48 UINT64 Alignment;
49 UINT64 Length;
50 UINT8 Type : 7;
51
52 //
53 // Temprary use for calculating the best MTRR settings.
54 //
55 BOOLEAN Visited : 1;
56 UINT8 Weight;
57 UINT16 Previous;
58 } MTRR_LIB_ADDRESS;
59
60 //
61 // This table defines the offset, base and length of the fixed MTRRs
62 //
63 CONST FIXED_MTRR mMtrrLibFixedMtrrTable[] = {
64 {
65 MSR_IA32_MTRR_FIX64K_00000,
66 0,
67 SIZE_64KB
68 },
69 {
70 MSR_IA32_MTRR_FIX16K_80000,
71 0x80000,
72 SIZE_16KB
73 },
74 {
75 MSR_IA32_MTRR_FIX16K_A0000,
76 0xA0000,
77 SIZE_16KB
78 },
79 {
80 MSR_IA32_MTRR_FIX4K_C0000,
81 0xC0000,
82 SIZE_4KB
83 },
84 {
85 MSR_IA32_MTRR_FIX4K_C8000,
86 0xC8000,
87 SIZE_4KB
88 },
89 {
90 MSR_IA32_MTRR_FIX4K_D0000,
91 0xD0000,
92 SIZE_4KB
93 },
94 {
95 MSR_IA32_MTRR_FIX4K_D8000,
96 0xD8000,
97 SIZE_4KB
98 },
99 {
100 MSR_IA32_MTRR_FIX4K_E0000,
101 0xE0000,
102 SIZE_4KB
103 },
104 {
105 MSR_IA32_MTRR_FIX4K_E8000,
106 0xE8000,
107 SIZE_4KB
108 },
109 {
110 MSR_IA32_MTRR_FIX4K_F0000,
111 0xF0000,
112 SIZE_4KB
113 },
114 {
115 MSR_IA32_MTRR_FIX4K_F8000,
116 0xF8000,
117 SIZE_4KB
118 }
119 };
120
121 //
122 // Lookup table used to print MTRRs
123 //
124 GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {
125 "UC", // CacheUncacheable
126 "WC", // CacheWriteCombining
127 "R*", // Invalid
128 "R*", // Invalid
129 "WT", // CacheWriteThrough
130 "WP", // CacheWriteProtected
131 "WB", // CacheWriteBack
132 "R*" // Invalid
133 };
134
135
136 /**
137 Worker function prints all MTRRs for debugging.
138
139 If MtrrSetting is not NULL, print MTRR settings from input MTRR
140 settings buffer.
141 If MtrrSetting is NULL, print MTRR settings from MTRRs.
142
143 @param MtrrSetting A buffer holding all MTRRs content.
144 **/
145 VOID
146 MtrrDebugPrintAllMtrrsWorker (
147 IN MTRR_SETTINGS *MtrrSetting
148 );
149
150 /**
151 Worker function returns the variable MTRR count for the CPU.
152
153 @return Variable MTRR count
154
155 **/
156 UINT32
157 GetVariableMtrrCountWorker (
158 VOID
159 )
160 {
161 MSR_IA32_MTRRCAP_REGISTER MtrrCap;
162
163 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
164 ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0)->Mtrr));
165 return MtrrCap.Bits.VCNT;
166 }
167
168 /**
169 Returns the variable MTRR count for the CPU.
170
171 @return Variable MTRR count
172
173 **/
174 UINT32
175 EFIAPI
176 GetVariableMtrrCount (
177 VOID
178 )
179 {
180 if (!IsMtrrSupported ()) {
181 return 0;
182 }
183 return GetVariableMtrrCountWorker ();
184 }
185
186 /**
187 Worker function returns the firmware usable variable MTRR count for the CPU.
188
189 @return Firmware usable variable MTRR count
190
191 **/
192 UINT32
193 GetFirmwareVariableMtrrCountWorker (
194 VOID
195 )
196 {
197 UINT32 VariableMtrrCount;
198 UINT32 ReservedMtrrNumber;
199
200 VariableMtrrCount = GetVariableMtrrCountWorker ();
201 ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);
202 if (VariableMtrrCount < ReservedMtrrNumber) {
203 return 0;
204 }
205
206 return VariableMtrrCount - ReservedMtrrNumber;
207 }
208
209 /**
210 Returns the firmware usable variable MTRR count for the CPU.
211
212 @return Firmware usable variable MTRR count
213
214 **/
215 UINT32
216 EFIAPI
217 GetFirmwareVariableMtrrCount (
218 VOID
219 )
220 {
221 if (!IsMtrrSupported ()) {
222 return 0;
223 }
224 return GetFirmwareVariableMtrrCountWorker ();
225 }
226
227 /**
228 Worker function returns the default MTRR cache type for the system.
229
230 If MtrrSetting is not NULL, returns the default MTRR cache type from input
231 MTRR settings buffer.
232 If MtrrSetting is NULL, returns the default MTRR cache type from MSR.
233
234 @param[in] MtrrSetting A buffer holding all MTRRs content.
235
236 @return The default MTRR cache type.
237
238 **/
239 MTRR_MEMORY_CACHE_TYPE
240 MtrrGetDefaultMemoryTypeWorker (
241 IN MTRR_SETTINGS *MtrrSetting
242 )
243 {
244 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
245
246 if (MtrrSetting == NULL) {
247 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
248 } else {
249 DefType.Uint64 = MtrrSetting->MtrrDefType;
250 }
251
252 return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;
253 }
254
255
256 /**
257 Returns the default MTRR cache type for the system.
258
259 @return The default MTRR cache type.
260
261 **/
262 MTRR_MEMORY_CACHE_TYPE
263 EFIAPI
264 MtrrGetDefaultMemoryType (
265 VOID
266 )
267 {
268 if (!IsMtrrSupported ()) {
269 return CacheUncacheable;
270 }
271 return MtrrGetDefaultMemoryTypeWorker (NULL);
272 }
273
274 /**
275 Preparation before programming MTRR.
276
277 This function will do some preparation for programming MTRRs:
278 disable cache, invalid cache and disable MTRR caching functionality
279
280 @param[out] MtrrContext Pointer to context to save
281
282 **/
283 VOID
284 MtrrLibPreMtrrChange (
285 OUT MTRR_CONTEXT *MtrrContext
286 )
287 {
288 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
289 //
290 // Disable interrupts and save current interrupt state
291 //
292 MtrrContext->InterruptState = SaveAndDisableInterrupts();
293
294 //
295 // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)
296 //
297 AsmDisableCache ();
298
299 //
300 // Save original CR4 value and clear PGE flag (Bit 7)
301 //
302 MtrrContext->Cr4 = AsmReadCr4 ();
303 AsmWriteCr4 (MtrrContext->Cr4 & (~BIT7));
304
305 //
306 // Flush all TLBs
307 //
308 CpuFlushTlb ();
309
310 //
311 // Disable MTRRs
312 //
313 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
314 DefType.Bits.E = 0;
315 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
316 }
317
318 /**
319 Cleaning up after programming MTRRs.
320
321 This function will do some clean up after programming MTRRs:
322 Flush all TLBs, re-enable caching, restore CR4.
323
324 @param[in] MtrrContext Pointer to context to restore
325
326 **/
327 VOID
328 MtrrLibPostMtrrChangeEnableCache (
329 IN MTRR_CONTEXT *MtrrContext
330 )
331 {
332 //
333 // Flush all TLBs
334 //
335 CpuFlushTlb ();
336
337 //
338 // Enable Normal Mode caching CD=NW=0, CD(Bit30), NW(Bit29)
339 //
340 AsmEnableCache ();
341
342 //
343 // Restore original CR4 value
344 //
345 AsmWriteCr4 (MtrrContext->Cr4);
346
347 //
348 // Restore original interrupt state
349 //
350 SetInterruptState (MtrrContext->InterruptState);
351 }
352
353 /**
354 Cleaning up after programming MTRRs.
355
356 This function will do some clean up after programming MTRRs:
357 enable MTRR caching functionality, and enable cache
358
359 @param[in] MtrrContext Pointer to context to restore
360
361 **/
362 VOID
363 MtrrLibPostMtrrChange (
364 IN MTRR_CONTEXT *MtrrContext
365 )
366 {
367 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
368 //
369 // Enable Cache MTRR
370 //
371 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
372 DefType.Bits.E = 1;
373 DefType.Bits.FE = 1;
374 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
375
376 MtrrLibPostMtrrChangeEnableCache (MtrrContext);
377 }
378
379 /**
380 Worker function gets the content in fixed MTRRs
381
382 @param[out] FixedSettings A buffer to hold fixed MTRRs content.
383
384 @retval The pointer of FixedSettings
385
386 **/
387 MTRR_FIXED_SETTINGS*
388 MtrrGetFixedMtrrWorker (
389 OUT MTRR_FIXED_SETTINGS *FixedSettings
390 )
391 {
392 UINT32 Index;
393
394 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
395 FixedSettings->Mtrr[Index] =
396 AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);
397 }
398
399 return FixedSettings;
400 }
401
402
403 /**
404 This function gets the content in fixed MTRRs
405
406 @param[out] FixedSettings A buffer to hold fixed MTRRs content.
407
408 @retval The pointer of FixedSettings
409
410 **/
411 MTRR_FIXED_SETTINGS*
412 EFIAPI
413 MtrrGetFixedMtrr (
414 OUT MTRR_FIXED_SETTINGS *FixedSettings
415 )
416 {
417 if (!IsMtrrSupported ()) {
418 return FixedSettings;
419 }
420
421 return MtrrGetFixedMtrrWorker (FixedSettings);
422 }
423
424
425 /**
426 Worker function will get the raw value in variable MTRRs
427
428 If MtrrSetting is not NULL, gets the variable MTRRs raw value from input
429 MTRR settings buffer.
430 If MtrrSetting is NULL, gets the variable MTRRs raw value from MTRRs.
431
432 @param[in] MtrrSetting A buffer holding all MTRRs content.
433 @param[in] VariableMtrrCount Number of variable MTRRs.
434 @param[out] VariableSettings A buffer to hold variable MTRRs content.
435
436 @return The VariableSettings input pointer
437
438 **/
439 MTRR_VARIABLE_SETTINGS*
440 MtrrGetVariableMtrrWorker (
441 IN MTRR_SETTINGS *MtrrSetting,
442 IN UINT32 VariableMtrrCount,
443 OUT MTRR_VARIABLE_SETTINGS *VariableSettings
444 )
445 {
446 UINT32 Index;
447
448 ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));
449
450 for (Index = 0; Index < VariableMtrrCount; Index++) {
451 if (MtrrSetting == NULL) {
452 VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));
453 //
454 // Skip to read the Base MSR when the Mask.V is not set.
455 //
456 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
457 VariableSettings->Mtrr[Index].Base = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));
458 }
459 } else {
460 VariableSettings->Mtrr[Index].Base = MtrrSetting->Variables.Mtrr[Index].Base;
461 VariableSettings->Mtrr[Index].Mask = MtrrSetting->Variables.Mtrr[Index].Mask;
462 }
463 }
464
465 return VariableSettings;
466 }
467
468 /**
469 This function will get the raw value in variable MTRRs
470
471 @param[out] VariableSettings A buffer to hold variable MTRRs content.
472
473 @return The VariableSettings input pointer
474
475 **/
476 MTRR_VARIABLE_SETTINGS*
477 EFIAPI
478 MtrrGetVariableMtrr (
479 OUT MTRR_VARIABLE_SETTINGS *VariableSettings
480 )
481 {
482 if (!IsMtrrSupported ()) {
483 return VariableSettings;
484 }
485
486 return MtrrGetVariableMtrrWorker (
487 NULL,
488 GetVariableMtrrCountWorker (),
489 VariableSettings
490 );
491 }
492
493 /**
494 Programs fixed MTRRs registers.
495
496 @param[in] Type The memory type to set.
497 @param[in, out] Base The base address of memory range.
498 @param[in, out] Length The length of memory range.
499 @param[in, out] LastMsrIndex On input, the last index of the fixed MTRR MSR to program.
500 On return, the current index of the fixed MTRR MSR to program.
501 @param[out] ClearMask The bits to clear in the fixed MTRR MSR.
502 @param[out] OrMask The bits to set in the fixed MTRR MSR.
503
504 @retval RETURN_SUCCESS The cache type was updated successfully
505 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid
506 for the fixed MTRRs.
507
508 **/
509 RETURN_STATUS
510 MtrrLibProgramFixedMtrr (
511 IN MTRR_MEMORY_CACHE_TYPE Type,
512 IN OUT UINT64 *Base,
513 IN OUT UINT64 *Length,
514 IN OUT UINT32 *LastMsrIndex,
515 OUT UINT64 *ClearMask,
516 OUT UINT64 *OrMask
517 )
518 {
519 UINT32 MsrIndex;
520 UINT32 LeftByteShift;
521 UINT32 RightByteShift;
522 UINT64 SubLength;
523
524 //
525 // Find the fixed MTRR index to be programmed
526 //
527 for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {
528 if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) &&
529 (*Base <
530 (
531 mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +
532 (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)
533 )
534 )
535 ) {
536 break;
537 }
538 }
539
540 ASSERT (MsrIndex != ARRAY_SIZE (mMtrrLibFixedMtrrTable));
541
542 //
543 // Find the begin offset in fixed MTRR and calculate byte offset of left shift
544 //
545 if ((((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {
546 //
547 // Base address should be aligned to the begin of a certain Fixed MTRR range.
548 //
549 return RETURN_UNSUPPORTED;
550 }
551 LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length;
552 ASSERT (LeftByteShift < 8);
553
554 //
555 // Find the end offset in fixed MTRR and calculate byte offset of right shift
556 //
557 SubLength = mMtrrLibFixedMtrrTable[MsrIndex].Length * (8 - LeftByteShift);
558 if (*Length >= SubLength) {
559 RightByteShift = 0;
560 } else {
561 if (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrIndex].Length) != 0) {
562 //
563 // Length should be aligned to the end of a certain Fixed MTRR range.
564 //
565 return RETURN_UNSUPPORTED;
566 }
567 RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length;
568 //
569 // Update SubLength by actual length
570 //
571 SubLength = *Length;
572 }
573
574 *ClearMask = CLEAR_SEED;
575 *OrMask = MultU64x32 (OR_SEED, (UINT32) Type);
576
577 if (LeftByteShift != 0) {
578 //
579 // Clear the low bits by LeftByteShift
580 //
581 *ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8);
582 *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8);
583 }
584
585 if (RightByteShift != 0) {
586 //
587 // Clear the high bits by RightByteShift
588 //
589 *ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8);
590 *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8);
591 }
592
593 *Length -= SubLength;
594 *Base += SubLength;
595
596 *LastMsrIndex = MsrIndex;
597
598 return RETURN_SUCCESS;
599 }
600
601
602 /**
603 Worker function gets the attribute of variable MTRRs.
604
605 This function shadows the content of variable MTRRs into an
606 internal array: VariableMtrr.
607
608 @param[in] VariableSettings The variable MTRR values to shadow
609 @param[in] VariableMtrrCount The number of variable MTRRs
610 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
611 @param[in] MtrrValidAddressMask The valid address mask for MTRR
612 @param[out] VariableMtrr The array to shadow variable MTRRs content
613
614 @return Number of MTRRs which has been used.
615
616 **/
617 UINT32
618 MtrrGetMemoryAttributeInVariableMtrrWorker (
619 IN MTRR_VARIABLE_SETTINGS *VariableSettings,
620 IN UINTN VariableMtrrCount,
621 IN UINT64 MtrrValidBitsMask,
622 IN UINT64 MtrrValidAddressMask,
623 OUT VARIABLE_MTRR *VariableMtrr
624 )
625 {
626 UINTN Index;
627 UINT32 UsedMtrr;
628
629 ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSettings->Mtrr));
630 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {
631 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
632 VariableMtrr[Index].Msr = (UINT32)Index;
633 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);
634 VariableMtrr[Index].Length =
635 ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
636 VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff);
637 VariableMtrr[Index].Valid = TRUE;
638 VariableMtrr[Index].Used = TRUE;
639 UsedMtrr++;
640 }
641 }
642 return UsedMtrr;
643 }
644
645 /**
646 Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.
647 One MTRR_MEMORY_RANGE element is created for each MTRR setting.
648 The routine doesn't remove the overlap or combine the near-by region.
649
650 @param[in] VariableSettings The variable MTRR values to shadow
651 @param[in] VariableMtrrCount The number of variable MTRRs
652 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
653 @param[in] MtrrValidAddressMask The valid address mask for MTRR
654 @param[out] VariableMtrr The array to shadow variable MTRRs content
655
656 @return Number of MTRRs which has been used.
657
658 **/
659 UINT32
660 MtrrLibGetRawVariableRanges (
661 IN MTRR_VARIABLE_SETTINGS *VariableSettings,
662 IN UINTN VariableMtrrCount,
663 IN UINT64 MtrrValidBitsMask,
664 IN UINT64 MtrrValidAddressMask,
665 OUT MTRR_MEMORY_RANGE *VariableMtrr
666 )
667 {
668 UINTN Index;
669 UINT32 UsedMtrr;
670
671 ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (VariableSettings->Mtrr));
672 for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {
673 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
674 VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);
675 VariableMtrr[Index].Length =
676 ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
677 VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);
678 UsedMtrr++;
679 }
680 }
681 return UsedMtrr;
682 }
683
684 /**
685 Gets the attribute of variable MTRRs.
686
687 This function shadows the content of variable MTRRs into an
688 internal array: VariableMtrr.
689
690 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
691 @param[in] MtrrValidAddressMask The valid address mask for MTRR
692 @param[out] VariableMtrr The array to shadow variable MTRRs content
693
694 @return The return value of this parameter indicates the
695 number of MTRRs which has been used.
696
697 **/
698 UINT32
699 EFIAPI
700 MtrrGetMemoryAttributeInVariableMtrr (
701 IN UINT64 MtrrValidBitsMask,
702 IN UINT64 MtrrValidAddressMask,
703 OUT VARIABLE_MTRR *VariableMtrr
704 )
705 {
706 MTRR_VARIABLE_SETTINGS VariableSettings;
707
708 if (!IsMtrrSupported ()) {
709 return 0;
710 }
711
712 MtrrGetVariableMtrrWorker (
713 NULL,
714 GetVariableMtrrCountWorker (),
715 &VariableSettings
716 );
717
718 return MtrrGetMemoryAttributeInVariableMtrrWorker (
719 &VariableSettings,
720 GetFirmwareVariableMtrrCountWorker (),
721 MtrrValidBitsMask,
722 MtrrValidAddressMask,
723 VariableMtrr
724 );
725 }
726
727 /**
728 Return the biggest alignment (lowest set bit) of address.
729 The function is equivalent to: 1 << LowBitSet64 (Address).
730
731 @param Address The address to return the alignment.
732 @param Alignment0 The alignment to return when Address is 0.
733
734 @return The least alignment of the Address.
735 **/
736 UINT64
737 MtrrLibBiggestAlignment (
738 UINT64 Address,
739 UINT64 Alignment0
740 )
741 {
742 if (Address == 0) {
743 return Alignment0;
744 }
745
746 return Address & ((~Address) + 1);
747 }
748
749 /**
750 Return whether the left MTRR type precedes the right MTRR type.
751
752 The MTRR type precedence rules are:
753 1. UC precedes any other type
754 2. WT precedes WB
755 For further details, please refer the IA32 Software Developer's Manual,
756 Volume 3, Section "MTRR Precedences".
757
758 @param Left The left MTRR type.
759 @param Right The right MTRR type.
760
761 @retval TRUE Left precedes Right.
762 @retval FALSE Left doesn't precede Right.
763 **/
764 BOOLEAN
765 MtrrLibTypeLeftPrecedeRight (
766 IN MTRR_MEMORY_CACHE_TYPE Left,
767 IN MTRR_MEMORY_CACHE_TYPE Right
768 )
769 {
770 return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));
771 }
772
773 /**
774 Initializes the valid bits mask and valid address mask for MTRRs.
775
776 This function initializes the valid bits mask and valid address mask for MTRRs.
777
778 @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR
779 @param[out] MtrrValidAddressMask The valid address mask for the MTRR
780
781 **/
782 VOID
783 MtrrLibInitializeMtrrMask (
784 OUT UINT64 *MtrrValidBitsMask,
785 OUT UINT64 *MtrrValidAddressMask
786 )
787 {
788 UINT32 MaxExtendedFunction;
789 CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
790
791
792 AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
793
794 if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
795 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
796 } else {
797 VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
798 }
799
800 *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
801 *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
802 }
803
804
805 /**
806 Determines the real attribute of a memory range.
807
808 This function is to arbitrate the real attribute of the memory when
809 there are 2 MTRRs covers the same memory range. For further details,
810 please refer the IA32 Software Developer's Manual, Volume 3,
811 Section "MTRR Precedences".
812
813 @param[in] MtrrType1 The first kind of Memory type
814 @param[in] MtrrType2 The second kind of memory type
815
816 **/
817 MTRR_MEMORY_CACHE_TYPE
818 MtrrLibPrecedence (
819 IN MTRR_MEMORY_CACHE_TYPE MtrrType1,
820 IN MTRR_MEMORY_CACHE_TYPE MtrrType2
821 )
822 {
823 if (MtrrType1 == MtrrType2) {
824 return MtrrType1;
825 }
826
827 ASSERT (
828 MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) ||
829 MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1)
830 );
831
832 if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) {
833 return MtrrType1;
834 } else {
835 return MtrrType2;
836 }
837 }
838
839 /**
840 Worker function will get the memory cache type of the specific address.
841
842 If MtrrSetting is not NULL, gets the memory cache type from input
843 MTRR settings buffer.
844 If MtrrSetting is NULL, gets the memory cache type from MTRRs.
845
846 @param[in] MtrrSetting A buffer holding all MTRRs content.
847 @param[in] Address The specific address
848
849 @return Memory cache type of the specific address
850
851 **/
852 MTRR_MEMORY_CACHE_TYPE
853 MtrrGetMemoryAttributeByAddressWorker (
854 IN MTRR_SETTINGS *MtrrSetting,
855 IN PHYSICAL_ADDRESS Address
856 )
857 {
858 MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
859 UINT64 FixedMtrr;
860 UINTN Index;
861 UINTN SubIndex;
862 MTRR_MEMORY_CACHE_TYPE MtrrType;
863 MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
864 UINT64 MtrrValidBitsMask;
865 UINT64 MtrrValidAddressMask;
866 UINT32 VariableMtrrCount;
867 MTRR_VARIABLE_SETTINGS VariableSettings;
868
869 //
870 // Check if MTRR is enabled, if not, return UC as attribute
871 //
872 if (MtrrSetting == NULL) {
873 DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
874 } else {
875 DefType.Uint64 = MtrrSetting->MtrrDefType;
876 }
877
878 if (DefType.Bits.E == 0) {
879 return CacheUncacheable;
880 }
881
882 //
883 // If address is less than 1M, then try to go through the fixed MTRR
884 //
885 if (Address < BASE_1MB) {
886 if (DefType.Bits.FE != 0) {
887 //
888 // Go through the fixed MTRR
889 //
890 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
891 if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress &&
892 Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +
893 (mMtrrLibFixedMtrrTable[Index].Length * 8)) {
894 SubIndex =
895 ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /
896 mMtrrLibFixedMtrrTable[Index].Length;
897 if (MtrrSetting == NULL) {
898 FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);
899 } else {
900 FixedMtrr = MtrrSetting->Fixed.Mtrr[Index];
901 }
902 return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);
903 }
904 }
905 }
906 }
907
908 VariableMtrrCount = GetVariableMtrrCountWorker ();
909 ASSERT (VariableMtrrCount <= ARRAY_SIZE (MtrrSetting->Variables.Mtrr));
910 MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSettings);
911
912 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
913 MtrrLibGetRawVariableRanges (
914 &VariableSettings,
915 VariableMtrrCount,
916 MtrrValidBitsMask,
917 MtrrValidAddressMask,
918 VariableMtrr
919 );
920
921 //
922 // Go through the variable MTRR
923 //
924 MtrrType = CacheInvalid;
925 for (Index = 0; Index < VariableMtrrCount; Index++) {
926 if (VariableMtrr[Index].Length != 0) {
927 if (Address >= VariableMtrr[Index].BaseAddress &&
928 Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) {
929 if (MtrrType == CacheInvalid) {
930 MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type;
931 } else {
932 MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type);
933 }
934 }
935 }
936 }
937
938 //
939 // If there is no MTRR which covers the Address, use the default MTRR type.
940 //
941 if (MtrrType == CacheInvalid) {
942 MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;
943 }
944
945 return MtrrType;
946 }
947
948
949 /**
950 This function will get the memory cache type of the specific address.
951
952 This function is mainly for debug purpose.
953
954 @param[in] Address The specific address
955
956 @return Memory cache type of the specific address
957
958 **/
959 MTRR_MEMORY_CACHE_TYPE
960 EFIAPI
961 MtrrGetMemoryAttribute (
962 IN PHYSICAL_ADDRESS Address
963 )
964 {
965 if (!IsMtrrSupported ()) {
966 return CacheUncacheable;
967 }
968
969 return MtrrGetMemoryAttributeByAddressWorker (NULL, Address);
970 }
971
972 /**
973 Update the Ranges array to change the specified range identified by
974 BaseAddress and Length to Type.
975
976 @param Ranges Array holding memory type settings for all memory regions.
977 @param Capacity The maximum count of memory ranges the array can hold.
978 @param Count Return the new memory range count in the array.
979 @param BaseAddress The base address of the memory range to change type.
980 @param Length The length of the memory range to change type.
981 @param Type The new type of the specified memory range.
982
983 @retval RETURN_SUCCESS The type of the specified memory range is
984 changed successfully.
985 @retval RETURN_ALREADY_STARTED The type of the specified memory range equals
986 to the desired type.
987 @retval RETURN_OUT_OF_RESOURCES The new type set causes the count of memory
988 range exceeds capacity.
989 **/
990 RETURN_STATUS
991 MtrrLibSetMemoryType (
992 IN MTRR_MEMORY_RANGE *Ranges,
993 IN UINTN Capacity,
994 IN OUT UINTN *Count,
995 IN UINT64 BaseAddress,
996 IN UINT64 Length,
997 IN MTRR_MEMORY_CACHE_TYPE Type
998 )
999 {
1000 UINTN Index;
1001 UINT64 Limit;
1002 UINT64 LengthLeft;
1003 UINT64 LengthRight;
1004 UINTN StartIndex;
1005 UINTN EndIndex;
1006 UINTN DeltaCount;
1007
1008 LengthRight = 0;
1009 LengthLeft = 0;
1010 Limit = BaseAddress + Length;
1011 StartIndex = *Count;
1012 EndIndex = *Count;
1013 for (Index = 0; Index < *Count; Index++) {
1014 if ((StartIndex == *Count) &&
1015 (Ranges[Index].BaseAddress <= BaseAddress) &&
1016 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) {
1017 StartIndex = Index;
1018 LengthLeft = BaseAddress - Ranges[Index].BaseAddress;
1019 }
1020
1021 if ((EndIndex == *Count) &&
1022 (Ranges[Index].BaseAddress < Limit) &&
1023 (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) {
1024 EndIndex = Index;
1025 LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit;
1026 break;
1027 }
1028 }
1029
1030 ASSERT (StartIndex != *Count && EndIndex != *Count);
1031 if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) {
1032 return RETURN_ALREADY_STARTED;
1033 }
1034
1035 //
1036 // The type change may cause merging with previous range or next range.
1037 // Update the StartIndex, EndIndex, BaseAddress, Length so that following
1038 // logic doesn't need to consider merging.
1039 //
1040 if (StartIndex != 0) {
1041 if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) {
1042 StartIndex--;
1043 Length += Ranges[StartIndex].Length;
1044 BaseAddress -= Ranges[StartIndex].Length;
1045 }
1046 }
1047 if (EndIndex != (*Count) - 1) {
1048 if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) {
1049 EndIndex++;
1050 Length += Ranges[EndIndex].Length;
1051 }
1052 }
1053
1054 //
1055 // |- 0 -|- 1 -|- 2 -|- 3 -| StartIndex EndIndex DeltaCount Count (Count = 4)
1056 // |++++++++++++++++++| 0 3 1=3-0-2 3
1057 // |+++++++| 0 1 -1=1-0-2 5
1058 // |+| 0 0 -2=0-0-2 6
1059 // |+++| 0 0 -1=0-0-2+1 5
1060 //
1061 //
1062 DeltaCount = EndIndex - StartIndex - 2;
1063 if (LengthLeft == 0) {
1064 DeltaCount++;
1065 }
1066 if (LengthRight == 0) {
1067 DeltaCount++;
1068 }
1069 if (*Count - DeltaCount > Capacity) {
1070 return RETURN_OUT_OF_RESOURCES;
1071 }
1072
1073 //
1074 // Reserve (-DeltaCount) space
1075 //
1076 CopyMem (&Ranges[EndIndex + 1 - DeltaCount], &Ranges[EndIndex + 1], (*Count - EndIndex - 1) * sizeof (Ranges[0]));
1077 *Count -= DeltaCount;
1078
1079 if (LengthLeft != 0) {
1080 Ranges[StartIndex].Length = LengthLeft;
1081 StartIndex++;
1082 }
1083 if (LengthRight != 0) {
1084 Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length;
1085 Ranges[EndIndex - DeltaCount].Length = LengthRight;
1086 Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;
1087 }
1088 Ranges[StartIndex].BaseAddress = BaseAddress;
1089 Ranges[StartIndex].Length = Length;
1090 Ranges[StartIndex].Type = Type;
1091 return RETURN_SUCCESS;
1092 }
1093
1094 /**
1095 Return the number of memory types in range [BaseAddress, BaseAddress + Length).
1096
1097 @param Ranges Array holding memory type settings for all memory regions.
1098 @param RangeCount The count of memory ranges the array holds.
1099 @param BaseAddress Base address.
1100 @param Length Length.
1101 @param Types Return bit mask to indicate all memory types in the specified range.
1102
1103 @retval Number of memory types.
1104 **/
1105 UINT8
1106 MtrrLibGetNumberOfTypes (
1107 IN CONST MTRR_MEMORY_RANGE *Ranges,
1108 IN UINTN RangeCount,
1109 IN UINT64 BaseAddress,
1110 IN UINT64 Length,
1111 IN OUT UINT8 *Types OPTIONAL
1112 )
1113 {
1114 UINTN Index;
1115 UINT8 TypeCount;
1116 UINT8 LocalTypes;
1117
1118 TypeCount = 0;
1119 LocalTypes = 0;
1120 for (Index = 0; Index < RangeCount; Index++) {
1121 if ((Ranges[Index].BaseAddress <= BaseAddress) &&
1122 (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)
1123 ) {
1124 if ((LocalTypes & (1 << Ranges[Index].Type)) == 0) {
1125 LocalTypes |= (UINT8)(1 << Ranges[Index].Type);
1126 TypeCount++;
1127 }
1128
1129 if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {
1130 Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;
1131 BaseAddress = Ranges[Index].BaseAddress + Ranges[Index].Length;
1132 } else {
1133 break;
1134 }
1135 }
1136 }
1137
1138 if (Types != NULL) {
1139 *Types = LocalTypes;
1140 }
1141 return TypeCount;
1142 }
1143
1144 /**
1145 Calculate the least MTRR number from vector Start to Stop and update
1146 the Previous of all vectors from Start to Stop is updated to reflect
1147 how the memory range is covered by MTRR.
1148
1149 @param VectorCount The count of vectors in the graph.
1150 @param Vector Array holding all vectors.
1151 @param Weight 2-dimention array holding weights between vectors.
1152 @param Start Start vector.
1153 @param Stop Stop vector.
1154 @param IncludeOptional TRUE to count the optional weight.
1155 **/
1156 VOID
1157 MtrrLibCalculateLeastMtrrs (
1158 IN UINT16 VectorCount,
1159 IN MTRR_LIB_ADDRESS *Vector,
1160 IN OUT CONST UINT8 *Weight,
1161 IN UINT16 Start,
1162 IN UINT16 Stop,
1163 IN BOOLEAN IncludeOptional
1164 )
1165 {
1166 UINT16 Index;
1167 UINT8 MinWeight;
1168 UINT16 MinI;
1169 UINT8 Mandatory;
1170 UINT8 Optional;
1171
1172 for (Index = Start; Index <= Stop; Index++) {
1173 Vector[Index].Visited = FALSE;
1174 Vector[Index].Previous = VectorCount;
1175 Mandatory = Weight[M(Start,Index)];
1176 Vector[Index].Weight = Mandatory;
1177 if (Mandatory != MAX_WEIGHT) {
1178 Optional = IncludeOptional ? Weight[O(Start, Index)] : 0;
1179 Vector[Index].Weight += Optional;
1180 ASSERT (Vector[Index].Weight >= Optional);
1181 }
1182 }
1183
1184 MinI = Start;
1185 MinWeight = 0;
1186 while (!Vector[Stop].Visited) {
1187 //
1188 // Update the weight from the shortest vector to other unvisited vectors
1189 //
1190 for (Index = Start + 1; Index <= Stop; Index++) {
1191 if (!Vector[Index].Visited) {
1192 Mandatory = Weight[M(MinI, Index)];
1193 if (Mandatory != MAX_WEIGHT) {
1194 Optional = IncludeOptional ? Weight[O(MinI, Index)] : 0;
1195 if (MinWeight + Mandatory + Optional <= Vector[Index].Weight) {
1196 Vector[Index].Weight = MinWeight + Mandatory + Optional;
1197 Vector[Index].Previous = MinI; // Previous is Start based.
1198 }
1199 }
1200 }
1201 }
1202
1203 //
1204 // Find the shortest vector from Start
1205 //
1206 MinI = VectorCount;
1207 MinWeight = MAX_WEIGHT;
1208 for (Index = Start + 1; Index <= Stop; Index++) {
1209 if (!Vector[Index].Visited && MinWeight > Vector[Index].Weight) {
1210 MinI = Index;
1211 MinWeight = Vector[Index].Weight;
1212 }
1213 }
1214
1215 //
1216 // Mark the shortest vector from Start as visited
1217 //
1218 Vector[MinI].Visited = TRUE;
1219 }
1220 }
1221
1222 /**
1223 Append the MTRR setting to MTRR setting array.
1224
1225 @param Mtrrs Array holding all MTRR settings.
1226 @param MtrrCapacity Capacity of the MTRR array.
1227 @param MtrrCount The count of MTRR settings in array.
1228 @param BaseAddress Base address.
1229 @param Length Length.
1230 @param Type Memory type.
1231
1232 @retval RETURN_SUCCESS MTRR setting is appended to array.
1233 @retval RETURN_OUT_OF_RESOURCES Array is full.
1234 **/
1235 RETURN_STATUS
1236 MtrrLibAppendVariableMtrr (
1237 IN OUT MTRR_MEMORY_RANGE *Mtrrs,
1238 IN UINT32 MtrrCapacity,
1239 IN OUT UINT32 *MtrrCount,
1240 IN UINT64 BaseAddress,
1241 IN UINT64 Length,
1242 IN MTRR_MEMORY_CACHE_TYPE Type
1243 )
1244 {
1245 if (*MtrrCount == MtrrCapacity) {
1246 return RETURN_OUT_OF_RESOURCES;
1247 }
1248
1249 Mtrrs[*MtrrCount].BaseAddress = BaseAddress;
1250 Mtrrs[*MtrrCount].Length = Length;
1251 Mtrrs[*MtrrCount].Type = Type;
1252 (*MtrrCount)++;
1253 return RETURN_SUCCESS;
1254 }
1255
1256 /**
1257 Return the memory type that has the least precedence.
1258
1259 @param TypeBits Bit mask of memory type.
1260
1261 @retval Memory type that has the least precedence.
1262 **/
1263 MTRR_MEMORY_CACHE_TYPE
1264 MtrrLibLowestType (
1265 IN UINT8 TypeBits
1266 )
1267 {
1268 INT8 Type;
1269
1270 ASSERT (TypeBits != 0);
1271 for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1);
1272 return (MTRR_MEMORY_CACHE_TYPE)Type;
1273 }
1274
1275 /**
1276 Return TRUE when the Operand is exactly power of 2.
1277
1278 @retval TRUE Operand is exactly power of 2.
1279 @retval FALSE Operand is not power of 2.
1280 **/
1281 BOOLEAN
1282 MtrrLibIsPowerOfTwo (
1283 IN UINT64 Operand
1284 )
1285 {
1286 ASSERT (Operand != 0);
1287 return (BOOLEAN) ((Operand & (Operand - 1)) == 0);
1288 }
1289
1290 /**
1291 Calculate the subtractive path from vector Start to Stop.
1292
1293 @param DefaultType Default memory type.
1294 @param A0 Alignment to use when base address is 0.
1295 @param Ranges Array holding memory type settings for all memory regions.
1296 @param RangeCount The count of memory ranges the array holds.
1297 @param VectorCount The count of vectors in the graph.
1298 @param Vector Array holding all vectors.
1299 @param Weight 2-dimention array holding weights between vectors.
1300 @param Start Start vector.
1301 @param Stop Stop vector.
1302 @param Types Type bit mask of memory range from Start to Stop.
1303 @param TypeCount Number of different memory types from Start to Stop.
1304 @param Mtrrs Array holding all MTRR settings.
1305 @param MtrrCapacity Capacity of the MTRR array.
1306 @param MtrrCount The count of MTRR settings in array.
1307
1308 @retval RETURN_SUCCESS The subtractive path is calculated successfully.
1309 @retval RETURN_OUT_OF_RESOURCES The MTRR setting array is full.
1310
1311 **/
1312 RETURN_STATUS
1313 MtrrLibCalculateSubtractivePath (
1314 IN MTRR_MEMORY_CACHE_TYPE DefaultType,
1315 IN UINT64 A0,
1316 IN CONST MTRR_MEMORY_RANGE *Ranges,
1317 IN UINTN RangeCount,
1318 IN UINT16 VectorCount,
1319 IN MTRR_LIB_ADDRESS *Vector,
1320 IN OUT UINT8 *Weight,
1321 IN UINT16 Start,
1322 IN UINT16 Stop,
1323 IN UINT8 Types,
1324 IN UINT8 TypeCount,
1325 IN OUT MTRR_MEMORY_RANGE *Mtrrs, OPTIONAL
1326 IN UINT32 MtrrCapacity, OPTIONAL
1327 IN OUT UINT32 *MtrrCount OPTIONAL
1328 )
1329 {
1330 RETURN_STATUS Status;
1331 UINT64 Base;
1332 UINT64 Length;
1333 UINT8 PrecedentTypes;
1334 UINTN Index;
1335 UINT64 HBase;
1336 UINT64 HLength;
1337 UINT64 SubLength;
1338 UINT16 SubStart;
1339 UINT16 SubStop;
1340 UINT16 Cur;
1341 UINT16 Pre;
1342 MTRR_MEMORY_CACHE_TYPE LowestType;
1343 MTRR_MEMORY_CACHE_TYPE LowestPrecedentType;
1344
1345 Base = Vector[Start].Address;
1346 Length = Vector[Stop].Address - Base;
1347
1348 LowestType = MtrrLibLowestType (Types);
1349
1350 //
1351 // Clear the lowest type (highest bit) to get the precedent types
1352 //
1353 PrecedentTypes = ~(1 << LowestType) & Types;
1354 LowestPrecedentType = MtrrLibLowestType (PrecedentTypes);
1355
1356 if (Mtrrs == NULL) {
1357 Weight[M(Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);
1358 Weight[O(Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);
1359 }
1360
1361 // Add all high level ranges
1362 HBase = MAX_UINT64;
1363 HLength = 0;
1364 for (Index = 0; Index < RangeCount; Index++) {
1365 if (Length == 0) {
1366 break;
1367 }
1368 if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress + Ranges[Index].Length <= Base)) {
1369 continue;
1370 }
1371
1372 //
1373 // Base is in the Range[Index]
1374 //
1375 if (Base + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {
1376 SubLength = Ranges[Index].BaseAddress + Ranges[Index].Length - Base;
1377 } else {
1378 SubLength = Length;
1379 }
1380 if (((1 << Ranges[Index].Type) & PrecedentTypes) != 0) {
1381 //
1382 // Meet a range whose types take precedence.
1383 // Update the [HBase, HBase + HLength) to include the range,
1384 // [HBase, HBase + HLength) may contain sub ranges with 2 different types, and both take precedence.
1385 //
1386 if (HBase == MAX_UINT64) {
1387 HBase = Base;
1388 }
1389 HLength += SubLength;
1390 }
1391
1392 Base += SubLength;
1393 Length -= SubLength;
1394
1395 if (HLength == 0) {
1396 continue;
1397 }
1398
1399 if ((Ranges[Index].Type == LowestType) || (Length == 0)) { // meet low type or end
1400
1401 //
1402 // Add the MTRRs for each high priority type range
1403 // the range[HBase, HBase + HLength) contains only two types.
1404 // We might use positive or subtractive, depending on which way uses less MTRR
1405 //
1406 for (SubStart = Start; SubStart <= Stop; SubStart++) {
1407 if (Vector[SubStart].Address == HBase) {
1408 break;
1409 }
1410 }
1411
1412 for (SubStop = SubStart; SubStop <= Stop; SubStop++) {
1413 if (Vector[SubStop].Address == HBase + HLength) {
1414 break;
1415 }
1416 }
1417 ASSERT (Vector[SubStart].Address == HBase);
1418 ASSERT (Vector[SubStop].Address == HBase + HLength);
1419
1420 if ((TypeCount == 2) || (SubStart == SubStop - 1)) {
1421 //
1422 // add subtractive MTRRs for [HBase, HBase + HLength)
1423 // [HBase, HBase + HLength) contains only one type.
1424 // while - loop is to split the range to MTRR - compliant aligned range.
1425 //
1426 if (Mtrrs == NULL) {
1427 Weight[M (Start, Stop)] += (UINT8)(SubStop - SubStart);
1428 } else {
1429 while (SubStart != SubStop) {
1430 Status = MtrrLibAppendVariableMtrr (
1431 Mtrrs, MtrrCapacity, MtrrCount,
1432 Vector[SubStart].Address, Vector[SubStart].Length, (MTRR_MEMORY_CACHE_TYPE) Vector[SubStart].Type
1433 );
1434 if (RETURN_ERROR (Status)) {
1435 return Status;
1436 }
1437 SubStart++;
1438 }
1439 }
1440 } else {
1441 ASSERT (TypeCount == 3);
1442 MtrrLibCalculateLeastMtrrs (VectorCount, Vector, Weight, SubStart, SubStop, TRUE);
1443
1444 if (Mtrrs == NULL) {
1445 Weight[M (Start, Stop)] += Vector[SubStop].Weight;
1446 } else {
1447 // When we need to collect the optimal path from SubStart to SubStop
1448 while (SubStop != SubStart) {
1449 Cur = SubStop;
1450 Pre = Vector[Cur].Previous;
1451 SubStop = Pre;
1452
1453 if (Weight[M (Pre, Cur)] != 0) {
1454 Status = MtrrLibAppendVariableMtrr (
1455 Mtrrs, MtrrCapacity, MtrrCount,
1456 Vector[Pre].Address, Vector[Cur].Address - Vector[Pre].Address, LowestPrecedentType
1457 );
1458 if (RETURN_ERROR (Status)) {
1459 return Status;
1460 }
1461 }
1462 if (Pre != Cur - 1) {
1463 Status = MtrrLibCalculateSubtractivePath (
1464 DefaultType, A0,
1465 Ranges, RangeCount,
1466 VectorCount, Vector, Weight,
1467 Pre, Cur, PrecedentTypes, 2,
1468 Mtrrs, MtrrCapacity, MtrrCount
1469 );
1470 if (RETURN_ERROR (Status)) {
1471 return Status;
1472 }
1473 }
1474 }
1475 }
1476
1477 }
1478 //
1479 // Reset HBase, HLength
1480 //
1481 HBase = MAX_UINT64;
1482 HLength = 0;
1483 }
1484 }
1485 return RETURN_SUCCESS;
1486 }
1487
1488 /**
1489 Calculate MTRR settings to cover the specified memory ranges.
1490
1491 @param DefaultType Default memory type.
1492 @param A0 Alignment to use when base address is 0.
1493 @param Ranges Memory range array holding the memory type
1494 settings for all memory address.
1495 @param RangeCount Count of memory ranges.
1496 @param Scratch A temporary scratch buffer that is used to perform the calculation.
1497 This is an optional parameter that may be NULL.
1498 @param ScratchSize Pointer to the size in bytes of the scratch buffer.
1499 It may be updated to the actual required size when the calculation
1500 needs more scratch buffer.
1501 @param Mtrrs Array holding all MTRR settings.
1502 @param MtrrCapacity Capacity of the MTRR array.
1503 @param MtrrCount The count of MTRR settings in array.
1504
1505 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.
1506 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.
1507 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.
1508 **/
1509 RETURN_STATUS
1510 MtrrLibCalculateMtrrs (
1511 IN MTRR_MEMORY_CACHE_TYPE DefaultType,
1512 IN UINT64 A0,
1513 IN CONST MTRR_MEMORY_RANGE *Ranges,
1514 IN UINTN RangeCount,
1515 IN VOID *Scratch,
1516 IN OUT UINTN *ScratchSize,
1517 IN OUT MTRR_MEMORY_RANGE *Mtrrs,
1518 IN UINT32 MtrrCapacity,
1519 IN OUT UINT32 *MtrrCount
1520 )
1521 {
1522 UINT64 Base0;
1523 UINT64 Base1;
1524 UINTN Index;
1525 UINT64 Base;
1526 UINT64 Length;
1527 UINT64 Alignment;
1528 UINT64 SubLength;
1529 MTRR_LIB_ADDRESS *Vector;
1530 UINT8 *Weight;
1531 UINT32 VectorIndex;
1532 UINT32 VectorCount;
1533 UINTN RequiredScratchSize;
1534 UINT8 TypeCount;
1535 UINT16 Start;
1536 UINT16 Stop;
1537 UINT8 Type;
1538 RETURN_STATUS Status;
1539
1540 Base0 = Ranges[0].BaseAddress;
1541 Base1 = Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length;
1542 MTRR_LIB_ASSERT_ALIGNED (Base0, Base1 - Base0);
1543
1544 //
1545 // Count the number of vectors.
1546 //
1547 Vector = (MTRR_LIB_ADDRESS*)Scratch;
1548 for (VectorIndex = 0, Index = 0; Index < RangeCount; Index++) {
1549 Base = Ranges[Index].BaseAddress;
1550 Length = Ranges[Index].Length;
1551 while (Length != 0) {
1552 Alignment = MtrrLibBiggestAlignment (Base, A0);
1553 SubLength = Alignment;
1554 if (SubLength > Length) {
1555 SubLength = GetPowerOfTwo64 (Length);
1556 }
1557 if (VectorIndex < *ScratchSize / sizeof (*Vector)) {
1558 Vector[VectorIndex].Address = Base;
1559 Vector[VectorIndex].Alignment = Alignment;
1560 Vector[VectorIndex].Type = Ranges[Index].Type;
1561 Vector[VectorIndex].Length = SubLength;
1562 }
1563 Base += SubLength;
1564 Length -= SubLength;
1565 VectorIndex++;
1566 }
1567 }
1568 //
1569 // Vector[VectorIndex] = Base1, so whole vector count is (VectorIndex + 1).
1570 //
1571 VectorCount = VectorIndex + 1;
1572 DEBUG ((
1573 DEBUG_CACHE, " VectorCount (%016lx - %016lx) = %d\n",
1574 Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, VectorCount
1575 ));
1576 ASSERT (VectorCount < MAX_UINT16);
1577
1578 RequiredScratchSize = VectorCount * sizeof (*Vector) + VectorCount * VectorCount * sizeof (*Weight);
1579 if (*ScratchSize < RequiredScratchSize) {
1580 *ScratchSize = RequiredScratchSize;
1581 return RETURN_BUFFER_TOO_SMALL;
1582 }
1583 Vector[VectorCount - 1].Address = Base1;
1584
1585 Weight = (UINT8 *) &Vector[VectorCount];
1586 //
1587 // Set mandatory weight between any vector to max
1588 // Set optional weight and between any vector and self->self to 0
1589 // E.g.:
1590 // 00 FF FF FF
1591 // 00 00 FF FF
1592 // 00 00 00 FF
1593 // 00 00 00 00
1594 //
1595 for (VectorIndex = 0; VectorIndex < VectorCount; VectorIndex++) {
1596 SetMem (&Weight[M(VectorIndex, 0)], VectorIndex + 1, 0);
1597 if (VectorIndex != VectorCount - 1) {
1598 Weight[M (VectorIndex, VectorIndex + 1)] = (DefaultType == Vector[VectorIndex].Type) ? 0 : 1;
1599 SetMem (&Weight[M (VectorIndex, VectorIndex + 2)], VectorCount - VectorIndex - 2, MAX_WEIGHT);
1600 }
1601 }
1602
1603 for (TypeCount = 2; TypeCount <= 3; TypeCount++) {
1604 for (Start = 0; Start < VectorCount; Start++) {
1605 for (Stop = Start + 2; Stop < VectorCount; Stop++) {
1606 ASSERT (Vector[Stop].Address > Vector[Start].Address);
1607 Length = Vector[Stop].Address - Vector[Start].Address;
1608 if (Length > Vector[Start].Alignment) {
1609 //
1610 // Pickup a new Start when [Start, Stop) cannot be described by one MTRR.
1611 //
1612 break;
1613 }
1614 if ((Weight[M(Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {
1615 if (MtrrLibGetNumberOfTypes (
1616 Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, &Type
1617 ) == TypeCount) {
1618 //
1619 // Update the Weight[Start, Stop] using subtractive path.
1620 //
1621 MtrrLibCalculateSubtractivePath (
1622 DefaultType, A0,
1623 Ranges, RangeCount,
1624 (UINT16)VectorCount, Vector, Weight,
1625 Start, Stop, Type, TypeCount,
1626 NULL, 0, NULL
1627 );
1628 } else if (TypeCount == 2) {
1629 //
1630 // Pick up a new Start when we expect 2-type range, but 3-type range is met.
1631 // Because no matter how Stop is increased, we always meet 3-type range.
1632 //
1633 break;
1634 }
1635 }
1636 }
1637 }
1638 }
1639
1640 Status = RETURN_SUCCESS;
1641 MtrrLibCalculateLeastMtrrs ((UINT16) VectorCount, Vector, Weight, 0, (UINT16) VectorCount - 1, FALSE);
1642 Stop = (UINT16) VectorCount - 1;
1643 while (Stop != 0) {
1644 Start = Vector[Stop].Previous;
1645 TypeCount = MAX_UINT8;
1646 Type = 0;
1647 if (Weight[M(Start, Stop)] != 0) {
1648 TypeCount = MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, &Type);
1649 Status = MtrrLibAppendVariableMtrr (
1650 Mtrrs, MtrrCapacity, MtrrCount,
1651 Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address,
1652 MtrrLibLowestType (Type)
1653 );
1654 if (RETURN_ERROR (Status)) {
1655 break;
1656 }
1657 }
1658
1659 if (Start != Stop - 1) {
1660 //
1661 // substractive path
1662 //
1663 if (TypeCount == MAX_UINT8) {
1664 TypeCount = MtrrLibGetNumberOfTypes (
1665 Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Address - Vector[Start].Address, &Type
1666 );
1667 }
1668 Status = MtrrLibCalculateSubtractivePath (
1669 DefaultType, A0,
1670 Ranges, RangeCount,
1671 (UINT16) VectorCount, Vector, Weight, Start, Stop,
1672 Type, TypeCount,
1673 Mtrrs, MtrrCapacity, MtrrCount
1674 );
1675 if (RETURN_ERROR (Status)) {
1676 break;
1677 }
1678 }
1679 Stop = Start;
1680 }
1681 return Status;
1682 }
1683
1684
1685 /**
1686 Apply the fixed MTRR settings to memory range array.
1687
1688 @param Fixed The fixed MTRR settings.
1689 @param Ranges Return the memory range array holding memory type
1690 settings for all memory address.
1691 @param RangeCapacity The capacity of memory range array.
1692 @param RangeCount Return the count of memory range.
1693
1694 @retval RETURN_SUCCESS The memory range array is returned successfully.
1695 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.
1696 **/
1697 RETURN_STATUS
1698 MtrrLibApplyFixedMtrrs (
1699 IN MTRR_FIXED_SETTINGS *Fixed,
1700 IN OUT MTRR_MEMORY_RANGE *Ranges,
1701 IN UINTN RangeCapacity,
1702 IN OUT UINTN *RangeCount
1703 )
1704 {
1705 RETURN_STATUS Status;
1706 UINTN MsrIndex;
1707 UINTN Index;
1708 MTRR_MEMORY_CACHE_TYPE MemoryType;
1709 UINT64 Base;
1710
1711 Base = 0;
1712 for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {
1713 ASSERT (Base == mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress);
1714 for (Index = 0; Index < sizeof (UINT64); Index++) {
1715 MemoryType = (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIndex]))[Index];
1716 Status = MtrrLibSetMemoryType (
1717 Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtrrTable[MsrIndex].Length, MemoryType
1718 );
1719 if (Status == RETURN_OUT_OF_RESOURCES) {
1720 return Status;
1721 }
1722 Base += mMtrrLibFixedMtrrTable[MsrIndex].Length;
1723 }
1724 }
1725 ASSERT (Base == BASE_1MB);
1726 return RETURN_SUCCESS;
1727 }
1728
1729 /**
1730 Apply the variable MTRR settings to memory range array.
1731
1732 @param VariableMtrr The variable MTRR array.
1733 @param VariableMtrrCount The count of variable MTRRs.
1734 @param Ranges Return the memory range array with new MTRR settings applied.
1735 @param RangeCapacity The capacity of memory range array.
1736 @param RangeCount Return the count of memory range.
1737
1738 @retval RETURN_SUCCESS The memory range array is returned successfully.
1739 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.
1740 **/
1741 RETURN_STATUS
1742 MtrrLibApplyVariableMtrrs (
1743 IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
1744 IN UINT32 VariableMtrrCount,
1745 IN OUT MTRR_MEMORY_RANGE *Ranges,
1746 IN UINTN RangeCapacity,
1747 IN OUT UINTN *RangeCount
1748 )
1749 {
1750 RETURN_STATUS Status;
1751 UINTN Index;
1752
1753 //
1754 // WT > WB
1755 // UC > *
1756 // UC > * (except WB, UC) > WB
1757 //
1758
1759 //
1760 // 1. Set WB
1761 //
1762 for (Index = 0; Index < VariableMtrrCount; Index++) {
1763 if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheWriteBack)) {
1764 Status = MtrrLibSetMemoryType (
1765 Ranges, RangeCapacity, RangeCount,
1766 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type
1767 );
1768 if (Status == RETURN_OUT_OF_RESOURCES) {
1769 return Status;
1770 }
1771 }
1772 }
1773
1774 //
1775 // 2. Set other types than WB or UC
1776 //
1777 for (Index = 0; Index < VariableMtrrCount; Index++) {
1778 if ((VariableMtrr[Index].Length != 0) &&
1779 (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) {
1780 Status = MtrrLibSetMemoryType (
1781 Ranges, RangeCapacity, RangeCount,
1782 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type
1783 );
1784 if (Status == RETURN_OUT_OF_RESOURCES) {
1785 return Status;
1786 }
1787 }
1788 }
1789
1790 //
1791 // 3. Set UC
1792 //
1793 for (Index = 0; Index < VariableMtrrCount; Index++) {
1794 if (VariableMtrr[Index].Length != 0 && VariableMtrr[Index].Type == CacheUncacheable) {
1795 Status = MtrrLibSetMemoryType (
1796 Ranges, RangeCapacity, RangeCount,
1797 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type
1798 );
1799 if (Status == RETURN_OUT_OF_RESOURCES) {
1800 return Status;
1801 }
1802 }
1803 }
1804 return RETURN_SUCCESS;
1805 }
1806
1807 /**
1808 Return the memory type bit mask that's compatible to first type in the Ranges.
1809
1810 @param Ranges Memory range array holding the memory type
1811 settings for all memory address.
1812 @param RangeCount Count of memory ranges.
1813
1814 @return Compatible memory type bit mask.
1815 **/
1816 UINT8
1817 MtrrLibGetCompatibleTypes (
1818 IN CONST MTRR_MEMORY_RANGE *Ranges,
1819 IN UINTN RangeCount
1820 )
1821 {
1822 ASSERT (RangeCount != 0);
1823
1824 switch (Ranges[0].Type) {
1825 case CacheWriteBack:
1826 case CacheWriteThrough:
1827 return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);
1828 break;
1829
1830 case CacheWriteCombining:
1831 case CacheWriteProtected:
1832 return (1 << Ranges[0].Type) | (1 << CacheUncacheable);
1833 break;
1834
1835 case CacheUncacheable:
1836 if (RangeCount == 1) {
1837 return (1 << CacheUncacheable);
1838 }
1839 return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);
1840 break;
1841
1842 case CacheInvalid:
1843 default:
1844 ASSERT (FALSE);
1845 break;
1846 }
1847 return 0;
1848 }
1849
1850 /**
1851 Overwrite the destination MTRR settings with the source MTRR settings.
1852 This routine is to make sure the modification to destination MTRR settings
1853 is as small as possible.
1854
1855 @param DstMtrrs Destination MTRR settings.
1856 @param DstMtrrCount Count of destination MTRR settings.
1857 @param SrcMtrrs Source MTRR settings.
1858 @param SrcMtrrCount Count of source MTRR settings.
1859 @param Modified Flag array to indicate which destination MTRR setting is modified.
1860 **/
1861 VOID
1862 MtrrLibMergeVariableMtrr (
1863 MTRR_MEMORY_RANGE *DstMtrrs,
1864 UINT32 DstMtrrCount,
1865 MTRR_MEMORY_RANGE *SrcMtrrs,
1866 UINT32 SrcMtrrCount,
1867 BOOLEAN *Modified
1868 )
1869 {
1870 UINT32 DstIndex;
1871 UINT32 SrcIndex;
1872
1873 ASSERT (SrcMtrrCount <= DstMtrrCount);
1874
1875 for (DstIndex = 0; DstIndex < DstMtrrCount; DstIndex++) {
1876 Modified[DstIndex] = FALSE;
1877
1878 if (DstMtrrs[DstIndex].Length == 0) {
1879 continue;
1880 }
1881 for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {
1882 if (DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress &&
1883 DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length &&
1884 DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type) {
1885 break;
1886 }
1887 }
1888
1889 if (SrcIndex == SrcMtrrCount) {
1890 //
1891 // Remove the one from DstMtrrs which is not in SrcMtrrs
1892 //
1893 DstMtrrs[DstIndex].Length = 0;
1894 Modified[DstIndex] = TRUE;
1895 } else {
1896 //
1897 // Remove the one from SrcMtrrs which is also in DstMtrrs
1898 //
1899 SrcMtrrs[SrcIndex].Length = 0;
1900 }
1901 }
1902
1903 //
1904 // Now valid MTRR only exists in either DstMtrrs or SrcMtrrs.
1905 // Merge MTRRs from SrcMtrrs to DstMtrrs
1906 //
1907 DstIndex = 0;
1908 for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {
1909 if (SrcMtrrs[SrcIndex].Length != 0) {
1910
1911 //
1912 // Find the empty slot in DstMtrrs
1913 //
1914 while (DstIndex < DstMtrrCount) {
1915 if (DstMtrrs[DstIndex].Length == 0) {
1916 break;
1917 }
1918 DstIndex++;
1919 }
1920 ASSERT (DstIndex < DstMtrrCount);
1921 CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[0]));
1922 Modified[DstIndex] = TRUE;
1923 }
1924 }
1925 }
1926
1927 /**
1928 Calculate the variable MTRR settings for all memory ranges.
1929
1930 @param DefaultType Default memory type.
1931 @param A0 Alignment to use when base address is 0.
1932 @param Ranges Memory range array holding the memory type
1933 settings for all memory address.
1934 @param RangeCount Count of memory ranges.
1935 @param Scratch Scratch buffer to be used in MTRR calculation.
1936 @param ScratchSize Pointer to the size of scratch buffer.
1937 @param VariableMtrr Array holding all MTRR settings.
1938 @param VariableMtrrCapacity Capacity of the MTRR array.
1939 @param VariableMtrrCount The count of MTRR settings in array.
1940
1941 @retval RETURN_SUCCESS Variable MTRRs are allocated successfully.
1942 @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity.
1943 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.
1944 The required scratch buffer size is returned through ScratchSize.
1945 **/
1946 RETURN_STATUS
1947 MtrrLibSetMemoryRanges (
1948 IN MTRR_MEMORY_CACHE_TYPE DefaultType,
1949 IN UINT64 A0,
1950 IN MTRR_MEMORY_RANGE *Ranges,
1951 IN UINTN RangeCount,
1952 IN VOID *Scratch,
1953 IN OUT UINTN *ScratchSize,
1954 OUT MTRR_MEMORY_RANGE *VariableMtrr,
1955 IN UINT32 VariableMtrrCapacity,
1956 OUT UINT32 *VariableMtrrCount
1957 )
1958 {
1959 RETURN_STATUS Status;
1960 UINT32 Index;
1961 UINT64 Base0;
1962 UINT64 Base1;
1963 UINT64 Alignment;
1964 UINT8 CompatibleTypes;
1965 UINT64 Length;
1966 UINT32 End;
1967 UINTN ActualScratchSize;
1968 UINTN BiggestScratchSize;
1969
1970 *VariableMtrrCount = 0;
1971
1972 //
1973 // Since the whole ranges need multiple calls of MtrrLibCalculateMtrrs().
1974 // Each call needs different scratch buffer size.
1975 // When the provided scratch buffer size is not sufficient in any call,
1976 // set the GetActualScratchSize to TRUE, and following calls will only
1977 // calculate the actual scratch size for the caller.
1978 //
1979 BiggestScratchSize = 0;
1980
1981 for (Index = 0; Index < RangeCount;) {
1982 Base0 = Ranges[Index].BaseAddress;
1983
1984 //
1985 // Full step is optimal
1986 //
1987 while (Index < RangeCount) {
1988 ASSERT (Ranges[Index].BaseAddress == Base0);
1989 Alignment = MtrrLibBiggestAlignment (Base0, A0);
1990 while (Base0 + Alignment <= Ranges[Index].BaseAddress + Ranges[Index].Length) {
1991 if ((BiggestScratchSize <= *ScratchSize) && (Ranges[Index].Type != DefaultType)) {
1992 Status = MtrrLibAppendVariableMtrr (
1993 VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,
1994 Base0, Alignment, Ranges[Index].Type
1995 );
1996 if (RETURN_ERROR (Status)) {
1997 return Status;
1998 }
1999 }
2000 Base0 += Alignment;
2001 Alignment = MtrrLibBiggestAlignment (Base0, A0);
2002 }
2003
2004 //
2005 // Remove the above range from Ranges[Index]
2006 //
2007 Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress;
2008 Ranges[Index].BaseAddress = Base0;
2009 if (Ranges[Index].Length != 0) {
2010 break;
2011 } else {
2012 Index++;
2013 }
2014 }
2015
2016 if (Index == RangeCount) {
2017 break;
2018 }
2019
2020 //
2021 // Find continous ranges [Base0, Base1) which could be combined by MTRR.
2022 // Per SDM, the compatible types between[B0, B1) are:
2023 // UC, *
2024 // WB, WT
2025 // UC, WB, WT
2026 //
2027 CompatibleTypes = MtrrLibGetCompatibleTypes (&Ranges[Index], RangeCount - Index);
2028
2029 End = Index; // End points to last one that matches the CompatibleTypes.
2030 while (End + 1 < RangeCount) {
2031 if (((1 << Ranges[End + 1].Type) & CompatibleTypes) == 0) {
2032 break;
2033 }
2034 End++;
2035 }
2036 Alignment = MtrrLibBiggestAlignment (Base0, A0);
2037 Length = GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].Length - Base0);
2038 Base1 = Base0 + MIN (Alignment, Length);
2039
2040 //
2041 // Base1 may not in Ranges[End]. Update End to the range Base1 belongs to.
2042 //
2043 End = Index;
2044 while (End + 1 < RangeCount) {
2045 if (Base1 <= Ranges[End + 1].BaseAddress) {
2046 break;
2047 }
2048 End++;
2049 }
2050
2051 Length = Ranges[End].Length;
2052 Ranges[End].Length = Base1 - Ranges[End].BaseAddress;
2053 ActualScratchSize = *ScratchSize;
2054 Status = MtrrLibCalculateMtrrs (
2055 DefaultType, A0,
2056 &Ranges[Index], End + 1 - Index,
2057 Scratch, &ActualScratchSize,
2058 VariableMtrr, VariableMtrrCapacity, VariableMtrrCount
2059 );
2060 if (Status == RETURN_BUFFER_TOO_SMALL) {
2061 BiggestScratchSize = MAX (BiggestScratchSize, ActualScratchSize);
2062 //
2063 // Ignore this error, because we need to calculate the biggest
2064 // scratch buffer size.
2065 //
2066 Status = RETURN_SUCCESS;
2067 }
2068 if (RETURN_ERROR (Status)) {
2069 return Status;
2070 }
2071
2072 if (Length != Ranges[End].Length) {
2073 Ranges[End].BaseAddress = Base1;
2074 Ranges[End].Length = Length - Ranges[End].Length;
2075 Index = End;
2076 } else {
2077 Index = End + 1;
2078 }
2079 }
2080
2081 if (*ScratchSize < BiggestScratchSize) {
2082 *ScratchSize = BiggestScratchSize;
2083 return RETURN_BUFFER_TOO_SMALL;
2084 }
2085 return RETURN_SUCCESS;
2086 }
2087
2088 /**
2089 Set the below-1MB memory attribute to fixed MTRR buffer.
2090 Modified flag array indicates which fixed MTRR is modified.
2091
2092 @param [in, out] FixedSettings Fixed MTRR buffer.
2093 @param [out] Modified Flag array indicating which MTRR is modified.
2094 @param [in] BaseAddress Base address.
2095 @param [in] Length Length.
2096 @param [in] Type Memory type.
2097
2098 @retval RETURN_SUCCESS The memory attribute is set successfully.
2099 @retval RETURN_UNSUPPORTED The requested range or cache type was invalid
2100 for the fixed MTRRs.
2101 **/
2102 RETURN_STATUS
2103 MtrrLibSetBelow1MBMemoryAttribute (
2104 IN OUT MTRR_FIXED_SETTINGS *FixedSettings,
2105 OUT BOOLEAN *Modified,
2106 IN PHYSICAL_ADDRESS BaseAddress,
2107 IN UINT64 Length,
2108 IN MTRR_MEMORY_CACHE_TYPE Type
2109 )
2110 {
2111 RETURN_STATUS Status;
2112 UINT32 MsrIndex;
2113 UINT64 ClearMask;
2114 UINT64 OrMask;
2115 UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
2116 UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
2117 BOOLEAN LocalModified[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
2118
2119 ASSERT (BaseAddress < BASE_1MB);
2120
2121 SetMem (LocalModified, sizeof (LocalModified), FALSE);
2122
2123 //
2124 // (Value & ~0 | 0) still equals to (Value)
2125 //
2126 SetMem (ClearMasks, sizeof (ClearMasks), 0);
2127 SetMem (OrMasks, sizeof (OrMasks), 0);
2128
2129 MsrIndex = (UINT32)-1;
2130 while ((BaseAddress < BASE_1MB) && (Length != 0)) {
2131 Status = MtrrLibProgramFixedMtrr (Type, &BaseAddress, &Length, &MsrIndex, &ClearMask, &OrMask);
2132 if (RETURN_ERROR (Status)) {
2133 return Status;
2134 }
2135 ClearMasks[MsrIndex] = ClearMask;
2136 OrMasks[MsrIndex] = OrMask;
2137 Modified[MsrIndex] = TRUE;
2138 LocalModified[MsrIndex] = TRUE;
2139 }
2140
2141 for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {
2142 if (LocalModified[MsrIndex]) {
2143 FixedSettings->Mtrr[MsrIndex] = (FixedSettings->Mtrr[MsrIndex] & ~ClearMasks[MsrIndex]) | OrMasks[MsrIndex];
2144 }
2145 }
2146 return RETURN_SUCCESS;
2147 }
2148
2149 /**
2150 This function attempts to set the attributes into MTRR setting buffer for multiple memory ranges.
2151
2152 @param[in, out] MtrrSetting MTRR setting buffer to be set.
2153 @param[in] Scratch A temporary scratch buffer that is used to perform the calculation.
2154 @param[in, out] ScratchSize Pointer to the size in bytes of the scratch buffer.
2155 It may be updated to the actual required size when the calculation
2156 needs more scratch buffer.
2157 @param[in] Ranges Pointer to an array of MTRR_MEMORY_RANGE.
2158 When range overlap happens, the last one takes higher priority.
2159 When the function returns, either all the attributes are set successfully,
2160 or none of them is set.
2161 @param[in] RangeCount Count of MTRR_MEMORY_RANGE.
2162
2163 @retval RETURN_SUCCESS The attributes were set for all the memory ranges.
2164 @retval RETURN_INVALID_PARAMETER Length in any range is zero.
2165 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the
2166 memory resource range specified by BaseAddress and Length in any range.
2167 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource
2168 range specified by BaseAddress and Length in any range.
2169 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
2170 the memory resource ranges.
2171 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by
2172 BaseAddress and Length cannot be modified.
2173 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.
2174 **/
2175 RETURN_STATUS
2176 EFIAPI
2177 MtrrSetMemoryAttributesInMtrrSettings (
2178 IN OUT MTRR_SETTINGS *MtrrSetting,
2179 IN VOID *Scratch,
2180 IN OUT UINTN *ScratchSize,
2181 IN CONST MTRR_MEMORY_RANGE *Ranges,
2182 IN UINTN RangeCount
2183 )
2184 {
2185 RETURN_STATUS Status;
2186 UINT32 Index;
2187 UINT64 BaseAddress;
2188 UINT64 Length;
2189 BOOLEAN Above1MbExist;
2190
2191 UINT64 MtrrValidBitsMask;
2192 UINT64 MtrrValidAddressMask;
2193 MTRR_MEMORY_CACHE_TYPE DefaultType;
2194 MTRR_VARIABLE_SETTINGS VariableSettings;
2195 MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];
2196 UINTN WorkingRangeCount;
2197 BOOLEAN Modified;
2198 MTRR_VARIABLE_SETTING VariableSetting;
2199 UINT32 OriginalVariableMtrrCount;
2200 UINT32 FirmwareVariableMtrrCount;
2201 UINT32 WorkingVariableMtrrCount;
2202 MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
2203 MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
2204 BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
2205
2206 BOOLEAN FixedSettingsModified[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
2207 MTRR_FIXED_SETTINGS WorkingFixedSettings;
2208
2209 MTRR_CONTEXT MtrrContext;
2210 BOOLEAN MtrrContextValid;
2211
2212 Status = RETURN_SUCCESS;
2213 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
2214
2215 //
2216 // TRUE indicating the accordingly Variable setting needs modificaiton in OriginalVariableMtrr.
2217 //
2218 SetMem (VariableSettingModified, ARRAY_SIZE (VariableSettingModified), FALSE);
2219 //
2220 // TRUE indicating the accordingly Fixed setting needs modification in WorkingFixedSettings.
2221 //
2222 SetMem (FixedSettingsModified, ARRAY_SIZE (FixedSettingsModified), FALSE);
2223
2224 //
2225 // TRUE indicating the caller requests to set variable MTRRs.
2226 //
2227 Above1MbExist = FALSE;
2228 OriginalVariableMtrrCount = 0;
2229
2230 //
2231 // 0. Dump the requests.
2232 //
2233 DEBUG_CODE (
2234 DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",
2235 (MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize,
2236 (RangeCount <= 1) ? "," : "\n"
2237 ));
2238 for (Index = 0; Index < RangeCount; Index++) {
2239 DEBUG ((DEBUG_CACHE, " %a: [%016lx, %016lx)\n",
2240 mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)],
2241 Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length
2242 ));
2243 }
2244 );
2245
2246 //
2247 // 1. Validate the parameters.
2248 //
2249 if (!IsMtrrSupported ()) {
2250 Status = RETURN_UNSUPPORTED;
2251 goto Exit;
2252 }
2253
2254 for (Index = 0; Index < RangeCount; Index++) {
2255 if (Ranges[Index].Length == 0) {
2256 Status = RETURN_INVALID_PARAMETER;
2257 goto Exit;
2258 }
2259 if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) != 0) ||
2260 ((Ranges[Index].Length & ~MtrrValidAddressMask) != 0)
2261 ) {
2262 Status = RETURN_UNSUPPORTED;
2263 goto Exit;
2264 }
2265 if ((Ranges[Index].Type != CacheUncacheable) &&
2266 (Ranges[Index].Type != CacheWriteCombining) &&
2267 (Ranges[Index].Type != CacheWriteThrough) &&
2268 (Ranges[Index].Type != CacheWriteProtected) &&
2269 (Ranges[Index].Type != CacheWriteBack)) {
2270 Status = RETURN_INVALID_PARAMETER;
2271 goto Exit;
2272 }
2273 if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) {
2274 Above1MbExist = TRUE;
2275 }
2276 }
2277
2278 //
2279 // 2. Apply the above-1MB memory attribute settings.
2280 //
2281 if (Above1MbExist) {
2282 //
2283 // 2.1. Read all variable MTRRs and convert to Ranges.
2284 //
2285 OriginalVariableMtrrCount = GetVariableMtrrCountWorker ();
2286 MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &VariableSettings);
2287 MtrrLibGetRawVariableRanges (
2288 &VariableSettings, OriginalVariableMtrrCount,
2289 MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr
2290 );
2291
2292 DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);
2293 WorkingRangeCount = 1;
2294 WorkingRanges[0].BaseAddress = 0;
2295 WorkingRanges[0].Length = MtrrValidBitsMask + 1;
2296 WorkingRanges[0].Type = DefaultType;
2297
2298 Status = MtrrLibApplyVariableMtrrs (
2299 OriginalVariableMtrr, OriginalVariableMtrrCount,
2300 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount);
2301 ASSERT_RETURN_ERROR (Status);
2302
2303 ASSERT (OriginalVariableMtrrCount >= PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs));
2304 FirmwareVariableMtrrCount = OriginalVariableMtrrCount - PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);
2305 ASSERT (WorkingRangeCount <= 2 * FirmwareVariableMtrrCount + 1);
2306
2307 //
2308 // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction algorithm.
2309 //
2310 Status = MtrrLibSetMemoryType (
2311 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,
2312 0, SIZE_1MB, CacheUncacheable
2313 );
2314 ASSERT (Status != RETURN_OUT_OF_RESOURCES);
2315
2316 //
2317 // 2.3. Apply the new memory attribute settings to Ranges.
2318 //
2319 Modified = FALSE;
2320 for (Index = 0; Index < RangeCount; Index++) {
2321 BaseAddress = Ranges[Index].BaseAddress;
2322 Length = Ranges[Index].Length;
2323 if (BaseAddress < BASE_1MB) {
2324 if (Length <= BASE_1MB - BaseAddress) {
2325 continue;
2326 }
2327 Length -= BASE_1MB - BaseAddress;
2328 BaseAddress = BASE_1MB;
2329 }
2330 Status = MtrrLibSetMemoryType (
2331 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,
2332 BaseAddress, Length, Ranges[Index].Type
2333 );
2334 if (Status == RETURN_ALREADY_STARTED) {
2335 Status = RETURN_SUCCESS;
2336 } else if (Status == RETURN_OUT_OF_RESOURCES) {
2337 goto Exit;
2338 } else {
2339 ASSERT_RETURN_ERROR (Status);
2340 Modified = TRUE;
2341 }
2342 }
2343
2344 if (Modified) {
2345 //
2346 // 2.4. Calculate the Variable MTRR settings based on the Ranges.
2347 // Buffer Too Small may be returned if the scratch buffer size is insufficient.
2348 //
2349 Status = MtrrLibSetMemoryRanges (
2350 DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), WorkingRanges, WorkingRangeCount,
2351 Scratch, ScratchSize,
2352 WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount
2353 );
2354 if (RETURN_ERROR (Status)) {
2355 goto Exit;
2356 }
2357
2358 //
2359 // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with other range)
2360 //
2361 for (Index = 0; Index < WorkingVariableMtrrCount; Index++) {
2362 if (WorkingVariableMtrr[Index].BaseAddress == 0 && WorkingVariableMtrr[Index].Length == SIZE_1MB) {
2363 ASSERT (WorkingVariableMtrr[Index].Type == CacheUncacheable);
2364 WorkingVariableMtrrCount--;
2365 CopyMem (
2366 &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1],
2367 (WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMtrr[0])
2368 );
2369 break;
2370 }
2371 }
2372
2373 if (WorkingVariableMtrrCount > FirmwareVariableMtrrCount) {
2374 Status = RETURN_OUT_OF_RESOURCES;
2375 goto Exit;
2376 }
2377
2378 //
2379 // 2.6. Merge the WorkingVariableMtrr to OriginalVariableMtrr
2380 // Make sure least modification is made to OriginalVariableMtrr.
2381 //
2382 MtrrLibMergeVariableMtrr (
2383 OriginalVariableMtrr, OriginalVariableMtrrCount,
2384 WorkingVariableMtrr, WorkingVariableMtrrCount,
2385 VariableSettingModified
2386 );
2387 }
2388 }
2389
2390 //
2391 // 3. Apply the below-1MB memory attribute settings.
2392 //
2393 ZeroMem (WorkingFixedSettings.Mtrr, sizeof (WorkingFixedSettings.Mtrr));
2394 for (Index = 0; Index < RangeCount; Index++) {
2395 if (Ranges[Index].BaseAddress >= BASE_1MB) {
2396 continue;
2397 }
2398
2399 Status = MtrrLibSetBelow1MBMemoryAttribute (
2400 &WorkingFixedSettings, FixedSettingsModified,
2401 Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type
2402 );
2403 if (RETURN_ERROR (Status)) {
2404 goto Exit;
2405 }
2406 }
2407
2408 MtrrContextValid = FALSE;
2409 //
2410 // 4. Write fixed MTRRs that have been modified
2411 //
2412 for (Index = 0; Index < ARRAY_SIZE (FixedSettingsModified); Index++) {
2413 if (FixedSettingsModified[Index]) {
2414 if (MtrrSetting != NULL) {
2415 MtrrSetting->Fixed.Mtrr[Index] = WorkingFixedSettings.Mtrr[Index];
2416 } else {
2417 if (!MtrrContextValid) {
2418 MtrrLibPreMtrrChange (&MtrrContext);
2419 MtrrContextValid = TRUE;
2420 }
2421 AsmWriteMsr64 (
2422 mMtrrLibFixedMtrrTable[Index].Msr,
2423 WorkingFixedSettings.Mtrr[Index]
2424 );
2425 }
2426 }
2427 }
2428
2429 //
2430 // 5. Write variable MTRRs that have been modified
2431 //
2432 for (Index = 0; Index < OriginalVariableMtrrCount; Index++) {
2433 if (VariableSettingModified[Index]) {
2434 if (OriginalVariableMtrr[Index].Length != 0) {
2435 VariableSetting.Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask)
2436 | (UINT8)OriginalVariableMtrr[Index].Type;
2437 VariableSetting.Mask = ((~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask) | BIT11;
2438 } else {
2439 VariableSetting.Base = 0;
2440 VariableSetting.Mask = 0;
2441 }
2442 if (MtrrSetting != NULL) {
2443 CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, sizeof (VariableSetting));
2444 } else {
2445 if (!MtrrContextValid) {
2446 MtrrLibPreMtrrChange (&MtrrContext);
2447 MtrrContextValid = TRUE;
2448 }
2449 AsmWriteMsr64 (
2450 MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),
2451 VariableSetting.Base
2452 );
2453 AsmWriteMsr64 (
2454 MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),
2455 VariableSetting.Mask
2456 );
2457 }
2458 }
2459 }
2460
2461 if (MtrrSetting != NULL) {
2462 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1;
2463 ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.FE = 1;
2464 } else {
2465 if (MtrrContextValid) {
2466 MtrrLibPostMtrrChange (&MtrrContext);
2467 }
2468 }
2469
2470 Exit:
2471 DEBUG ((DEBUG_CACHE, " Result = %r\n", Status));
2472 if (!RETURN_ERROR (Status)) {
2473 MtrrDebugPrintAllMtrrsWorker (MtrrSetting);
2474 }
2475 return Status;
2476 }
2477
2478 /**
2479 This function attempts to set the attributes into MTRR setting buffer for a memory range.
2480
2481 @param[in, out] MtrrSetting MTRR setting buffer to be set.
2482 @param[in] BaseAddress The physical address that is the start address
2483 of a memory range.
2484 @param[in] Length The size in bytes of the memory range.
2485 @param[in] Attribute The bit mask of attributes to set for the
2486 memory range.
2487
2488 @retval RETURN_SUCCESS The attributes were set for the memory range.
2489 @retval RETURN_INVALID_PARAMETER Length is zero.
2490 @retval RETURN_UNSUPPORTED The processor does not support one or more bytes of the
2491 memory resource range specified by BaseAddress and Length.
2492 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support for the memory resource
2493 range specified by BaseAddress and Length.
2494 @retval RETURN_ACCESS_DENIED The attributes for the memory resource range specified by
2495 BaseAddress and Length cannot be modified.
2496 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
2497 the memory resource range.
2498 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.
2499 **/
2500 RETURN_STATUS
2501 EFIAPI
2502 MtrrSetMemoryAttributeInMtrrSettings (
2503 IN OUT MTRR_SETTINGS *MtrrSetting,
2504 IN PHYSICAL_ADDRESS BaseAddress,
2505 IN UINT64 Length,
2506 IN MTRR_MEMORY_CACHE_TYPE Attribute
2507 )
2508 {
2509 UINT8 Scratch[SCRATCH_BUFFER_SIZE];
2510 UINTN ScratchSize;
2511 MTRR_MEMORY_RANGE Range;
2512
2513 Range.BaseAddress = BaseAddress;
2514 Range.Length = Length;
2515 Range.Type = Attribute;
2516 ScratchSize = sizeof (Scratch);
2517 return MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, &ScratchSize, &Range, 1);
2518 }
2519
2520 /**
2521 This function attempts to set the attributes for a memory range.
2522
2523 @param[in] BaseAddress The physical address that is the start
2524 address of a memory range.
2525 @param[in] Length The size in bytes of the memory range.
2526 @param[in] Attributes The bit mask of attributes to set for the
2527 memory range.
2528
2529 @retval RETURN_SUCCESS The attributes were set for the memory
2530 range.
2531 @retval RETURN_INVALID_PARAMETER Length is zero.
2532 @retval RETURN_UNSUPPORTED The processor does not support one or
2533 more bytes of the memory resource range
2534 specified by BaseAddress and Length.
2535 @retval RETURN_UNSUPPORTED The bit mask of attributes is not support
2536 for the memory resource range specified
2537 by BaseAddress and Length.
2538 @retval RETURN_ACCESS_DENIED The attributes for the memory resource
2539 range specified by BaseAddress and Length
2540 cannot be modified.
2541 @retval RETURN_OUT_OF_RESOURCES There are not enough system resources to
2542 modify the attributes of the memory
2543 resource range.
2544 @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR calculation.
2545 **/
2546 RETURN_STATUS
2547 EFIAPI
2548 MtrrSetMemoryAttribute (
2549 IN PHYSICAL_ADDRESS BaseAddress,
2550 IN UINT64 Length,
2551 IN MTRR_MEMORY_CACHE_TYPE Attribute
2552 )
2553 {
2554 return MtrrSetMemoryAttributeInMtrrSettings (NULL, BaseAddress, Length, Attribute);
2555 }
2556
2557 /**
2558 Worker function setting variable MTRRs
2559
2560 @param[in] VariableSettings A buffer to hold variable MTRRs content.
2561
2562 **/
2563 VOID
2564 MtrrSetVariableMtrrWorker (
2565 IN MTRR_VARIABLE_SETTINGS *VariableSettings
2566 )
2567 {
2568 UINT32 Index;
2569 UINT32 VariableMtrrCount;
2570
2571 VariableMtrrCount = GetVariableMtrrCountWorker ();
2572 ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));
2573
2574 for (Index = 0; Index < VariableMtrrCount; Index++) {
2575 //
2576 // Mask MSR is always updated since caller might need to invalidate the MSR pair.
2577 // Base MSR is skipped when Mask.V is not set.
2578 //
2579 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSettings->Mtrr[Index].Mask);
2580 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
2581 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSettings->Mtrr[Index].Base);
2582 }
2583 }
2584 }
2585
2586
2587 /**
2588 This function sets variable MTRRs
2589
2590 @param[in] VariableSettings A buffer to hold variable MTRRs content.
2591
2592 @return The pointer of VariableSettings
2593
2594 **/
2595 MTRR_VARIABLE_SETTINGS*
2596 EFIAPI
2597 MtrrSetVariableMtrr (
2598 IN MTRR_VARIABLE_SETTINGS *VariableSettings
2599 )
2600 {
2601 MTRR_CONTEXT MtrrContext;
2602
2603 if (!IsMtrrSupported ()) {
2604 return VariableSettings;
2605 }
2606
2607 MtrrLibPreMtrrChange (&MtrrContext);
2608 MtrrSetVariableMtrrWorker (VariableSettings);
2609 MtrrLibPostMtrrChange (&MtrrContext);
2610 MtrrDebugPrintAllMtrrs ();
2611
2612 return VariableSettings;
2613 }
2614
2615 /**
2616 Worker function setting fixed MTRRs
2617
2618 @param[in] FixedSettings A buffer to hold fixed MTRRs content.
2619
2620 **/
2621 VOID
2622 MtrrSetFixedMtrrWorker (
2623 IN MTRR_FIXED_SETTINGS *FixedSettings
2624 )
2625 {
2626 UINT32 Index;
2627
2628 for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
2629 AsmWriteMsr64 (
2630 mMtrrLibFixedMtrrTable[Index].Msr,
2631 FixedSettings->Mtrr[Index]
2632 );
2633 }
2634 }
2635
2636
2637 /**
2638 This function sets fixed MTRRs
2639
2640 @param[in] FixedSettings A buffer to hold fixed MTRRs content.
2641
2642 @retval The pointer of FixedSettings
2643
2644 **/
2645 MTRR_FIXED_SETTINGS*
2646 EFIAPI
2647 MtrrSetFixedMtrr (
2648 IN MTRR_FIXED_SETTINGS *FixedSettings
2649 )
2650 {
2651 MTRR_CONTEXT MtrrContext;
2652
2653 if (!IsMtrrSupported ()) {
2654 return FixedSettings;
2655 }
2656
2657 MtrrLibPreMtrrChange (&MtrrContext);
2658 MtrrSetFixedMtrrWorker (FixedSettings);
2659 MtrrLibPostMtrrChange (&MtrrContext);
2660 MtrrDebugPrintAllMtrrs ();
2661
2662 return FixedSettings;
2663 }
2664
2665
2666 /**
2667 This function gets the content in all MTRRs (variable and fixed)
2668
2669 @param[out] MtrrSetting A buffer to hold all MTRRs content.
2670
2671 @retval the pointer of MtrrSetting
2672
2673 **/
2674 MTRR_SETTINGS *
2675 EFIAPI
2676 MtrrGetAllMtrrs (
2677 OUT MTRR_SETTINGS *MtrrSetting
2678 )
2679 {
2680 if (!IsMtrrSupported ()) {
2681 return MtrrSetting;
2682 }
2683
2684 //
2685 // Get fixed MTRRs
2686 //
2687 MtrrGetFixedMtrrWorker (&MtrrSetting->Fixed);
2688
2689 //
2690 // Get variable MTRRs
2691 //
2692 MtrrGetVariableMtrrWorker (
2693 NULL,
2694 GetVariableMtrrCountWorker (),
2695 &MtrrSetting->Variables
2696 );
2697
2698 //
2699 // Get MTRR_DEF_TYPE value
2700 //
2701 MtrrSetting->MtrrDefType = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2702
2703 return MtrrSetting;
2704 }
2705
2706
2707 /**
2708 This function sets all MTRRs (variable and fixed)
2709
2710 @param[in] MtrrSetting A buffer holding all MTRRs content.
2711
2712 @retval The pointer of MtrrSetting
2713
2714 **/
2715 MTRR_SETTINGS *
2716 EFIAPI
2717 MtrrSetAllMtrrs (
2718 IN MTRR_SETTINGS *MtrrSetting
2719 )
2720 {
2721 MTRR_CONTEXT MtrrContext;
2722
2723 if (!IsMtrrSupported ()) {
2724 return MtrrSetting;
2725 }
2726
2727 MtrrLibPreMtrrChange (&MtrrContext);
2728
2729 //
2730 // Set fixed MTRRs
2731 //
2732 MtrrSetFixedMtrrWorker (&MtrrSetting->Fixed);
2733
2734 //
2735 // Set variable MTRRs
2736 //
2737 MtrrSetVariableMtrrWorker (&MtrrSetting->Variables);
2738
2739 //
2740 // Set MTRR_DEF_TYPE value
2741 //
2742 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);
2743
2744 MtrrLibPostMtrrChangeEnableCache (&MtrrContext);
2745
2746 return MtrrSetting;
2747 }
2748
2749
2750 /**
2751 Checks if MTRR is supported.
2752
2753 @retval TRUE MTRR is supported.
2754 @retval FALSE MTRR is not supported.
2755
2756 **/
2757 BOOLEAN
2758 EFIAPI
2759 IsMtrrSupported (
2760 VOID
2761 )
2762 {
2763 CPUID_VERSION_INFO_EDX Edx;
2764 MSR_IA32_MTRRCAP_REGISTER MtrrCap;
2765
2766 //
2767 // Check CPUID(1).EDX[12] for MTRR capability
2768 //
2769 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32);
2770 if (Edx.Bits.MTRR == 0) {
2771 return FALSE;
2772 }
2773
2774 //
2775 // Check number of variable MTRRs and fixed MTRRs existence.
2776 // If number of variable MTRRs is zero, or fixed MTRRs do not
2777 // exist, return false.
2778 //
2779 MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
2780 if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) {
2781 return FALSE;
2782 }
2783 return TRUE;
2784 }
2785
2786
2787 /**
2788 Worker function prints all MTRRs for debugging.
2789
2790 If MtrrSetting is not NULL, print MTRR settings from input MTRR
2791 settings buffer.
2792 If MtrrSetting is NULL, print MTRR settings from MTRRs.
2793
2794 @param MtrrSetting A buffer holding all MTRRs content.
2795 **/
2796 VOID
2797 MtrrDebugPrintAllMtrrsWorker (
2798 IN MTRR_SETTINGS *MtrrSetting
2799 )
2800 {
2801 DEBUG_CODE (
2802 MTRR_SETTINGS LocalMtrrs;
2803 MTRR_SETTINGS *Mtrrs;
2804 UINTN Index;
2805 UINTN RangeCount;
2806 UINT64 MtrrValidBitsMask;
2807 UINT64 MtrrValidAddressMask;
2808 UINT32 VariableMtrrCount;
2809 BOOLEAN ContainVariableMtrr;
2810 MTRR_MEMORY_RANGE Ranges[
2811 ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1
2812 ];
2813 MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];
2814
2815 if (!IsMtrrSupported ()) {
2816 return;
2817 }
2818
2819 VariableMtrrCount = GetVariableMtrrCountWorker ();
2820
2821 if (MtrrSetting != NULL) {
2822 Mtrrs = MtrrSetting;
2823 } else {
2824 MtrrGetAllMtrrs (&LocalMtrrs);
2825 Mtrrs = &LocalMtrrs;
2826 }
2827
2828 //
2829 // Dump RAW MTRR contents
2830 //
2831 DEBUG ((DEBUG_CACHE, "MTRR Settings:\n"));
2832 DEBUG ((DEBUG_CACHE, "=============\n"));
2833 DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));
2834 for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {
2835 DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));
2836 }
2837 ContainVariableMtrr = FALSE;
2838 for (Index = 0; Index < VariableMtrrCount; Index++) {
2839 if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 0) {
2840 //
2841 // If mask is not valid, then do not display range
2842 //
2843 continue;
2844 }
2845 ContainVariableMtrr = TRUE;
2846 DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",
2847 Index,
2848 Mtrrs->Variables.Mtrr[Index].Base,
2849 Mtrrs->Variables.Mtrr[Index].Mask
2850 ));
2851 }
2852 if (!ContainVariableMtrr) {
2853 DEBUG ((DEBUG_CACHE, "Variable MTRR : None.\n"));
2854 }
2855 DEBUG((DEBUG_CACHE, "\n"));
2856
2857 //
2858 // Dump MTRR setting in ranges
2859 //
2860 DEBUG((DEBUG_CACHE, "Memory Ranges:\n"));
2861 DEBUG((DEBUG_CACHE, "====================================\n"));
2862 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
2863 Ranges[0].BaseAddress = 0;
2864 Ranges[0].Length = MtrrValidBitsMask + 1;
2865 Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs);
2866 RangeCount = 1;
2867
2868 MtrrLibGetRawVariableRanges (
2869 &Mtrrs->Variables, VariableMtrrCount,
2870 MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges
2871 );
2872 MtrrLibApplyVariableMtrrs (
2873 RawVariableRanges, VariableMtrrCount,
2874 Ranges, ARRAY_SIZE (Ranges), &RangeCount
2875 );
2876
2877 MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);
2878
2879 for (Index = 0; Index < RangeCount; Index++) {
2880 DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n",
2881 mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],
2882 Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1
2883 ));
2884 }
2885 );
2886 }
2887
2888 /**
2889 This function prints all MTRRs for debugging.
2890 **/
2891 VOID
2892 EFIAPI
2893 MtrrDebugPrintAllMtrrs (
2894 VOID
2895 )
2896 {
2897 MtrrDebugPrintAllMtrrsWorker (NULL);
2898 }