1 #------------------------------------------------------------------------------
3 # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php.
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 # Code template of the SMI handler for a particular processor
20 #------------------------------------------------------------------------------
22 ASM_GLOBAL ASM_PFX(gcStmSmiHandlerTemplate)
23 ASM_GLOBAL ASM_PFX(gcStmSmiHandlerSize)
24 ASM_GLOBAL ASM_PFX(gcStmSmiHandlerOffset)
25 ASM_GLOBAL ASM_PFX(gStmSmiCr3)
26 ASM_GLOBAL ASM_PFX(gStmSmiStack)
27 ASM_GLOBAL ASM_PFX(gStmSmbase)
28 ASM_GLOBAL ASM_PFX(gStmXdSupported)
29 ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
30 ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
32 .equ MSR_IA32_MISC_ENABLE, 0x1A0
33 .equ MSR_EFER, 0xc0000080
34 .equ MSR_EFER_XD, 0x800
37 # Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
39 .equ DSC_OFFSET, 0xfb00
45 .equ DSC_OTHERSEG, 0x1A
47 .equ PROTECT_MODE_CS, 0x08
48 .equ PROTECT_MODE_DS, 0x20
49 .equ TSS_SEGMENT, 0x40
52 ASM_PFX(gcStmSmiHandlerTemplate):
55 .byte 0xbb # mov bx, imm16
56 .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
57 .byte 0x2e,0xa1 # mov ax, cs:[offset16]
58 .word DSC_OFFSET + DSC_GDTSIZ
60 movl %eax, %cs:(%edi) # mov cs:[bx], ax
61 .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
62 .word DSC_OFFSET + DSC_GDTPTR
64 movw %ax, %bp # ebp = GDT base
67 # Patch ProtectedMode Segment
68 .byte 0xb8 # mov ax, imm16
69 .word PROTECT_MODE_CS # set AX for segment directly
70 movl %eax, %cs:-2(%edi) # mov cs:[bx - 2], ax
71 # Patch ProtectedMode entry
72 .byte 0x66, 0xbf # mov edi, SMBASE
73 ASM_PFX(gStmSmbase): .space 4
75 lea ((Start32bit - _StmSmiEntryPoint) + 0x8000)(%edi), %ax
76 movw %ax, %cs:-6(%edi)
79 andl $0x9ffafff3, %ebx
90 movw $PROTECT_MODE_DS, %ax
96 .byte 0xbc # mov esp, imm32
97 ASM_PFX(gStmSmiStack): .space 4
98 movl $ASM_PFX(gStmSmiHandlerIdtr), %eax
103 .byte 0xb8 # mov eax, imm32
104 ASM_PFX(gStmSmiCr3): .space 4
107 # Need to test for CR4 specific bit support
110 cpuid # use CPUID to determine if specific CR4 bits are supported
111 xorl %eax, %eax # Clear EAX
112 testl $BIT2, %edx # Check for DE capabilities
116 testl $BIT6, %edx # Check for PAE capabilities
120 testl $BIT7, %edx # Check for MCE capabilities
124 testl $BIT24, %edx # Check for FXSR capabilities
128 testl $BIT25, %edx # Check for SSE capabilities
131 L12: # as cr4.PGE is not set here, refresh cr3
132 movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
134 cmpb $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
137 movb $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
138 movl $TSS_SEGMENT, %eax
142 # enable NXE if supported
143 .byte 0xb0 # mov al, imm8
144 ASM_PFX(gStmXdSupported): .byte 1
148 # Check XD disable bit
150 movl $MSR_IA32_MISC_ENABLE, %ecx
152 pushl %edx # save MSR_IA32_MISC_ENABLE[63-32]
153 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
155 andw $0x0FFFB, %dx # clear XD Disable bit if it is set
160 orw $MSR_EFER_XD,%ax # enable NXE
168 orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
170 leal DSC_OFFSET(%edi),%ebx
171 movw DSC_DS(%ebx),%ax
173 movw DSC_OTHERSEG(%ebx),%ax
177 movw DSC_SS(%ebx),%ax
184 movl $ASM_PFX(CpuSmmDebugEntry), %eax
189 movl $ASM_PFX(SmiRendezvous), %eax
194 movl $ASM_PFX(CpuSmmDebugExit), %eax
198 movl $ASM_PFX(gStmXdSupported), %eax
202 popl %edx # get saved MSR_IA32_MISC_ENABLE[63-32]
205 movl $MSR_IA32_MISC_ENABLE, %ecx
207 orw $BIT2, %dx # set XD Disable bit if it was set before entering into SMM
215 # Check XD disable bit
218 movl $ASM_PFX(gStmXdSupported), %eax
222 movl $MSR_IA32_MISC_ENABLE, %ecx
224 movl %edx, %esi # save MSR_IA32_MISC_ENABLE[63-32]
225 testl $BIT2, %edx # MSR_IA32_MISC_ENABLE[34]
227 andw $0x0FFFB, %dx # clear XD Disable bit if it is set
232 orw $MSR_EFER_XD,%ax # enable NXE
237 # below step is needed, because STM does not run above code.
238 # we have to run below code to set IDT/CR0/CR4
239 movl $ASM_PFX(gStmSmiHandlerIdtr), %eax
243 orl $0x80010023, %eax # enable paging + WP + NE + MP + PE
246 # Need to test for CR4 specific bit support
249 cpuid # use CPUID to determine if specific CR4 bits are supported
250 movl %cr4, %eax # init EAX
251 testl $BIT2, %edx # Check for DE capabilities
255 testl $BIT6, %edx # Check for PAE capabilities
259 testl $BIT7, %edx # Check for MCE capabilities
263 testl $BIT24, %edx # Check for FXSR capabilities
267 testl $BIT25, %edx # Check for SSE capabilities
270 L32: # as cr4.PGE is not set here, refresh cr3
271 movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
276 ASM_PFX(gcStmSmiHandlerSize) : .word . - _StmSmiEntryPoint
277 ASM_PFX(gcStmSmiHandlerOffset): .word _StmSmiHandler - _StmSmiEntryPoint