UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmiException.asm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Exception handlers used in SM mode
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21     .686p
  22     .model  flat,C
  23
  24 EXTERNDEF   gcStmPsd:BYTE
  25
  26 EXTERNDEF   SmmStmExceptionHandler:PROC
  27 EXTERNDEF   SmmStmSetup:PROC
  28 EXTERNDEF   SmmStmTeardown:PROC
  29 EXTERNDEF   gStmXdSupported:BYTE
  30
  31 CODE_SEL    = 08h
  32 DATA_SEL    = 20h
  33 TSS_SEL     = 40h
  34
  35 MSR_IA32_MISC_ENABLE  EQU     1A0h
  36 MSR_EFER              EQU     0c0000080h
  37 MSR_EFER_XD           EQU     0800h
  38
  39     .data
  40
  41 gcStmPsd     LABEL   BYTE
  42             DB      'TXTPSSIG'
  43             DW      PSD_SIZE
  44             DW      1              ; Version
  45             DD      0              ; LocalApicId
  46             DB      05h            ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  47             DB      0              ; BIOS to STM
  48             DB      0              ; STM to BIOS
  49             DB      0
  50             DW      CODE_SEL
  51             DW      DATA_SEL
  52             DW      DATA_SEL
  53             DW      DATA_SEL
  54             DW      TSS_SEL
  55             DW      0
  56             DQ      0              ; SmmCr3
  57             DQ      _OnStmSetup
  58             DQ      _OnStmTeardown
  59             DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint
  60             DQ      0              ; SmmSmiHandlerRsp
  61             DQ      0
  62             DD      0
  63             DD      80010100h      ; RequiredStmSmmRevId
  64             DQ      _OnException
  65             DQ      0              ; ExceptionStack
  66             DW      DATA_SEL
  67             DW      01Fh           ; ExceptionFilter
  68             DD      0
  69             DQ      0
  70             DQ      0              ; BiosHwResourceRequirementsPtr
  71             DQ      0              ; AcpiRsdp
  72             DB      0              ; PhysicalAddressBits
  73 PSD_SIZE  = $ - offset gcStmPsd
  74
  75     .code
  76 ;------------------------------------------------------------------------------
  77 ; SMM Exception handlers
  78 ;------------------------------------------------------------------------------
  79 _OnException       PROC
  80     mov  ecx, esp
  81     push ecx
  82     call SmmStmExceptionHandler
  83     add  esp, 4
  84
  85     mov  ebx, eax
  86     mov  eax, 4
  87     DB  0fh, 01h, 0c1h ; VMCALL
  88     jmp $
  89 _OnException       ENDP
  90
  91 _OnStmSetup PROC
  92 ;
  93 ; Check XD disable bit
  94 ;
  95     xor     esi, esi
  96     mov     eax, offset gStmXdSupported
  97     mov     al, [eax]
  98     cmp     al, 0
  99     jz      @StmXdDone1
 100     mov     ecx, MSR_IA32_MISC_ENABLE
 101     rdmsr
 102     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 103     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 104     jz      @f
 105     and     dx, 0FFFBh                 ; clear XD Disable bit if it is set
 106     wrmsr
 107 @@:
 108     mov     ecx, MSR_EFER
 109     rdmsr
 110     or      ax, MSR_EFER_XD             ; enable NXE
 111     wrmsr
 112 @StmXdDone1:
 113     push    esi
 114
 115   call SmmStmSetup
 116
 117     mov     eax, offset gStmXdSupported
 118     mov     al, [eax]
 119     cmp     al, 0
 120     jz      @f
 121     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 122     test    edx, BIT2
 123     jz      @f
 124     mov     ecx, MSR_IA32_MISC_ENABLE
 125     rdmsr
 126     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 127     wrmsr
 128 @@:
 129
 130   rsm
 131 _OnStmSetup ENDP
 132
 133 _OnStmTeardown PROC
 134 ;
 135 ; Check XD disable bit
 136 ;
 137     xor     esi, esi
 138     mov     eax, offset gStmXdSupported
 139     mov     al, [eax]
 140     cmp     al, 0
 141     jz      @StmXdDone2
 142     mov     ecx, MSR_IA32_MISC_ENABLE
 143     rdmsr
 144     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 145     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 146     jz      @f
 147     and     dx, 0FFFBh                 ; clear XD Disable bit if it is set
 148     wrmsr
 149 @@:
 150     mov     ecx, MSR_EFER
 151     rdmsr
 152     or      ax, MSR_EFER_XD             ; enable NXE
 153     wrmsr
 154 @StmXdDone2:
 155     push    esi
 156
 157   call SmmStmTeardown
 158
 159     mov     eax, offset gStmXdSupported
 160     mov     al, [eax]
 161     cmp     al, 0
 162     jz      @f
 163     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 164     test    edx, BIT2
 165     jz      @f
 166     mov     ecx, MSR_IA32_MISC_ENABLE
 167     rdmsr
 168     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 169     wrmsr
 170 @@:
 171
 172   rsm
 173 _OnStmTeardown ENDP
 174
 175     END