UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmiException.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Exception handlers used in SM mode
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 global  ASM_PFX(gcStmPsd)
  22
  23 extern  ASM_PFX(SmmStmExceptionHandler)
  24 extern  ASM_PFX(SmmStmSetup)
  25 extern  ASM_PFX(SmmStmTeardown)
  26 extern  ASM_PFX(gStmXdSupported)
  27 extern  ASM_PFX(gStmSmiHandlerIdtr)
  28
  29 %define MSR_IA32_MISC_ENABLE 0x1A0
  30 %define MSR_EFER      0xc0000080
  31 %define MSR_EFER_XD   0x800
  32
  33 CODE_SEL          equ 0x08
  34 DATA_SEL          equ 0x20
  35 TSS_SEL           equ 0x40
  36
  37     SECTION .data
  38
  39 ASM_PFX(gcStmPsd):
  40             DB      'TXTPSSIG'
  41             DW      PSD_SIZE
  42             DW      1              ; Version
  43             DD      0              ; LocalApicId
  44             DB      0x05           ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  45             DB      0              ; BIOS to STM
  46             DB      0              ; STM to BIOS
  47             DB      0
  48             DW      CODE_SEL
  49             DW      DATA_SEL
  50             DW      DATA_SEL
  51             DW      DATA_SEL
  52             DW      TSS_SEL
  53             DW      0
  54             DQ      0              ; SmmCr3
  55             DD      ASM_PFX(OnStmSetup)
  56             DD      0
  57             DD      ASM_PFX(OnStmTeardown)
  58             DD      0
  59             DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint
  60             DQ      0              ; SmmSmiHandlerRsp
  61             DQ      0
  62             DD      0
  63             DD      0x80010100     ; RequiredStmSmmRevId
  64             DD      ASM_PFX(OnException)
  65             DD      0
  66             DQ      0              ; ExceptionStack
  67             DW      DATA_SEL
  68             DW      0x01F          ; ExceptionFilter
  69             DD      0
  70             DD      0
  71             DD      0
  72             DQ      0              ; BiosHwResourceRequirementsPtr
  73             DQ      0              ; AcpiRsdp
  74             DB      0              ; PhysicalAddressBits
  75 PSD_SIZE  equ $ - ASM_PFX(gcStmPsd)
  76
  77     SECTION .text
  78 ;------------------------------------------------------------------------------
  79 ; SMM Exception handlers
  80 ;------------------------------------------------------------------------------
  81 global ASM_PFX(OnException)
  82 ASM_PFX(OnException):
  83     mov  ecx, esp
  84     push ecx
  85     call ASM_PFX(SmmStmExceptionHandler)
  86     add  esp, 4
  87
  88     mov  ebx, eax
  89     mov  eax, 4
  90     DB  0x0f, 0x01, 0x0c1 ; VMCALL
  91     jmp $
  92
  93 global ASM_PFX(OnStmSetup)
  94 ASM_PFX(OnStmSetup):
  95 ;
  96 ; Check XD disable bit
  97 ;
  98     xor     esi, esi
  99     mov     eax, ASM_PFX(gStmXdSupported)
 100     mov     al, [eax]
 101     cmp     al, 0
 102     jz      @StmXdDone1
 103     mov     ecx, MSR_IA32_MISC_ENABLE
 104     rdmsr
 105     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 106     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 107     jz      .51
 108     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 109     wrmsr
 110 .51:
 111     mov     ecx, MSR_EFER
 112     rdmsr
 113     or      ax, MSR_EFER_XD             ; enable NXE
 114     wrmsr
 115 @StmXdDone1:
 116     push    esi
 117
 118   call ASM_PFX(SmmStmSetup)
 119
 120     mov     eax, ASM_PFX(gStmXdSupported)
 121     mov     al, [eax]
 122     cmp     al, 0
 123     jz      .71
 124     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 125     test    edx, BIT2
 126     jz      .71
 127     mov     ecx, MSR_IA32_MISC_ENABLE
 128     rdmsr
 129     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 130     wrmsr
 131
 132 .71:
 133   rsm
 134
 135 global  ASM_PFX(OnStmTeardown)
 136 ASM_PFX(OnStmTeardown):
 137 ;
 138 ; Check XD disable bit
 139 ;
 140     xor     esi, esi
 141     mov     eax, ASM_PFX(gStmXdSupported)
 142     mov     al, [eax]
 143     cmp     al, 0
 144     jz      @StmXdDone2
 145     mov     ecx, MSR_IA32_MISC_ENABLE
 146     rdmsr
 147     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 148     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 149     jz      .52
 150     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 151     wrmsr
 152 .52:
 153     mov     ecx, MSR_EFER
 154     rdmsr
 155     or      ax, MSR_EFER_XD             ; enable NXE
 156     wrmsr
 157 @StmXdDone2:
 158     push    esi
 159
 160   call ASM_PFX(SmmStmTeardown)
 161
 162     mov     eax, ASM_PFX(gStmXdSupported)
 163     mov     al, [eax]
 164     cmp     al, 0
 165     jz      .72
 166     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 167     test    edx, BIT2
 168     jz      .72
 169     mov     ecx, MSR_IA32_MISC_ENABLE
 170     rdmsr
 171     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 172     wrmsr
 173
 174 .72:
 175   rsm
 176