UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   4 ;
   5 ; Module Name:
   6 ;
   7 ;   SmiException.nasm
   8 ;
   9 ; Abstract:
  10 ;
  11 ;   Exception handlers used in SM mode
  12 ;
  13 ;-------------------------------------------------------------------------------
  14
  15 %include "StuffRsbNasm.inc"
  16
  17 global  ASM_PFX(gcStmPsd)
  18
  19 extern  ASM_PFX(SmmStmExceptionHandler)
  20 extern  ASM_PFX(SmmStmSetup)
  21 extern  ASM_PFX(SmmStmTeardown)
  22 extern  ASM_PFX(gStmXdSupported)
  23 extern  ASM_PFX(gStmSmiHandlerIdtr)
  24
  25 %define MSR_IA32_MISC_ENABLE 0x1A0
  26 %define MSR_EFER      0xc0000080
  27 %define MSR_EFER_XD   0x800
  28
  29 CODE_SEL          equ 0x08
  30 DATA_SEL          equ 0x20
  31 TSS_SEL           equ 0x40
  32
  33     SECTION .data
  34
  35 ASM_PFX(gcStmPsd):
  36             DB      'TXTPSSIG'
  37             DW      PSD_SIZE
  38             DW      1              ; Version
  39             DD      0              ; LocalApicId
  40             DB      0x05           ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  41             DB      0              ; BIOS to STM
  42             DB      0              ; STM to BIOS
  43             DB      0
  44             DW      CODE_SEL
  45             DW      DATA_SEL
  46             DW      DATA_SEL
  47             DW      DATA_SEL
  48             DW      TSS_SEL
  49             DW      0
  50             DQ      0              ; SmmCr3
  51             DD      ASM_PFX(OnStmSetup)
  52             DD      0
  53             DD      ASM_PFX(OnStmTeardown)
  54             DD      0
  55             DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint
  56             DQ      0              ; SmmSmiHandlerRsp
  57             DQ      0
  58             DD      0
  59             DD      0x80010100     ; RequiredStmSmmRevId
  60             DD      ASM_PFX(OnException)
  61             DD      0
  62             DQ      0              ; ExceptionStack
  63             DW      DATA_SEL
  64             DW      0x01F          ; ExceptionFilter
  65             DD      0
  66             DD      0
  67             DD      0
  68             DQ      0              ; BiosHwResourceRequirementsPtr
  69             DQ      0              ; AcpiRsdp
  70             DB      0              ; PhysicalAddressBits
  71 PSD_SIZE  equ $ - ASM_PFX(gcStmPsd)
  72
  73     SECTION .text
  74 ;------------------------------------------------------------------------------
  75 ; SMM Exception handlers
  76 ;------------------------------------------------------------------------------
  77 global ASM_PFX(OnException)
  78 ASM_PFX(OnException):
  79     mov  ecx, esp
  80     push ecx
  81     call ASM_PFX(SmmStmExceptionHandler)
  82     add  esp, 4
  83
  84     mov  ebx, eax
  85     mov  eax, 4
  86     vmcall
  87     jmp $
  88
  89 global ASM_PFX(OnStmSetup)
  90 ASM_PFX(OnStmSetup):
  91 ;
  92 ; Check XD disable bit
  93 ;
  94     xor     esi, esi
  95     mov     eax, ASM_PFX(gStmXdSupported)
  96     mov     al, [eax]
  97     cmp     al, 0
  98     jz      @StmXdDone1
  99     mov     ecx, MSR_IA32_MISC_ENABLE
 100     rdmsr
 101     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 102     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 103     jz      .51
 104     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 105     wrmsr
 106 .51:
 107     mov     ecx, MSR_EFER
 108     rdmsr
 109     or      ax, MSR_EFER_XD             ; enable NXE
 110     wrmsr
 111 @StmXdDone1:
 112     push    esi
 113
 114   call ASM_PFX(SmmStmSetup)
 115
 116     mov     eax, ASM_PFX(gStmXdSupported)
 117     mov     al, [eax]
 118     cmp     al, 0
 119     jz      .71
 120     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 121     test    edx, BIT2
 122     jz      .71
 123     mov     ecx, MSR_IA32_MISC_ENABLE
 124     rdmsr
 125     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 126     wrmsr
 127
 128 .71:
 129     StuffRsb32
 130     rsm
 131
 132 global  ASM_PFX(OnStmTeardown)
 133 ASM_PFX(OnStmTeardown):
 134 ;
 135 ; Check XD disable bit
 136 ;
 137     xor     esi, esi
 138     mov     eax, ASM_PFX(gStmXdSupported)
 139     mov     al, [eax]
 140     cmp     al, 0
 141     jz      @StmXdDone2
 142     mov     ecx, MSR_IA32_MISC_ENABLE
 143     rdmsr
 144     mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]
 145     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 146     jz      .52
 147     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 148     wrmsr
 149 .52:
 150     mov     ecx, MSR_EFER
 151     rdmsr
 152     or      ax, MSR_EFER_XD             ; enable NXE
 153     wrmsr
 154 @StmXdDone2:
 155     push    esi
 156
 157   call ASM_PFX(SmmStmTeardown)
 158
 159     mov     eax, ASM_PFX(gStmXdSupported)
 160     mov     al, [eax]
 161     cmp     al, 0
 162     jz      .72
 163     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 164     test    edx, BIT2
 165     jz      .72
 166     mov     ecx, MSR_IA32_MISC_ENABLE
 167     rdmsr
 168     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 169     wrmsr
 170
 171 .72:
 172     StuffRsb32
 173     rsm