UefiCpuPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields check
[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / SmmCpuFeaturesLib.c
1 /** @file
2 The CPU specific programming for PiSmmCpuDxeSmm module.
3
4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include <PiSmm.h>
16 #include <Library/SmmCpuFeaturesLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/MtrrLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/MemoryAllocationLib.h>
21 #include <Library/DebugLib.h>
22 #include <Register/Cpuid.h>
23 #include <Register/SmramSaveStateMap.h>
24
25 //
26 // Machine Specific Registers (MSRs)
27 //
28 #define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE
29 #define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A
30 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2
31 #define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3
32 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0
33 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
34 #define EFI_MSR_SMRR_MASK 0xFFFFF000
35 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
36 #define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
37
38 //
39 // MSRs required for configuration of SMM Code Access Check
40 //
41 #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
42 #define SMM_CODE_ACCESS_CHK_BIT BIT58
43
44 //
45 // Set default value to assume SMRR is not supported
46 //
47 BOOLEAN mSmrrSupported = FALSE;
48
49 //
50 // Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
51 //
52 BOOLEAN mSmmFeatureControlSupported = FALSE;
53
54 //
55 // Set default value to assume IA-32 Architectural MSRs are used
56 //
57 UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
58 UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
59
60 //
61 // Set default value to assume MTRRs need to be configured on each SMI
62 //
63 BOOLEAN mNeedConfigureMtrrs = TRUE;
64
65 //
66 // Array for state of SMRR enable on all CPUs
67 //
68 BOOLEAN *mSmrrEnabled;
69
70 /**
71 The constructor function
72
73 @param[in] ImageHandle The firmware allocated handle for the EFI image.
74 @param[in] SystemTable A pointer to the EFI System Table.
75
76 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
77
78 **/
79 EFI_STATUS
80 EFIAPI
81 SmmCpuFeaturesLibConstructor (
82 IN EFI_HANDLE ImageHandle,
83 IN EFI_SYSTEM_TABLE *SystemTable
84 )
85 {
86 UINT32 RegEax;
87 UINT32 RegEdx;
88 UINTN FamilyId;
89 UINTN ModelId;
90
91 //
92 // Retrieve CPU Family and Model
93 //
94 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
95 FamilyId = (RegEax >> 8) & 0xf;
96 ModelId = (RegEax >> 4) & 0xf;
97 if (FamilyId == 0x06 || FamilyId == 0x0f) {
98 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
99 }
100
101 //
102 // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability
103 //
104 if ((RegEdx & BIT12) != 0) {
105 //
106 // Check MTRR_CAP MSR bit 11 for SMRR support
107 //
108 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {
109 mSmrrSupported = TRUE;
110 }
111 }
112
113 //
114 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
115 // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family
116 //
117 // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then
118 // SMRR Physical Base and SMM Physical Mask MSRs are not available.
119 //
120 if (FamilyId == 0x06) {
121 if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {
122 mSmrrSupported = FALSE;
123 }
124 }
125
126 //
127 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
128 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
129 //
130 // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2
131 // Processor Family MSRs
132 //
133 if (FamilyId == 0x06) {
134 if (ModelId == 0x17 || ModelId == 0x0f) {
135 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
136 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
137 }
138 }
139
140 //
141 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
142 // Volume 3C, Section 34.4.2 SMRAM Caching
143 // An IA-32 processor does not automatically write back and invalidate its
144 // caches before entering SMM or before exiting SMM. Because of this behavior,
145 // care must be taken in the placement of the SMRAM in system memory and in
146 // the caching of the SMRAM to prevent cache incoherence when switching back
147 // and forth between SMM and protected mode operation.
148 //
149 // An IA-32 processor is a processor that does not support the Intel 64
150 // Architecture. Support for the Intel 64 Architecture can be detected from
151 // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]
152 //
153 // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,
154 // so caches are flushed on SMI entry and SMI exit, the interrupted code
155 // MTRRs are saved/restored, and MTRRs for SMM are loaded.
156 //
157 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
158 if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
159 AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
160 if ((RegEdx & BIT29) != 0) {
161 mNeedConfigureMtrrs = FALSE;
162 }
163 }
164
165 //
166 // Allocate array for state of SMRR enable on all CPUs
167 //
168 mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));
169 ASSERT (mSmrrEnabled != NULL);
170
171 return EFI_SUCCESS;
172 }
173
174 /**
175 Called during the very first SMI into System Management Mode to initialize
176 CPU features, including SMBASE, for the currently executing CPU. Since this
177 is the first SMI, the SMRAM Save State Map is at the default address of
178 SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing
179 CPU is specified by CpuIndex and CpuIndex can be used to access information
180 about the currently executing CPU in the ProcessorInfo array and the
181 HotPlugCpuData data structure.
182
183 @param[in] CpuIndex The index of the CPU to initialize. The value
184 must be between 0 and the NumberOfCpus field in
185 the System Management System Table (SMST).
186 @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that
187 was elected as monarch during System Management
188 Mode initialization.
189 FALSE if the CpuIndex is not the index of the CPU
190 that was elected as monarch during System
191 Management Mode initialization.
192 @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION
193 structures. ProcessorInfo[CpuIndex] contains the
194 information for the currently executing CPU.
195 @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that
196 contains the ApidId and SmBase arrays.
197 **/
198 VOID
199 EFIAPI
200 SmmCpuFeaturesInitializeProcessor (
201 IN UINTN CpuIndex,
202 IN BOOLEAN IsMonarch,
203 IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,
204 IN CPU_HOT_PLUG_DATA *CpuHotPlugData
205 )
206 {
207 SMRAM_SAVE_STATE_MAP *CpuState;
208 UINT64 FeatureControl;
209 UINT32 RegEax;
210 UINT32 RegEdx;
211 UINTN FamilyId;
212 UINTN ModelId;
213
214 //
215 // Configure SMBASE.
216 //
217 CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
218 CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
219
220 //
221 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
222 // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family
223 //
224 // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then
225 // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before
226 // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
227 // is set, then the MSR is locked and can not be modified.
228 //
229 if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {
230 FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
231 if ((FeatureControl & BIT3) == 0) {
232 if ((FeatureControl & BIT0) == 0) {
233 AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);
234 } else {
235 mSmrrSupported = FALSE;
236 }
237 }
238 }
239
240 //
241 // If SMRR is supported, then program SMRR base/mask MSRs.
242 // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
243 // The code that initializes SMM environment is running in normal mode
244 // from SMRAM region. If SMRR is enabled here, then the SMRAM region
245 // is protected and the normal mode code execution will fail.
246 //
247 if (mSmrrSupported) {
248 //
249 // SMRR size cannot be less than 4-KBytes
250 // SMRR size must be of length 2^n
251 // SMRR base alignment cannot be less than SMRR length
252 //
253 if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
254 (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
255 ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {
256 //
257 // Print message and halt if CPU is Monarch
258 //
259 if (IsMonarch) {
260 DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
261 CpuDeadLoop ();
262 }
263 } else {
264 AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);
265 AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));
266 mSmrrEnabled[CpuIndex] = FALSE;
267 }
268 }
269
270 //
271 // Retrieve CPU Family and Model
272 //
273 AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
274 FamilyId = (RegEax >> 8) & 0xf;
275 ModelId = (RegEax >> 4) & 0xf;
276 if (FamilyId == 0x06 || FamilyId == 0x0f) {
277 ModelId = ModelId | ((RegEax >> 12) & 0xf0);
278 }
279
280 //
281 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
282 // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
283 // Processor Family.
284 //
285 // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
286 // Intel(R) Core(TM) Processor Family MSRs.
287 //
288 if (FamilyId == 0x06) {
289 if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
290 //
291 // Check to see if the CPU supports the SMM Code Access Check feature
292 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
293 //
294 if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {
295 mSmmFeatureControlSupported = TRUE;
296 }
297 }
298 }
299 }
300
301 /**
302 This function updates the SMRAM save state on the currently executing CPU
303 to resume execution at a specific address after an RSM instruction. This
304 function must evaluate the SMRAM save state to determine the execution mode
305 the RSM instruction resumes and update the resume execution address with
306 either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart
307 flag in the SMRAM save state must always be cleared. This function returns
308 the value of the instruction pointer from the SMRAM save state that was
309 replaced. If this function returns 0, then the SMRAM save state was not
310 modified.
311
312 This function is called during the very first SMI on each CPU after
313 SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
314 to signal that the SMBASE of each CPU has been updated before the default
315 SMBASE address is used for the first SMI to the next CPU.
316
317 @param[in] CpuIndex The index of the CPU to hook. The value
318 must be between 0 and the NumberOfCpus
319 field in the System Management System Table
320 (SMST).
321 @param[in] CpuState Pointer to SMRAM Save State Map for the
322 currently executing CPU.
323 @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
324 32-bit execution mode from 64-bit SMM.
325 @param[in] NewInstructionPointer Instruction pointer to use if resuming to
326 same execution mode as SMM.
327
328 @retval 0 This function did modify the SMRAM save state.
329 @retval > 0 The original instruction pointer value from the SMRAM save state
330 before it was replaced.
331 **/
332 UINT64
333 EFIAPI
334 SmmCpuFeaturesHookReturnFromSmm (
335 IN UINTN CpuIndex,
336 IN SMRAM_SAVE_STATE_MAP *CpuState,
337 IN UINT64 NewInstructionPointer32,
338 IN UINT64 NewInstructionPointer
339 )
340 {
341 return 0;
342 }
343
344 /**
345 Hook point in normal execution mode that allows the one CPU that was elected
346 as monarch during System Management Mode initialization to perform additional
347 initialization actions immediately after all of the CPUs have processed their
348 first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE
349 into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().
350 **/
351 VOID
352 EFIAPI
353 SmmCpuFeaturesSmmRelocationComplete (
354 VOID
355 )
356 {
357 }
358
359 /**
360 Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is
361 returned, then a custom SMI handler is not provided by this library,
362 and the default SMI handler must be used.
363
364 @retval 0 Use the default SMI handler.
365 @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
366 The caller is required to allocate enough SMRAM for each CPU to
367 support the size of the custom SMI handler.
368 **/
369 UINTN
370 EFIAPI
371 SmmCpuFeaturesGetSmiHandlerSize (
372 VOID
373 )
374 {
375 return 0;
376 }
377
378 /**
379 Install a custom SMI handler for the CPU specified by CpuIndex. This function
380 is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
381 than zero and is called by the CPU that was elected as monarch during System
382 Management Mode initialization.
383
384 @param[in] CpuIndex The index of the CPU to install the custom SMI handler.
385 The value must be between 0 and the NumberOfCpus field
386 in the System Management System Table (SMST).
387 @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
388 @param[in] SmiStack The stack to use when an SMI is processed by the
389 the CPU specified by CpuIndex.
390 @param[in] StackSize The size, in bytes, if the stack used when an SMI is
391 processed by the CPU specified by CpuIndex.
392 @param[in] GdtBase The base address of the GDT to use when an SMI is
393 processed by the CPU specified by CpuIndex.
394 @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
395 processed by the CPU specified by CpuIndex.
396 @param[in] IdtBase The base address of the IDT to use when an SMI is
397 processed by the CPU specified by CpuIndex.
398 @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
399 processed by the CPU specified by CpuIndex.
400 @param[in] Cr3 The base address of the page tables to use when an SMI
401 is processed by the CPU specified by CpuIndex.
402 **/
403 VOID
404 EFIAPI
405 SmmCpuFeaturesInstallSmiHandler (
406 IN UINTN CpuIndex,
407 IN UINT32 SmBase,
408 IN VOID *SmiStack,
409 IN UINTN StackSize,
410 IN UINTN GdtBase,
411 IN UINTN GdtSize,
412 IN UINTN IdtBase,
413 IN UINTN IdtSize,
414 IN UINT32 Cr3
415 )
416 {
417 }
418
419 /**
420 Determines if MTRR registers must be configured to set SMRAM cache-ability
421 when executing in System Management Mode.
422
423 @retval TRUE MTRR registers must be configured to set SMRAM cache-ability.
424 @retval FALSE MTRR registers do not need to be configured to set SMRAM
425 cache-ability.
426 **/
427 BOOLEAN
428 EFIAPI
429 SmmCpuFeaturesNeedConfigureMtrrs (
430 VOID
431 )
432 {
433 return mNeedConfigureMtrrs;
434 }
435
436 /**
437 Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
438 returns TRUE.
439 **/
440 VOID
441 EFIAPI
442 SmmCpuFeaturesDisableSmrr (
443 VOID
444 )
445 {
446 if (mSmrrSupported && mNeedConfigureMtrrs) {
447 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
448 }
449 }
450
451 /**
452 Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
453 returns TRUE.
454 **/
455 VOID
456 EFIAPI
457 SmmCpuFeaturesReenableSmrr (
458 VOID
459 )
460 {
461 if (mSmrrSupported && mNeedConfigureMtrrs) {
462 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
463 }
464 }
465
466 /**
467 Processor specific hook point each time a CPU enters System Management Mode.
468
469 @param[in] CpuIndex The index of the CPU that has entered SMM. The value
470 must be between 0 and the NumberOfCpus field in the
471 System Management System Table (SMST).
472 **/
473 VOID
474 EFIAPI
475 SmmCpuFeaturesRendezvousEntry (
476 IN UINTN CpuIndex
477 )
478 {
479 //
480 // If SMRR is supported and this is the first normal SMI, then enable SMRR
481 //
482 if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) {
483 AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
484 mSmrrEnabled[CpuIndex] = TRUE;
485 }
486 }
487
488 /**
489 Processor specific hook point each time a CPU exits System Management Mode.
490
491 @param[in] CpuIndex The index of the CPU that is exiting SMM. The value must
492 be between 0 and the NumberOfCpus field in the System
493 Management System Table (SMST).
494 **/
495 VOID
496 EFIAPI
497 SmmCpuFeaturesRendezvousExit (
498 IN UINTN CpuIndex
499 )
500 {
501 }
502
503 /**
504 Check to see if an SMM register is supported by a specified CPU.
505
506 @param[in] CpuIndex The index of the CPU to check for SMM register support.
507 The value must be between 0 and the NumberOfCpus field
508 in the System Management System Table (SMST).
509 @param[in] RegName Identifies the SMM register to check for support.
510
511 @retval TRUE The SMM register specified by RegName is supported by the CPU
512 specified by CpuIndex.
513 @retval FALSE The SMM register specified by RegName is not supported by the
514 CPU specified by CpuIndex.
515 **/
516 BOOLEAN
517 EFIAPI
518 SmmCpuFeaturesIsSmmRegisterSupported (
519 IN UINTN CpuIndex,
520 IN SMM_REG_NAME RegName
521 )
522 {
523 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
524 return TRUE;
525 }
526 return FALSE;
527 }
528
529 /**
530 Returns the current value of the SMM register for the specified CPU.
531 If the SMM register is not supported, then 0 is returned.
532
533 @param[in] CpuIndex The index of the CPU to read the SMM register. The
534 value must be between 0 and the NumberOfCpus field in
535 the System Management System Table (SMST).
536 @param[in] RegName Identifies the SMM register to read.
537
538 @return The value of the SMM register specified by RegName from the CPU
539 specified by CpuIndex.
540 **/
541 UINT64
542 EFIAPI
543 SmmCpuFeaturesGetSmmRegister (
544 IN UINTN CpuIndex,
545 IN SMM_REG_NAME RegName
546 )
547 {
548 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
549 return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
550 }
551 return 0;
552 }
553
554 /**
555 Sets the value of an SMM register on a specified CPU.
556 If the SMM register is not supported, then no action is performed.
557
558 @param[in] CpuIndex The index of the CPU to write the SMM register. The
559 value must be between 0 and the NumberOfCpus field in
560 the System Management System Table (SMST).
561 @param[in] RegName Identifies the SMM register to write.
562 registers are read-only.
563 @param[in] Value The value to write to the SMM register.
564 **/
565 VOID
566 EFIAPI
567 SmmCpuFeaturesSetSmmRegister (
568 IN UINTN CpuIndex,
569 IN SMM_REG_NAME RegName,
570 IN UINT64 Value
571 )
572 {
573 if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
574 AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
575 }
576 }
577
578 /**
579 Read an SMM Save State register on the target processor. If this function
580 returns EFI_UNSUPPORTED, then the caller is responsible for reading the
581 SMM Save Sate register.
582
583 @param[in] CpuIndex The index of the CPU to read the SMM Save State. The
584 value must be between 0 and the NumberOfCpus field in
585 the System Management System Table (SMST).
586 @param[in] Register The SMM Save State register to read.
587 @param[in] Width The number of bytes to read from the CPU save state.
588 @param[out] Buffer Upon return, this holds the CPU register value read
589 from the save state.
590
591 @retval EFI_SUCCESS The register was read from Save State.
592 @retval EFI_INVALID_PARAMTER Buffer is NULL.
593 @retval EFI_UNSUPPORTED This function does not support reading Register.
594
595 **/
596 EFI_STATUS
597 EFIAPI
598 SmmCpuFeaturesReadSaveStateRegister (
599 IN UINTN CpuIndex,
600 IN EFI_SMM_SAVE_STATE_REGISTER Register,
601 IN UINTN Width,
602 OUT VOID *Buffer
603 )
604 {
605 return EFI_UNSUPPORTED;
606 }
607
608 /**
609 Writes an SMM Save State register on the target processor. If this function
610 returns EFI_UNSUPPORTED, then the caller is responsible for writing the
611 SMM Save Sate register.
612
613 @param[in] CpuIndex The index of the CPU to write the SMM Save State. The
614 value must be between 0 and the NumberOfCpus field in
615 the System Management System Table (SMST).
616 @param[in] Register The SMM Save State register to write.
617 @param[in] Width The number of bytes to write to the CPU save state.
618 @param[in] Buffer Upon entry, this holds the new CPU register value.
619
620 @retval EFI_SUCCESS The register was written to Save State.
621 @retval EFI_INVALID_PARAMTER Buffer is NULL.
622 @retval EFI_UNSUPPORTED This function does not support writing Register.
623 **/
624 EFI_STATUS
625 EFIAPI
626 SmmCpuFeaturesWriteSaveStateRegister (
627 IN UINTN CpuIndex,
628 IN EFI_SMM_SAVE_STATE_REGISTER Register,
629 IN UINTN Width,
630 IN CONST VOID *Buffer
631 )
632 {
633 return EFI_UNSUPPORTED;
634 }
635
636 /**
637 This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
638 notification is completely processed.
639 **/
640 VOID
641 EFIAPI
642 SmmCpuFeaturesCompleteSmmReadyToLock (
643 VOID
644 )
645 {
646 }
647
648 /**
649 This API provides a method for a CPU to allocate a specific region for storing page tables.
650
651 This API can be called more once to allocate memory for page tables.
652
653 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
654 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
655 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
656 returned.
657
658 This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.
659
660 @param Pages The number of 4 KB pages to allocate.
661
662 @return A pointer to the allocated buffer for page tables.
663 @retval NULL Fail to allocate a specific region for storing page tables,
664 Or there is no preference on where the page tables are allocated in SMRAM.
665
666 **/
667 VOID *
668 EFIAPI
669 SmmCpuFeaturesAllocatePageTableMemory (
670 IN UINTN Pages
671 )
672 {
673 return NULL;
674 }
675