UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   4 # This program and the accompanying materials
   5 # are licensed and made available under the terms and conditions of the BSD License
   6 # which accompanies this distribution.  The full text of the license may be found at
   7 # http://opensource.org/licenses/bsd-license.php.
   8 #
   9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 # Module Name:
  13 #
  14 #   SmiException.S
  15 #
  16 # Abstract:
  17 #
  18 #   Exception handlers used in SM mode
  19 #
  20 #------------------------------------------------------------------------------
  21
  22 ASM_GLOBAL  ASM_PFX(gcStmPsd)
  23
  24 ASM_GLOBAL  ASM_PFX(SmmStmExceptionHandler)
  25 ASM_GLOBAL  ASM_PFX(SmmStmSetup)
  26 ASM_GLOBAL  ASM_PFX(SmmStmTeardown)
  27
  28 .equ  CODE_SEL,             0x38
  29 .equ  DATA_SEL,             0x20
  30 .equ  TR_SEL,               0x40
  31
  32 .equ  MSR_IA32_MISC_ENABLE, 0x1A0
  33 .equ  MSR_EFER,             0x0c0000080
  34 .equ  MSR_EFER_XD,          0x0800
  35
  36     .data
  37
  38 #
  39 # This structure serves as a template for all processors.
  40 #
  41 ASM_PFX(gcStmPsd):
  42             .ascii     "TXTPSSIG"
  43             .word      PSD_SIZE
  44             .word      1              # Version
  45             .long      0              # LocalApicId
  46             .byte      0xF            # Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
  47             .byte      0              # BIOS to STM
  48             .byte      0              # STM to BIOS
  49             .byte      0
  50             .word      CODE_SEL
  51             .word      DATA_SEL
  52             .word      DATA_SEL
  53             .word      DATA_SEL
  54             .word      TR_SEL
  55             .word      0
  56             .quad      0              # SmmCr3
  57             .quad      ASM_PFX(_OnStmSetup)
  58             .quad      ASM_PFX(_OnStmTeardown)
  59             .quad      0              # SmmSmiHandlerRip - SMM guest entrypoint
  60             .quad      0              # SmmSmiHandlerRsp
  61             .quad      0
  62             .long      0
  63             .long      0x80010100     # RequiredStmSmmRevId
  64             .quad      ASM_PFX(_OnException)
  65             .quad      0              # ExceptionStack
  66             .word      DATA_SEL
  67             .word      0x1F           # ExceptionFilter
  68             .long      0
  69             .quad      0
  70             .quad      0              # BiosHwResourceRequirementsPtr
  71             .quad      0              # AcpiRsdp
  72             .byte      0              # PhysicalAddressBits
  73 .equ  PSD_SIZE,  . - ASM_PFX(gcStmPsd)
  74
  75     .text
  76 #------------------------------------------------------------------------------
  77 # SMM Exception handlers
  78 #------------------------------------------------------------------------------
  79
  80 ASM_GLOBAL ASM_PFX(_OnException)
  81 ASM_PFX(_OnException):
  82     movq %rsp, %rcx
  83     subq $0x28, %rsp
  84     call ASM_PFX(SmmStmExceptionHandler)
  85     addq $0x28, %rsp
  86     movl %eax, %ebx
  87     movl $4, %eax
  88     .byte  0xf, 0x1, 0xc1 # VMCALL
  89     jmp .
  90
  91 ASM_GLOBAL ASM_PFX(_OnStmSetup)
  92 ASM_PFX(_OnStmSetup):
  93 #
  94 # Check XD disable bit
  95 #
  96     xorq    %r8, %r8
  97     movabsq $ASM_PFX(gStmXdSupported), %rax
  98     movb    (%rax), %al
  99     cmpb    $0, %al
 100     jz      StmXdDone1
 101     movl    $MSR_IA32_MISC_ENABLE, %ecx
 102     rdmsr
 103     movq    %rdx, %r8                  # save MSR_IA32_MISC_ENABLE[63-32]
 104     testl   $BIT2, %edx                # MSR_IA32_MISC_ENABLE[34]
 105     jz      L13
 106     andw    $0x0FFFB, %dx              # clear XD Disable bit if it is set
 107     wrmsr
 108 L13:
 109     movl    $MSR_EFER, %ecx
 110     rdmsr
 111     orw     $MSR_EFER_XD,%ax            # enable NXE
 112     wrmsr
 113 StmXdDone1:
 114     pushq   %r8
 115
 116   subq $0x20, %rsp
 117   call ASM_PFX(SmmStmSetup)
 118   addq 0x20, %rsp
 119
 120     movabsq $ASM_PFX(gStmXdSupported), %rax
 121     movb    (%rax), %al
 122     cmpb    $0, %al
 123     jz      L14
 124     popq    %rdx                        # get saved MSR_IA32_MISC_ENABLE[63-32]
 125     testl   $BIT2, %edx
 126     jz      L14
 127     movl    $MSR_IA32_MISC_ENABLE, %ecx
 128     rdmsr
 129     orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM
 130     wrmsr
 131 L14:
 132
 133   rsm
 134
 135 ASM_GLOBAL ASM_PFX(_OnStmTeardown)
 136 ASM_PFX(_OnStmTeardown):
 137 #
 138 # Check XD disable bit
 139 #
 140     xorq    %r8, %r8
 141     movabsq $ASM_PFX(gStmXdSupported), %rax
 142     movb    (%rax), %al
 143     cmpb    $0, %al
 144     jz      StmXdDone2
 145     movl    $MSR_IA32_MISC_ENABLE, %ecx
 146     rdmsr
 147     movq    %rdx, %r8                  # save MSR_IA32_MISC_ENABLE[63-32]
 148     testl   $BIT2, %edx                # MSR_IA32_MISC_ENABLE[34]
 149     jz      L15
 150     andw    $0x0FFFB, %dx              # clear XD Disable bit if it is set
 151     wrmsr
 152 L15:
 153     movl    $MSR_EFER, %ecx
 154     rdmsr
 155     orw     $MSR_EFER_XD,%ax            # enable NXE
 156     wrmsr
 157 StmXdDone2:
 158     pushq   %r8
 159
 160   subq $0x20, %rsp
 161   call ASM_PFX(SmmStmTeardown)
 162   addq $0x20, %rsp
 163
 164     movabsq $ASM_PFX(gStmXdSupported), %rax
 165     movb    (%rax), %al
 166     cmpb    $0, %al
 167     jz      L16
 168     popq    %rdx                        # get saved MSR_IA32_MISC_ENABLE[63-32]
 169     testl   $BIT2, %edx
 170     jz      L16
 171     movl    $MSR_IA32_MISC_ENABLE, %ecx
 172     rdmsr
 173     orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM
 174     wrmsr
 175 L16:
 176
 177   rsm
 178