1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 global ASM_PFX(gcStmPsd)
23 extern ASM_PFX(SmmStmExceptionHandler)
24 extern ASM_PFX(SmmStmSetup)
25 extern ASM_PFX(SmmStmTeardown)
26 extern ASM_PFX(gStmXdSupported)
27 extern ASM_PFX(gStmSmiHandlerIdtr)
29 %define MSR_IA32_MISC_ENABLE 0x1A0
30 %define MSR_EFER 0xc0000080
31 %define MSR_EFER_XD 0x800
40 ; This structure serves as a template for all processors.
47 DB 0x0F ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
58 DQ ASM_PFX(OnStmSetup)
59 DQ ASM_PFX(OnStmTeardown)
60 DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
61 DQ 0 ; SmmSmiHandlerRsp
64 DD 0x80010100 ; RequiredStmSmmRevId
65 DQ ASM_PFX(OnException)
68 DW 0x01F ; ExceptionFilter
71 DQ 0 ; BiosHwResourceRequirementsPtr
73 DB 0 ; PhysicalAddressBits
74 PSD_SIZE equ $ - ASM_PFX(gcStmPsd)
78 ;------------------------------------------------------------------------------
79 ; SMM Exception handlers
80 ;------------------------------------------------------------------------------
81 global ASM_PFX(OnException)
85 call ASM_PFX(SmmStmExceptionHandler)
89 DB 0x0f, 0x01, 0x0c1 ; VMCALL
92 global ASM_PFX(OnStmSetup)
95 ; Check XD disable bit
98 mov rax, ASM_PFX(gStmXdSupported)
102 mov ecx, MSR_IA32_MISC_ENABLE
104 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
105 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
107 and dx, 0xFFFB ; clear XD Disable bit if it is set
112 or ax, MSR_EFER_XD ; enable NXE
118 call ASM_PFX(SmmStmSetup)
121 mov rax, ASM_PFX(gStmXdSupported)
125 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
128 mov ecx, MSR_IA32_MISC_ENABLE
130 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
136 global ASM_PFX(OnStmTeardown)
137 ASM_PFX(OnStmTeardown):
139 ; Check XD disable bit
142 mov rax, ASM_PFX(gStmXdSupported)
146 mov ecx, MSR_IA32_MISC_ENABLE
148 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
149 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
151 and dx, 0xFFFB ; clear XD Disable bit if it is set
156 or ax, MSR_EFER_XD ; enable NXE
162 call ASM_PFX(SmmStmTeardown)
165 mov rax, ASM_PFX(gStmXdSupported)
169 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
172 mov ecx, MSR_IA32_MISC_ENABLE
174 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM