UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c

   1 /** @file
   2 Page table manipulation functions for IA-32 processors
   3
   4 Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
   5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
   6
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include "PiSmmCpuDxeSmm.h"
  18
  19 /**
  20   Create PageTable for SMM use.
  21
  22   @return     PageTable Address
  23
  24 **/
  25 UINT32
  26 SmmInitPageTable (
  27   VOID
  28   )
  29 {
  30   UINTN                             PageFaultHandlerHookAddress;
  31   IA32_IDT_GATE_DESCRIPTOR          *IdtEntry;
  32   EFI_STATUS                        Status;
  33
  34   //
  35   // Initialize spin lock
  36   //
  37   InitializeSpinLock (mPFLock);
  38
  39   if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
  40     //
  41     // Set own Page Fault entry instead of the default one, because SMM Profile
  42     // feature depends on IRET instruction to do Single Step
  43     //
  44     PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
  45     IdtEntry  = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;
  46     IdtEntry += EXCEPT_IA32_PAGE_FAULT;
  47     IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;
  48     IdtEntry->Bits.Reserved_0     = 0;
  49     IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;
  50     IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);
  51   } else {
  52     //
  53     // Register SMM Page Fault Handler
  54     //
  55     Status = SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_PAGE_FAULT, SmiPFHandler);
  56     ASSERT_EFI_ERROR (Status);
  57   }
  58
  59   //
  60   // Additional SMM IDT initialization for SMM stack guard
  61   //
  62   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
  63     InitializeIDTSmmStackGuard ();
  64   }
  65   return Gen4GPageTable (TRUE);
  66 }
  67
  68 /**
  69   Page Fault handler for SMM use.
  70
  71 **/
  72 VOID
  73 SmiDefaultPFHandler (
  74   VOID
  75   )
  76 {
  77   CpuDeadLoop ();
  78 }
  79
  80 /**
  81   ThePage Fault handler wrapper for SMM use.
  82
  83   @param  InterruptType    Defines the type of interrupt or exception that
  84                            occurred on the processor.This parameter is processor architecture specific.
  85   @param  SystemContext    A pointer to the processor context when
  86                            the interrupt occurred on the processor.
  87 **/
  88 VOID
  89 EFIAPI
  90 SmiPFHandler (
  91   IN EFI_EXCEPTION_TYPE   InterruptType,
  92   IN EFI_SYSTEM_CONTEXT   SystemContext
  93   )
  94 {
  95   UINTN             PFAddress;
  96   UINTN             GuardPageAddress;
  97   UINTN             CpuIndex;
  98
  99   ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);
 100
 101   AcquireSpinLock (mPFLock);
 102
 103   PFAddress = AsmReadCr2 ();
 104
 105   //
 106   // If a page fault occurs in SMRAM range, it might be in a SMM stack guard page,
 107   // or SMM page protection violation.
 108   //
 109   if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
 110       (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
 111     DumpCpuContext (InterruptType, SystemContext);
 112     CpuIndex = GetCpuIndex ();
 113     GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);
 114     if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
 115         (PFAddress >= GuardPageAddress) &&
 116         (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
 117       DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
 118     } else {
 119       if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
 120         DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress));
 121         DEBUG_CODE (
 122           DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
 123         );
 124       } else {
 125         DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%x)\n", PFAddress));
 126         DEBUG_CODE (
 127           DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
 128         );
 129       }
 130     }
 131     CpuDeadLoop ();
 132   }
 133
 134   //
 135   // If a page fault occurs in SMM range
 136   //
 137   if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
 138       (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
 139     DumpCpuContext (InterruptType, SystemContext);
 140     if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
 141       DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));
 142       DEBUG_CODE (
 143         DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
 144       );
 145       CpuDeadLoop ();
 146     }
 147     if (IsSmmCommBufferForbiddenAddress (PFAddress)) {
 148       DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress));
 149       DEBUG_CODE (
 150         DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
 151       );
 152       CpuDeadLoop ();
 153     }
 154   }
 155
 156   if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
 157     SmmProfilePFHandler (
 158       SystemContext.SystemContextIa32->Eip,
 159       SystemContext.SystemContextIa32->ExceptionData
 160       );
 161   } else {
 162     DumpCpuContext (InterruptType, SystemContext);
 163     SmiDefaultPFHandler ();
 164   }
 165
 166   ReleaseSpinLock (mPFLock);
 167 }
 168
 169 /**
 170   This function sets memory attribute for page table.
 171 **/
 172 VOID
 173 SetPageTableAttributes (
 174   VOID
 175   )
 176 {
 177   UINTN                 Index2;
 178   UINTN                 Index3;
 179   UINT64                *L1PageTable;
 180   UINT64                *L2PageTable;
 181   UINT64                *L3PageTable;
 182   BOOLEAN               IsSplitted;
 183   BOOLEAN               PageTableSplitted;
 184
 185   DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
 186
 187   //
 188   // Disable write protection, because we need mark page table to be write protected.
 189   // We need *write* page table memory, to mark itself to be *read only*.
 190   //
 191   AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
 192
 193   do {
 194     DEBUG ((DEBUG_INFO, "Start...\n"));
 195     PageTableSplitted = FALSE;
 196
 197     L3PageTable = (UINT64 *)GetPageTableBase ();
 198
 199     SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
 200     PageTableSplitted = (PageTableSplitted || IsSplitted);
 201
 202     for (Index3 = 0; Index3 < 4; Index3++) {
 203       L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
 204       if (L2PageTable == NULL) {
 205         continue;
 206       }
 207
 208       SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
 209       PageTableSplitted = (PageTableSplitted || IsSplitted);
 210
 211       for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {
 212         if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
 213           // 2M
 214           continue;
 215         }
 216         L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
 217         if (L1PageTable == NULL) {
 218           continue;
 219         }
 220         SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
 221         PageTableSplitted = (PageTableSplitted || IsSplitted);
 222       }
 223     }
 224   } while (PageTableSplitted);
 225
 226   //
 227   // Enable write protection, after page table updated.
 228   //
 229   AsmWriteCr0 (AsmReadCr0() | CR0_WP);
 230
 231   return ;
 232 }