UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   4 # This program and the accompanying materials
   5 # are licensed and made available under the terms and conditions of the BSD License
   6 # which accompanies this distribution.  The full text of the license may be found at
   7 # http://opensource.org/licenses/bsd-license.php.
   8 #
   9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 # Module Name:
  13 #
  14 #   SmiEntry.S
  15 #
  16 # Abstract:
  17 #
  18 #   Code template of the SMI handler for a particular processor
  19 #
  20 #------------------------------------------------------------------------------
  21
  22 ASM_GLOBAL  ASM_PFX(gcSmiHandlerTemplate)
  23 ASM_GLOBAL  ASM_PFX(gcSmiHandlerSize)
  24 ASM_GLOBAL  ASM_PFX(gSmiCr3)
  25 ASM_GLOBAL  ASM_PFX(gSmiStack)
  26 ASM_GLOBAL  ASM_PFX(gSmbase)
  27 ASM_GLOBAL  ASM_PFX(mXdSupported)
  28 ASM_GLOBAL  ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
  29 ASM_GLOBAL  ASM_PFX(gSmiHandlerIdtr)
  30
  31 .equ            MSR_EFER, 0xc0000080
  32 .equ            MSR_EFER_XD, 0x800
  33
  34 .equ            DSC_OFFSET, 0xfb00
  35 .equ            DSC_GDTPTR, 0x30
  36 .equ            DSC_GDTSIZ, 0x38
  37 .equ            DSC_CS, 14
  38 .equ            DSC_DS, 16
  39 .equ            DSC_SS, 18
  40 .equ            DSC_OTHERSEG, 20
  41
  42 .equ            PROTECT_MODE_CS, 0x08
  43 .equ            PROTECT_MODE_DS, 0x20
  44 .equ            TSS_SEGMENT,     0x40
  45
  46     .text
  47
  48 ASM_PFX(gcSmiHandlerTemplate):
  49
  50 _SmiEntryPoint:
  51     .byte 0xbb                          # mov bx, imm16
  52     .word _GdtDesc - _SmiEntryPoint + 0x8000
  53     .byte 0x2e,0xa1                     # mov ax, cs:[offset16]
  54     .word DSC_OFFSET + DSC_GDTSIZ
  55     decl    %eax
  56     movl    %eax, %cs:(%edi)            # mov cs:[bx], ax
  57     .byte 0x66,0x2e,0xa1                # mov eax, cs:[offset16]
  58     .word   DSC_OFFSET + DSC_GDTPTR
  59     movw    %ax, %cs:2(%edi)
  60     movw    %ax, %bp                    # ebp = GDT base
  61     .byte 0x66
  62     lgdt    %cs:(%edi)
  63 # Patch ProtectedMode Segment
  64     .byte   0xb8                        # mov ax, imm16
  65     .word   PROTECT_MODE_CS             # set AX for segment directly
  66     movl    %eax, %cs:-2(%edi)          # mov cs:[bx - 2], ax
  67 # Patch ProtectedMode entry
  68     .byte 0x66, 0xbf                    # mov edi, SMBASE
  69 ASM_PFX(gSmbase): .space 4
  70     .byte 0x67
  71     lea     ((Start32bit - _SmiEntryPoint) + 0x8000)(%edi), %ax
  72     movw     %ax, %cs:-6(%edi)
  73     movl    %cr0, %ebx
  74     .byte 0x66
  75     andl    $0x9ffafff3, %ebx
  76     .byte 0x66
  77     orl     $0x23, %ebx
  78     movl    %ebx, %cr0
  79     .byte 0x66,0xea
  80     .space  4
  81     .space  2
  82 _GdtDesc:   .space 4
  83             .space 2
  84
  85 Start32bit:
  86     movw    $PROTECT_MODE_DS, %ax
  87     movl    %eax,%ds
  88     movl    %eax,%es
  89     movl    %eax,%fs
  90     movl    %eax,%gs
  91     movl    %eax,%ss
  92     .byte   0xbc                          # mov esp, imm32
  93 ASM_PFX(gSmiStack): .space 4
  94     movl    $ASM_PFX(gSmiHandlerIdtr), %eax
  95     lidt    (%eax)
  96     jmp     ProtFlatMode
  97
  98 ProtFlatMode:
  99     .byte   0xb8                           # mov eax, imm32
 100 ASM_PFX(gSmiCr3): .space 4
 101     movl    %eax, %cr3
 102 #
 103 # Need to test for CR4 specific bit support
 104 #
 105     movl    $1, %eax
 106     cpuid                                  # use CPUID to determine if specific CR4 bits are supported
 107     xorl    %eax, %eax                     # Clear EAX
 108     testl   $BIT2, %edx                    # Check for DE capabilities
 109     jz      L8
 110     orl     $BIT3, %eax
 111 L8:
 112     testl   $BIT6, %edx                    # Check for PAE capabilities
 113     jz      L9
 114     orl     $BIT5, %eax
 115 L9:
 116     testl   $BIT7, %edx                    # Check for MCE capabilities
 117     jz      L10
 118     orl     $BIT6, %eax
 119 L10:
 120     testl   $BIT24, %edx                   # Check for FXSR capabilities
 121     jz      L11
 122     orl     $BIT9, %eax
 123 L11:
 124     testl   $BIT25, %edx                   # Check for SSE capabilities
 125     jz      L12
 126     orl     $BIT10, %eax
 127 L12:                                       # as cr4.PGE is not set here, refresh cr3
 128     movl    %eax, %cr4                     # in PreModifyMtrrs() to flush TLB.
 129
 130     cmpb    $0, ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
 131     jz      L5
 132 # Load TSS
 133     movb    $0x89, (TSS_SEGMENT + 5)(%ebp) # clear busy flag
 134     movl    $TSS_SEGMENT, %eax
 135     ltrw    %ax
 136 L5:
 137
 138 # enable NXE if supported
 139     .byte   0xb0                           # mov al, imm8
 140 ASM_PFX(mXdSupported): .byte 1
 141     cmpb    $0, %al
 142     jz      SkipNxe
 143 #
 144 # Check XD disable bit
 145 #
 146     movl    $MSR_IA32_MISC_ENABLE, %ecx
 147     rdmsr
 148     pushl   %edx                           # save MSR_IA32_MISC_ENABLE[63-32]
 149     testl   $BIT2, %edx                    # MSR_IA32_MISC_ENABLE[34]
 150     jz      L13
 151     andw    $0x0FFFB, %dx                  # clear XD Disable bit if it is set
 152     wrmsr
 153 L13:
 154     movl    $MSR_EFER, %ecx
 155     rdmsr
 156     orw     $MSR_EFER_XD,%ax               # enable NXE
 157     wrmsr
 158 SkipNxe:
 159     subl    $4, %esp
 160 NxeDone:
 161
 162     movl    %cr0, %ebx
 163     orl     $0x080010023, %ebx             # enable paging + WP + NE + MP + PE
 164     movl    %ebx, %cr0
 165     leal    DSC_OFFSET(%edi),%ebx
 166     movw    DSC_DS(%ebx),%ax
 167     movl    %eax, %ds
 168     movw    DSC_OTHERSEG(%ebx),%ax
 169     movl    %eax, %es
 170     movl    %eax, %fs
 171     movl    %eax, %gs
 172     movw    DSC_SS(%ebx),%ax
 173     movl    %eax, %ss
 174
 175 #   jmp     _SmiHandler                 # instruction is not needed
 176
 177 _SmiHandler:
 178     movl    4(%esp), %ebx
 179
 180     pushl   %ebx
 181     movl    $ASM_PFX(CpuSmmDebugEntry), %eax
 182     call    *%eax
 183     addl    $4, %esp
 184
 185     pushl   %ebx
 186     movl    $ASM_PFX(SmiRendezvous), %eax
 187     call    *%eax
 188     addl    $4, %esp
 189
 190     pushl   %ebx
 191     movl    $ASM_PFX(CpuSmmDebugExit), %eax
 192     call    *%eax
 193     addl    $4, %esp
 194
 195     movl    $ASM_PFX(mXdSupported), %eax
 196     movb    (%eax), %al
 197     cmpb    $0, %al
 198     jz      L16
 199     popl    %edx                        # get saved MSR_IA32_MISC_ENABLE[63-32]
 200     testl   $BIT2, %edx
 201     jz      L16
 202     movl    $MSR_IA32_MISC_ENABLE, %ecx
 203     rdmsr
 204     orw     $BIT2, %dx                  # set XD Disable bit if it was set before entering into SMM
 205     wrmsr
 206
 207 L16:
 208     rsm
 209
 210 ASM_PFX(gcSmiHandlerSize):    .word      . - _SmiEntryPoint