UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmiEntry.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Code template of the SMI handler for a particular processor
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 %define DSC_OFFSET 0xfb00
  22 %define DSC_GDTPTR 0x30
  23 %define DSC_GDTSIZ 0x38
  24 %define DSC_CS 14
  25 %define DSC_DS 16
  26 %define DSC_SS 18
  27 %define DSC_OTHERSEG 20
  28
  29 %define PROTECT_MODE_CS 0x8
  30 %define PROTECT_MODE_DS 0x20
  31 %define TSS_SEGMENT 0x40
  32
  33 extern ASM_PFX(SmiRendezvous)
  34 extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
  35 extern ASM_PFX(CpuSmmDebugEntry)
  36 extern ASM_PFX(CpuSmmDebugExit)
  37
  38 global ASM_PFX(gcSmiHandlerTemplate)
  39 global ASM_PFX(gcSmiHandlerSize)
  40 global ASM_PFX(gSmiCr3)
  41 global ASM_PFX(gSmiStack)
  42 global ASM_PFX(gSmbase)
  43 extern ASM_PFX(gSmiHandlerIdtr)
  44
  45     SECTION .text
  46
  47 BITS 16
  48 ASM_PFX(gcSmiHandlerTemplate):
  49 _SmiEntryPoint:
  50     mov     bx, _GdtDesc - _SmiEntryPoint + 0x8000
  51     mov     ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
  52     dec     ax
  53     mov     [cs:bx], ax
  54     mov     eax, [cs:DSC_OFFSET + DSC_GDTPTR]
  55     mov     [cs:bx + 2], eax
  56     mov     ebp, eax                      ; ebp = GDT base
  57 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]
  58     mov     ax, PROTECT_MODE_CS
  59     mov     [cs:bx-0x2],ax
  60     DB      0x66, 0xbf                   ; mov edi, SMBASE
  61 ASM_PFX(gSmbase): DD 0
  62     lea     eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
  63     mov     [cs:bx-0x6],eax
  64     mov     ebx, cr0
  65     and     ebx, 0x9ffafff3
  66     or      ebx, 0x23
  67     mov     cr0, ebx
  68     jmp     dword 0x0:0x0
  69 _GdtDesc:
  70     DW 0
  71     DD 0
  72
  73 BITS 32
  74 @32bit:
  75     mov     ax, PROTECT_MODE_DS
  76 o16 mov     ds, ax
  77 o16 mov     es, ax
  78 o16 mov     fs, ax
  79 o16 mov     gs, ax
  80 o16 mov     ss, ax
  81     DB      0xbc                   ; mov esp, imm32
  82 ASM_PFX(gSmiStack): DD 0
  83     mov     eax, ASM_PFX(gSmiHandlerIdtr)
  84     lidt    [eax]
  85     jmp     ProtFlatMode
  86
  87 ProtFlatMode:
  88     DB      0xb8                        ; mov eax, imm32
  89 ASM_PFX(gSmiCr3): DD 0
  90     mov     cr3, eax
  91 ;
  92 ; Need to test for CR4 specific bit support
  93 ;
  94     mov     eax, 1
  95     cpuid                               ; use CPUID to determine if specific CR4 bits are supported
  96     xor     eax, eax                    ; Clear EAX
  97     test    edx, BIT2                   ; Check for DE capabilities
  98     jz      .0
  99     or      eax, BIT3
 100 .0:
 101     test    edx, BIT6                   ; Check for PAE capabilities
 102     jz      .1
 103     or      eax, BIT5
 104 .1:
 105     test    edx, BIT7                   ; Check for MCE capabilities
 106     jz      .2
 107     or      eax, BIT6
 108 .2:
 109     test    edx, BIT24                  ; Check for FXSR capabilities
 110     jz      .3
 111     or      eax, BIT9
 112 .3:
 113     test    edx, BIT25                  ; Check for SSE capabilities
 114     jz      .4
 115     or      eax, BIT10
 116 .4:                                     ; as cr4.PGE is not set here, refresh cr3
 117     mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.
 118     mov     ebx, cr0
 119     or      ebx, 0x080010000            ; enable paging + WP
 120     mov     cr0, ebx
 121     lea     ebx, [edi + DSC_OFFSET]
 122     mov     ax, [ebx + DSC_DS]
 123     mov     ds, eax
 124     mov     ax, [ebx + DSC_OTHERSEG]
 125     mov     es, eax
 126     mov     fs, eax
 127     mov     gs, eax
 128     mov     ax, [ebx + DSC_SS]
 129     mov     ss, eax
 130
 131     cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
 132     jz      .5
 133
 134 ; Load TSS
 135     mov     byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
 136     mov     eax, TSS_SEGMENT
 137     ltr     ax
 138 .5:
 139 ;   jmp     _SmiHandler                 ; instruction is not needed
 140
 141 global ASM_PFX(SmiHandler)
 142 ASM_PFX(SmiHandler):
 143     mov     ebx, [esp]                  ; CPU Index
 144
 145     push    ebx
 146     mov     eax, ASM_PFX(CpuSmmDebugEntry)
 147     call    eax
 148     pop     ecx
 149
 150     push    ebx
 151     mov     eax, ASM_PFX(SmiRendezvous)
 152     call    eax
 153     pop     ecx
 154
 155     push    ebx
 156     mov     eax, ASM_PFX(CpuSmmDebugExit)
 157     call    eax
 158     pop     ecx
 159
 160     rsm
 161
 162 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
 163