UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmiEntry.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Code template of the SMI handler for a particular processor
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 %define MSR_IA32_MISC_ENABLE 0x1A0
  22 %define MSR_EFER      0xc0000080
  23 %define MSR_EFER_XD   0x800
  24
  25 %define DSC_OFFSET 0xfb00
  26 %define DSC_GDTPTR 0x30
  27 %define DSC_GDTSIZ 0x38
  28 %define DSC_CS 14
  29 %define DSC_DS 16
  30 %define DSC_SS 18
  31 %define DSC_OTHERSEG 20
  32
  33 %define PROTECT_MODE_CS 0x8
  34 %define PROTECT_MODE_DS 0x20
  35 %define TSS_SEGMENT 0x40
  36
  37 extern ASM_PFX(SmiRendezvous)
  38 extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
  39 extern ASM_PFX(CpuSmmDebugEntry)
  40 extern ASM_PFX(CpuSmmDebugExit)
  41
  42 global ASM_PFX(gcSmiHandlerTemplate)
  43 global ASM_PFX(gcSmiHandlerSize)
  44 global ASM_PFX(gSmiCr3)
  45 global ASM_PFX(gSmiStack)
  46 global ASM_PFX(gSmbase)
  47 global ASM_PFX(mXdSupported)
  48 extern ASM_PFX(gSmiHandlerIdtr)
  49
  50     SECTION .text
  51
  52 BITS 16
  53 ASM_PFX(gcSmiHandlerTemplate):
  54 _SmiEntryPoint:
  55     mov     bx, _GdtDesc - _SmiEntryPoint + 0x8000
  56     mov     ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
  57     dec     ax
  58     mov     [cs:bx], ax
  59     mov     eax, [cs:DSC_OFFSET + DSC_GDTPTR]
  60     mov     [cs:bx + 2], eax
  61     mov     ebp, eax                      ; ebp = GDT base
  62 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]
  63     mov     ax, PROTECT_MODE_CS
  64     mov     [cs:bx-0x2],ax
  65     DB      0x66, 0xbf                   ; mov edi, SMBASE
  66 ASM_PFX(gSmbase): DD 0
  67     lea     eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
  68     mov     [cs:bx-0x6],eax
  69     mov     ebx, cr0
  70     and     ebx, 0x9ffafff3
  71     or      ebx, 0x23
  72     mov     cr0, ebx
  73     jmp     dword 0x0:0x0
  74 _GdtDesc:
  75     DW 0
  76     DD 0
  77
  78 BITS 32
  79 @32bit:
  80     mov     ax, PROTECT_MODE_DS
  81 o16 mov     ds, ax
  82 o16 mov     es, ax
  83 o16 mov     fs, ax
  84 o16 mov     gs, ax
  85 o16 mov     ss, ax
  86     DB      0xbc                   ; mov esp, imm32
  87 ASM_PFX(gSmiStack): DD 0
  88     mov     eax, ASM_PFX(gSmiHandlerIdtr)
  89     lidt    [eax]
  90     jmp     ProtFlatMode
  91
  92 ProtFlatMode:
  93     DB      0xb8                        ; mov eax, imm32
  94 ASM_PFX(gSmiCr3): DD 0
  95     mov     cr3, eax
  96 ;
  97 ; Need to test for CR4 specific bit support
  98 ;
  99     mov     eax, 1
 100     cpuid                               ; use CPUID to determine if specific CR4 bits are supported
 101     xor     eax, eax                    ; Clear EAX
 102     test    edx, BIT2                   ; Check for DE capabilities
 103     jz      .0
 104     or      eax, BIT3
 105 .0:
 106     test    edx, BIT6                   ; Check for PAE capabilities
 107     jz      .1
 108     or      eax, BIT5
 109 .1:
 110     test    edx, BIT7                   ; Check for MCE capabilities
 111     jz      .2
 112     or      eax, BIT6
 113 .2:
 114     test    edx, BIT24                  ; Check for FXSR capabilities
 115     jz      .3
 116     or      eax, BIT9
 117 .3:
 118     test    edx, BIT25                  ; Check for SSE capabilities
 119     jz      .4
 120     or      eax, BIT10
 121 .4:                                     ; as cr4.PGE is not set here, refresh cr3
 122     mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.
 123
 124     cmp     byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
 125     jz      .6
 126 ; Load TSS
 127     mov     byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
 128     mov     eax, TSS_SEGMENT
 129     ltr     ax
 130 .6:
 131
 132 ; enable NXE if supported
 133     DB      0b0h                        ; mov al, imm8
 134 ASM_PFX(mXdSupported):     DB      1
 135     cmp     al, 0
 136     jz      @SkipXd
 137 ;
 138 ; Check XD disable bit
 139 ;
 140     mov     ecx, MSR_IA32_MISC_ENABLE
 141     rdmsr
 142     push    edx                        ; save MSR_IA32_MISC_ENABLE[63-32]
 143     test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]
 144     jz      .5
 145     and     dx, 0xFFFB                 ; clear XD Disable bit if it is set
 146     wrmsr
 147 .5:
 148     mov     ecx, MSR_EFER
 149     rdmsr
 150     or      ax, MSR_EFER_XD             ; enable NXE
 151     wrmsr
 152     jmp     @XdDone
 153 @SkipXd:
 154     sub     esp, 4
 155 @XdDone:
 156
 157     mov     ebx, cr0
 158     or      ebx, 0x80010023             ; enable paging + WP + NE + MP + PE
 159     mov     cr0, ebx
 160     lea     ebx, [edi + DSC_OFFSET]
 161     mov     ax, [ebx + DSC_DS]
 162     mov     ds, eax
 163     mov     ax, [ebx + DSC_OTHERSEG]
 164     mov     es, eax
 165     mov     fs, eax
 166     mov     gs, eax
 167     mov     ax, [ebx + DSC_SS]
 168     mov     ss, eax
 169
 170 ;   jmp     _SmiHandler                 ; instruction is not needed
 171
 172 global ASM_PFX(SmiHandler)
 173 ASM_PFX(SmiHandler):
 174     mov     ebx, [esp + 4]                  ; CPU Index
 175     push    ebx
 176     mov     eax, ASM_PFX(CpuSmmDebugEntry)
 177     call    eax
 178     add     esp, 4
 179
 180     push    ebx
 181     mov     eax, ASM_PFX(SmiRendezvous)
 182     call    eax
 183     add     esp, 4
 184
 185     push    ebx
 186     mov     eax, ASM_PFX(CpuSmmDebugExit)
 187     call    eax
 188     add     esp, 4
 189
 190     mov     eax, ASM_PFX(mXdSupported)
 191     mov     al, [eax]
 192     cmp     al, 0
 193     jz      .7
 194     pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]
 195     test    edx, BIT2
 196     jz      .7
 197     mov     ecx, MSR_IA32_MISC_ENABLE
 198     rdmsr
 199     or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM
 200     wrmsr
 201
 202 .7:
 203     rsm
 204
 205 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
 206