UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   4 ;
   5 ; Module Name:
   6 ;
   7 ;   SmmInit.nasm
   8 ;
   9 ; Abstract:
  10 ;
  11 ;   Functions for relocating SMBASE's for all processors
  12 ;
  13 ;-------------------------------------------------------------------------------
  14
  15 %include "StuffRsbNasm.inc"
  16
  17 extern ASM_PFX(SmmInitHandler)
  18 extern ASM_PFX(mRebasedFlag)
  19 extern ASM_PFX(mSmmRelocationOriginalAddress)
  20
  21 global ASM_PFX(gPatchSmmCr3)
  22 global ASM_PFX(gPatchSmmCr4)
  23 global ASM_PFX(gPatchSmmCr0)
  24 global ASM_PFX(gPatchSmmInitStack)
  25 global ASM_PFX(gcSmiInitGdtr)
  26 global ASM_PFX(gcSmmInitSize)
  27 global ASM_PFX(gcSmmInitTemplate)
  28
  29 %define PROTECT_MODE_CS 0x8
  30 %define PROTECT_MODE_DS 0x20
  31
  32     SECTION .text
  33
  34 ASM_PFX(gcSmiInitGdtr):
  35             DW      0
  36             DQ      0
  37
  38 global ASM_PFX(SmmStartup)
  39
  40 BITS 16
  41 ASM_PFX(SmmStartup):
  42     mov     eax, 0x80000001             ; read capability
  43     cpuid
  44     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.
  45     and     ebx, BIT20                  ; extract NX capability bit
  46     shr     ebx, 9                      ; shift bit to IA32_EFER.NXE[BIT11] position
  47     mov     eax, strict dword 0         ; source operand will be patched
  48 ASM_PFX(gPatchSmmCr3):
  49     mov     cr3, eax
  50 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
  51     mov     eax, strict dword 0         ; source operand will be patched
  52 ASM_PFX(gPatchSmmCr4):
  53     mov     cr4, eax
  54     mov     ecx, 0xc0000080             ; IA32_EFER MSR
  55     rdmsr
  56     or      eax, ebx                    ; set NXE bit if NX is available
  57     wrmsr
  58     mov     eax, strict dword 0         ; source operand will be patched
  59 ASM_PFX(gPatchSmmCr0):
  60     mov     di, PROTECT_MODE_DS
  61     mov     cr0, eax
  62     jmp     PROTECT_MODE_CS : dword @32bit
  63
  64 BITS 32
  65 @32bit:
  66     mov     ds, edi
  67     mov     es, edi
  68     mov     fs, edi
  69     mov     gs, edi
  70     mov     ss, edi
  71     mov     esp, strict dword 0         ; source operand will be patched
  72 ASM_PFX(gPatchSmmInitStack):
  73     call    ASM_PFX(SmmInitHandler)
  74     StuffRsb32
  75     rsm
  76
  77 BITS 16
  78 ASM_PFX(gcSmmInitTemplate):
  79     mov ebp, ASM_PFX(SmmStartup)
  80     sub ebp, 0x30000
  81     jmp ebp
  82
  83 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
  84
  85 BITS 32
  86 global ASM_PFX(SmmRelocationSemaphoreComplete)
  87 ASM_PFX(SmmRelocationSemaphoreComplete):
  88     push    eax
  89     mov     eax, [ASM_PFX(mRebasedFlag)]
  90     mov     byte [eax], 1
  91     pop     eax
  92     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]
  93
  94 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
  95 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
  96     ret