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UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / MpService.c
1 /** @file
2 SMM MP service implementation
3
4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
6
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #include "PiSmmCpuDxeSmm.h"
18
19 //
20 // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
21 //
22 MTRR_SETTINGS gSmiMtrrs;
23 UINT64 gPhyMask;
24 SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
25 UINTN mSmmMpSyncDataSize;
26 SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
27 UINTN mSemaphoreSize;
28 SPIN_LOCK *mPFLock = NULL;
29 SMM_CPU_SYNC_MODE mCpuSmmSyncMode;
30
31 /**
32 Performs an atomic compare exchange operation to get semaphore.
33 The compare exchange operation must be performed using
34 MP safe mechanisms.
35
36 @param Sem IN: 32-bit unsigned integer
37 OUT: original integer - 1
38 @return Original integer - 1
39
40 **/
41 UINT32
42 WaitForSemaphore (
43 IN OUT volatile UINT32 *Sem
44 )
45 {
46 UINT32 Value;
47
48 do {
49 Value = *Sem;
50 } while (Value == 0 ||
51 InterlockedCompareExchange32 (
52 (UINT32*)Sem,
53 Value,
54 Value - 1
55 ) != Value);
56 return Value - 1;
57 }
58
59
60 /**
61 Performs an atomic compare exchange operation to release semaphore.
62 The compare exchange operation must be performed using
63 MP safe mechanisms.
64
65 @param Sem IN: 32-bit unsigned integer
66 OUT: original integer + 1
67 @return Original integer + 1
68
69 **/
70 UINT32
71 ReleaseSemaphore (
72 IN OUT volatile UINT32 *Sem
73 )
74 {
75 UINT32 Value;
76
77 do {
78 Value = *Sem;
79 } while (Value + 1 != 0 &&
80 InterlockedCompareExchange32 (
81 (UINT32*)Sem,
82 Value,
83 Value + 1
84 ) != Value);
85 return Value + 1;
86 }
87
88 /**
89 Performs an atomic compare exchange operation to lock semaphore.
90 The compare exchange operation must be performed using
91 MP safe mechanisms.
92
93 @param Sem IN: 32-bit unsigned integer
94 OUT: -1
95 @return Original integer
96
97 **/
98 UINT32
99 LockdownSemaphore (
100 IN OUT volatile UINT32 *Sem
101 )
102 {
103 UINT32 Value;
104
105 do {
106 Value = *Sem;
107 } while (InterlockedCompareExchange32 (
108 (UINT32*)Sem,
109 Value, (UINT32)-1
110 ) != Value);
111 return Value;
112 }
113
114 /**
115 Wait all APs to performs an atomic compare exchange operation to release semaphore.
116
117 @param NumberOfAPs AP number
118
119 **/
120 VOID
121 WaitForAllAPs (
122 IN UINTN NumberOfAPs
123 )
124 {
125 UINTN BspIndex;
126
127 BspIndex = mSmmMpSyncData->BspIndex;
128 while (NumberOfAPs-- > 0) {
129 WaitForSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
130 }
131 }
132
133 /**
134 Performs an atomic compare exchange operation to release semaphore
135 for each AP.
136
137 **/
138 VOID
139 ReleaseAllAPs (
140 VOID
141 )
142 {
143 UINTN Index;
144 UINTN BspIndex;
145
146 BspIndex = mSmmMpSyncData->BspIndex;
147 for (Index = mMaxNumberOfCpus; Index-- > 0;) {
148 if (Index != BspIndex && *(mSmmMpSyncData->CpuData[Index].Present)) {
149 ReleaseSemaphore (mSmmMpSyncData->CpuData[Index].Run);
150 }
151 }
152 }
153
154 /**
155 Checks if all CPUs (with certain exceptions) have checked in for this SMI run
156
157 @param Exceptions CPU Arrival exception flags.
158
159 @retval TRUE if all CPUs the have checked in.
160 @retval FALSE if at least one Normal AP hasn't checked in.
161
162 **/
163 BOOLEAN
164 AllCpusInSmmWithExceptions (
165 SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions
166 )
167 {
168 UINTN Index;
169 SMM_CPU_DATA_BLOCK *CpuData;
170 EFI_PROCESSOR_INFORMATION *ProcessorInfo;
171
172 ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
173
174 if (*mSmmMpSyncData->Counter == mNumberOfCpus) {
175 return TRUE;
176 }
177
178 CpuData = mSmmMpSyncData->CpuData;
179 ProcessorInfo = gSmmCpuPrivate->ProcessorInfo;
180 for (Index = mMaxNumberOfCpus; Index-- > 0;) {
181 if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
182 if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) {
183 continue;
184 }
185 if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0) {
186 continue;
187 }
188 if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0) {
189 continue;
190 }
191 return FALSE;
192 }
193 }
194
195
196 return TRUE;
197 }
198
199
200 /**
201 Given timeout constraint, wait for all APs to arrive, and insure when this function returns, no AP will execute normal mode code before
202 entering SMM, except SMI disabled APs.
203
204 **/
205 VOID
206 SmmWaitForApArrival (
207 VOID
208 )
209 {
210 UINT64 Timer;
211 UINTN Index;
212
213 ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
214
215 //
216 // Platform implementor should choose a timeout value appropriately:
217 // - The timeout value should balance the SMM time constrains and the likelihood that delayed CPUs are excluded in the SMM run. Note
218 // the SMI Handlers must ALWAYS take into account the cases that not all APs are available in an SMI run.
219 // - The timeout value must, in the case of 2nd timeout, be at least long enough to give time for all APs to receive the SMI IPI
220 // and either enter SMM or buffer the SMI, to insure there is no CPU running normal mode code when SMI handling starts. This will
221 // be TRUE even if a blocked CPU is brought out of the blocked state by a normal mode CPU (before the normal mode CPU received the
222 // SMI IPI), because with a buffered SMI, and CPU will enter SMM immediately after it is brought out of the blocked state.
223 // - The timeout value must be longer than longest possible IO operation in the system
224 //
225
226 //
227 // Sync with APs 1st timeout
228 //
229 for (Timer = StartSyncTimer ();
230 !IsSyncTimerTimeout (Timer) &&
231 !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED );
232 ) {
233 CpuPause ();
234 }
235
236 //
237 // Not all APs have arrived, so we need 2nd round of timeout. IPIs should be sent to ALL none present APs,
238 // because:
239 // a) Delayed AP may have just come out of the delayed state. Blocked AP may have just been brought out of blocked state by some AP running
240 // normal mode code. These APs need to be guaranteed to have an SMI pending to insure that once they are out of delayed / blocked state, they
241 // enter SMI immediately without executing instructions in normal mode. Note traditional flow requires there are no APs doing normal mode
242 // work while SMI handling is on-going.
243 // b) As a consequence of SMI IPI sending, (spurious) SMI may occur after this SMM run.
244 // c) ** NOTE **: Use SMI disabling feature VERY CAREFULLY (if at all) for traditional flow, because a processor in SMI-disabled state
245 // will execute normal mode code, which breaks the traditional SMI handlers' assumption that no APs are doing normal
246 // mode work while SMI handling is on-going.
247 // d) We don't add code to check SMI disabling status to skip sending IPI to SMI disabled APs, because:
248 // - In traditional flow, SMI disabling is discouraged.
249 // - In relaxed flow, CheckApArrival() will check SMI disabling status before calling this function.
250 // In both cases, adding SMI-disabling checking code increases overhead.
251 //
252 if (*mSmmMpSyncData->Counter < mNumberOfCpus) {
253 //
254 // Send SMI IPIs to bring outside processors in
255 //
256 for (Index = mMaxNumberOfCpus; Index-- > 0;) {
257 if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
258 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
259 }
260 }
261
262 //
263 // Sync with APs 2nd timeout.
264 //
265 for (Timer = StartSyncTimer ();
266 !IsSyncTimerTimeout (Timer) &&
267 !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED );
268 ) {
269 CpuPause ();
270 }
271 }
272
273 return;
274 }
275
276
277 /**
278 Replace OS MTRR's with SMI MTRR's.
279
280 @param CpuIndex Processor Index
281
282 **/
283 VOID
284 ReplaceOSMtrrs (
285 IN UINTN CpuIndex
286 )
287 {
288 SmmCpuFeaturesDisableSmrr ();
289
290 //
291 // Replace all MTRRs registers
292 //
293 MtrrSetAllMtrrs (&gSmiMtrrs);
294 }
295
296 /**
297 SMI handler for BSP.
298
299 @param CpuIndex BSP processor Index
300 @param SyncMode SMM MP sync mode
301
302 **/
303 VOID
304 BSPHandler (
305 IN UINTN CpuIndex,
306 IN SMM_CPU_SYNC_MODE SyncMode
307 )
308 {
309 UINTN Index;
310 MTRR_SETTINGS Mtrrs;
311 UINTN ApCount;
312 BOOLEAN ClearTopLevelSmiResult;
313 UINTN PresentCount;
314
315 ASSERT (CpuIndex == mSmmMpSyncData->BspIndex);
316 ApCount = 0;
317
318 //
319 // Flag BSP's presence
320 //
321 *mSmmMpSyncData->InsideSmm = TRUE;
322
323 //
324 // Initialize Debug Agent to start source level debug in BSP handler
325 //
326 InitializeDebugAgent (DEBUG_AGENT_INIT_ENTER_SMI, NULL, NULL);
327
328 //
329 // Mark this processor's presence
330 //
331 *(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
332
333 //
334 // Clear platform top level SMI status bit before calling SMI handlers. If
335 // we cleared it after SMI handlers are run, we would miss the SMI that
336 // occurs after SMI handlers are done and before SMI status bit is cleared.
337 //
338 ClearTopLevelSmiResult = ClearTopLevelSmiStatus();
339 ASSERT (ClearTopLevelSmiResult == TRUE);
340
341 //
342 // Set running processor index
343 //
344 gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu = CpuIndex;
345
346 //
347 // If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
348 //
349 if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {
350
351 //
352 // Wait for APs to arrive
353 //
354 SmmWaitForApArrival();
355
356 //
357 // Lock the counter down and retrieve the number of APs
358 //
359 *mSmmMpSyncData->AllCpusInSync = TRUE;
360 ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
361
362 //
363 // Wait for all APs to get ready for programming MTRRs
364 //
365 WaitForAllAPs (ApCount);
366
367 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
368 //
369 // Signal all APs it's time for backup MTRRs
370 //
371 ReleaseAllAPs ();
372
373 //
374 // WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
375 // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
376 // to a large enough value to avoid this situation.
377 // Note: For HT capable CPUs, threads within a core share the same set of MTRRs.
378 // We do the backup first and then set MTRR to avoid race condition for threads
379 // in the same core.
380 //
381 MtrrGetAllMtrrs(&Mtrrs);
382
383 //
384 // Wait for all APs to complete their MTRR saving
385 //
386 WaitForAllAPs (ApCount);
387
388 //
389 // Let all processors program SMM MTRRs together
390 //
391 ReleaseAllAPs ();
392
393 //
394 // WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
395 // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
396 // to a large enough value to avoid this situation.
397 //
398 ReplaceOSMtrrs (CpuIndex);
399
400 //
401 // Wait for all APs to complete their MTRR programming
402 //
403 WaitForAllAPs (ApCount);
404 }
405 }
406
407 //
408 // The BUSY lock is initialized to Acquired state
409 //
410 AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[CpuIndex].Busy);
411
412 //
413 // Perform the pre tasks
414 //
415 PerformPreTasks ();
416
417 //
418 // Invoke SMM Foundation EntryPoint with the processor information context.
419 //
420 gSmmCpuPrivate->SmmCoreEntry (&gSmmCpuPrivate->SmmCoreEntryContext);
421
422 //
423 // Make sure all APs have completed their pending none-block tasks
424 //
425 for (Index = mMaxNumberOfCpus; Index-- > 0;) {
426 if (Index != CpuIndex && *(mSmmMpSyncData->CpuData[Index].Present)) {
427 AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
428 ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
429 }
430 }
431
432 //
433 // Perform the remaining tasks
434 //
435 PerformRemainingTasks ();
436
437 //
438 // If Relaxed-AP Sync Mode: gather all available APs after BSP SMM handlers are done, and
439 // make those APs to exit SMI synchronously. APs which arrive later will be excluded and
440 // will run through freely.
441 //
442 if (SyncMode != SmmCpuSyncModeTradition && !SmmCpuFeaturesNeedConfigureMtrrs()) {
443
444 //
445 // Lock the counter down and retrieve the number of APs
446 //
447 *mSmmMpSyncData->AllCpusInSync = TRUE;
448 ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
449 //
450 // Make sure all APs have their Present flag set
451 //
452 while (TRUE) {
453 PresentCount = 0;
454 for (Index = mMaxNumberOfCpus; Index-- > 0;) {
455 if (*(mSmmMpSyncData->CpuData[Index].Present)) {
456 PresentCount ++;
457 }
458 }
459 if (PresentCount > ApCount) {
460 break;
461 }
462 }
463 }
464
465 //
466 // Notify all APs to exit
467 //
468 *mSmmMpSyncData->InsideSmm = FALSE;
469 ReleaseAllAPs ();
470
471 //
472 // Wait for all APs to complete their pending tasks
473 //
474 WaitForAllAPs (ApCount);
475
476 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
477 //
478 // Signal APs to restore MTRRs
479 //
480 ReleaseAllAPs ();
481
482 //
483 // Restore OS MTRRs
484 //
485 SmmCpuFeaturesReenableSmrr ();
486 MtrrSetAllMtrrs(&Mtrrs);
487
488 //
489 // Wait for all APs to complete MTRR programming
490 //
491 WaitForAllAPs (ApCount);
492 }
493
494 //
495 // Stop source level debug in BSP handler, the code below will not be
496 // debugged.
497 //
498 InitializeDebugAgent (DEBUG_AGENT_INIT_EXIT_SMI, NULL, NULL);
499
500 //
501 // Signal APs to Reset states/semaphore for this processor
502 //
503 ReleaseAllAPs ();
504
505 //
506 // Perform pending operations for hot-plug
507 //
508 SmmCpuUpdate ();
509
510 //
511 // Clear the Present flag of BSP
512 //
513 *(mSmmMpSyncData->CpuData[CpuIndex].Present) = FALSE;
514
515 //
516 // Gather APs to exit SMM synchronously. Note the Present flag is cleared by now but
517 // WaitForAllAps does not depend on the Present flag.
518 //
519 WaitForAllAPs (ApCount);
520
521 //
522 // Reset BspIndex to -1, meaning BSP has not been elected.
523 //
524 if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) {
525 mSmmMpSyncData->BspIndex = (UINT32)-1;
526 }
527
528 //
529 // Allow APs to check in from this point on
530 //
531 *mSmmMpSyncData->Counter = 0;
532 *mSmmMpSyncData->AllCpusInSync = FALSE;
533 }
534
535 /**
536 SMI handler for AP.
537
538 @param CpuIndex AP processor Index.
539 @param ValidSmi Indicates that current SMI is a valid SMI or not.
540 @param SyncMode SMM MP sync mode.
541
542 **/
543 VOID
544 APHandler (
545 IN UINTN CpuIndex,
546 IN BOOLEAN ValidSmi,
547 IN SMM_CPU_SYNC_MODE SyncMode
548 )
549 {
550 UINT64 Timer;
551 UINTN BspIndex;
552 MTRR_SETTINGS Mtrrs;
553
554 //
555 // Timeout BSP
556 //
557 for (Timer = StartSyncTimer ();
558 !IsSyncTimerTimeout (Timer) &&
559 !(*mSmmMpSyncData->InsideSmm);
560 ) {
561 CpuPause ();
562 }
563
564 if (!(*mSmmMpSyncData->InsideSmm)) {
565 //
566 // BSP timeout in the first round
567 //
568 if (mSmmMpSyncData->BspIndex != -1) {
569 //
570 // BSP Index is known
571 //
572 BspIndex = mSmmMpSyncData->BspIndex;
573 ASSERT (CpuIndex != BspIndex);
574
575 //
576 // Send SMI IPI to bring BSP in
577 //
578 SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[BspIndex].ProcessorId);
579
580 //
581 // Now clock BSP for the 2nd time
582 //
583 for (Timer = StartSyncTimer ();
584 !IsSyncTimerTimeout (Timer) &&
585 !(*mSmmMpSyncData->InsideSmm);
586 ) {
587 CpuPause ();
588 }
589
590 if (!(*mSmmMpSyncData->InsideSmm)) {
591 //
592 // Give up since BSP is unable to enter SMM
593 // and signal the completion of this AP
594 WaitForSemaphore (mSmmMpSyncData->Counter);
595 return;
596 }
597 } else {
598 //
599 // Don't know BSP index. Give up without sending IPI to BSP.
600 //
601 WaitForSemaphore (mSmmMpSyncData->Counter);
602 return;
603 }
604 }
605
606 //
607 // BSP is available
608 //
609 BspIndex = mSmmMpSyncData->BspIndex;
610 ASSERT (CpuIndex != BspIndex);
611
612 //
613 // Mark this processor's presence
614 //
615 *(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
616
617 if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {
618 //
619 // Notify BSP of arrival at this point
620 //
621 ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
622 }
623
624 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
625 //
626 // Wait for the signal from BSP to backup MTRRs
627 //
628 WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
629
630 //
631 // Backup OS MTRRs
632 //
633 MtrrGetAllMtrrs(&Mtrrs);
634
635 //
636 // Signal BSP the completion of this AP
637 //
638 ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
639
640 //
641 // Wait for BSP's signal to program MTRRs
642 //
643 WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
644
645 //
646 // Replace OS MTRRs with SMI MTRRs
647 //
648 ReplaceOSMtrrs (CpuIndex);
649
650 //
651 // Signal BSP the completion of this AP
652 //
653 ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
654 }
655
656 while (TRUE) {
657 //
658 // Wait for something to happen
659 //
660 WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
661
662 //
663 // Check if BSP wants to exit SMM
664 //
665 if (!(*mSmmMpSyncData->InsideSmm)) {
666 break;
667 }
668
669 //
670 // BUSY should be acquired by SmmStartupThisAp()
671 //
672 ASSERT (
673 !AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[CpuIndex].Busy)
674 );
675
676 //
677 // Invoke the scheduled procedure
678 //
679 (*mSmmMpSyncData->CpuData[CpuIndex].Procedure) (
680 (VOID*)mSmmMpSyncData->CpuData[CpuIndex].Parameter
681 );
682
683 //
684 // Release BUSY
685 //
686 ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
687 }
688
689 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
690 //
691 // Notify BSP the readiness of this AP to program MTRRs
692 //
693 ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
694
695 //
696 // Wait for the signal from BSP to program MTRRs
697 //
698 WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
699
700 //
701 // Restore OS MTRRs
702 //
703 SmmCpuFeaturesReenableSmrr ();
704 MtrrSetAllMtrrs(&Mtrrs);
705 }
706
707 //
708 // Notify BSP the readiness of this AP to Reset states/semaphore for this processor
709 //
710 ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
711
712 //
713 // Wait for the signal from BSP to Reset states/semaphore for this processor
714 //
715 WaitForSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
716
717 //
718 // Reset states/semaphore for this processor
719 //
720 *(mSmmMpSyncData->CpuData[CpuIndex].Present) = FALSE;
721
722 //
723 // Notify BSP the readiness of this AP to exit SMM
724 //
725 ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
726
727 }
728
729 /**
730 Create 4G PageTable in SMRAM.
731
732 @param[in] Is32BitPageTable Whether the page table is 32-bit PAE
733 @return PageTable Address
734
735 **/
736 UINT32
737 Gen4GPageTable (
738 IN BOOLEAN Is32BitPageTable
739 )
740 {
741 VOID *PageTable;
742 UINTN Index;
743 UINT64 *Pte;
744 UINTN PagesNeeded;
745 UINTN Low2MBoundary;
746 UINTN High2MBoundary;
747 UINTN Pages;
748 UINTN GuardPage;
749 UINT64 *Pdpte;
750 UINTN PageIndex;
751 UINTN PageAddress;
752
753 Low2MBoundary = 0;
754 High2MBoundary = 0;
755 PagesNeeded = 0;
756 if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
757 //
758 // Add one more page for known good stack, then find the lower 2MB aligned address.
759 //
760 Low2MBoundary = (mSmmStackArrayBase + EFI_PAGE_SIZE) & ~(SIZE_2MB-1);
761 //
762 // Add two more pages for known good stack and stack guard page,
763 // then find the lower 2MB aligned address.
764 //
765 High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1);
766 PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;
767 }
768 //
769 // Allocate the page table
770 //
771 PageTable = AllocatePageTableMemory (5 + PagesNeeded);
772 ASSERT (PageTable != NULL);
773
774 PageTable = (VOID *)((UINTN)PageTable);
775 Pte = (UINT64*)PageTable;
776
777 //
778 // Zero out all page table entries first
779 //
780 ZeroMem (Pte, EFI_PAGES_TO_SIZE (1));
781
782 //
783 // Set Page Directory Pointers
784 //
785 for (Index = 0; Index < 4; Index++) {
786 Pte[Index] = (UINT64)((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask |
787 (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
788 }
789 Pte += EFI_PAGE_SIZE / sizeof (*Pte);
790
791 //
792 // Fill in Page Directory Entries
793 //
794 for (Index = 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) {
795 Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;
796 }
797
798 if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
799 Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);
800 GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE;
801 Pdpte = (UINT64*)PageTable;
802 for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {
803 Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
804 Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
805 //
806 // Fill in Page Table Entries
807 //
808 Pte = (UINT64*)Pages;
809 PageAddress = PageIndex;
810 for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
811 if (PageAddress == GuardPage) {
812 //
813 // Mark the guard page as non-present
814 //
815 Pte[Index] = PageAddress | mAddressEncMask;
816 GuardPage += mSmmStackSize;
817 if (GuardPage > mSmmStackArrayEnd) {
818 GuardPage = 0;
819 }
820 } else {
821 Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
822 }
823 PageAddress+= EFI_PAGE_SIZE;
824 }
825 Pages += EFI_PAGE_SIZE;
826 }
827 }
828
829 return (UINT32)(UINTN)PageTable;
830 }
831
832 /**
833 Schedule a procedure to run on the specified CPU.
834
835 @param[in] Procedure The address of the procedure to run
836 @param[in] CpuIndex Target CPU Index
837 @param[in, out] ProcArguments The parameter to pass to the procedure
838 @param[in] BlockingMode Startup AP in blocking mode or not
839
840 @retval EFI_INVALID_PARAMETER CpuNumber not valid
841 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
842 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
843 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
844 @retval EFI_SUCCESS The procedure has been successfully scheduled
845
846 **/
847 EFI_STATUS
848 InternalSmmStartupThisAp (
849 IN EFI_AP_PROCEDURE Procedure,
850 IN UINTN CpuIndex,
851 IN OUT VOID *ProcArguments OPTIONAL,
852 IN BOOLEAN BlockingMode
853 )
854 {
855 if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) {
856 DEBUG((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
857 return EFI_INVALID_PARAMETER;
858 }
859 if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
860 DEBUG((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));
861 return EFI_INVALID_PARAMETER;
862 }
863 if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
864 if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) {
865 DEBUG((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));
866 }
867 return EFI_INVALID_PARAMETER;
868 }
869 if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) {
870 if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {
871 DEBUG((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));
872 }
873 return EFI_INVALID_PARAMETER;
874 }
875
876 if (BlockingMode) {
877 AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
878 } else {
879 if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[CpuIndex].Busy)) {
880 DEBUG((DEBUG_ERROR, "mSmmMpSyncData->CpuData[%d].Busy\n", CpuIndex));
881 return EFI_INVALID_PARAMETER;
882 }
883 }
884
885 mSmmMpSyncData->CpuData[CpuIndex].Procedure = Procedure;
886 mSmmMpSyncData->CpuData[CpuIndex].Parameter = ProcArguments;
887 ReleaseSemaphore (mSmmMpSyncData->CpuData[CpuIndex].Run);
888
889 if (BlockingMode) {
890 AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
891 ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
892 }
893 return EFI_SUCCESS;
894 }
895
896 /**
897 Schedule a procedure to run on the specified CPU in blocking mode.
898
899 @param[in] Procedure The address of the procedure to run
900 @param[in] CpuIndex Target CPU Index
901 @param[in, out] ProcArguments The parameter to pass to the procedure
902
903 @retval EFI_INVALID_PARAMETER CpuNumber not valid
904 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
905 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
906 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
907 @retval EFI_SUCCESS The procedure has been successfully scheduled
908
909 **/
910 EFI_STATUS
911 EFIAPI
912 SmmBlockingStartupThisAp (
913 IN EFI_AP_PROCEDURE Procedure,
914 IN UINTN CpuIndex,
915 IN OUT VOID *ProcArguments OPTIONAL
916 )
917 {
918 return InternalSmmStartupThisAp(Procedure, CpuIndex, ProcArguments, TRUE);
919 }
920
921 /**
922 Schedule a procedure to run on the specified CPU.
923
924 @param Procedure The address of the procedure to run
925 @param CpuIndex Target CPU Index
926 @param ProcArguments The parameter to pass to the procedure
927
928 @retval EFI_INVALID_PARAMETER CpuNumber not valid
929 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
930 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
931 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
932 @retval EFI_SUCCESS The procedure has been successfully scheduled
933
934 **/
935 EFI_STATUS
936 EFIAPI
937 SmmStartupThisAp (
938 IN EFI_AP_PROCEDURE Procedure,
939 IN UINTN CpuIndex,
940 IN OUT VOID *ProcArguments OPTIONAL
941 )
942 {
943 return InternalSmmStartupThisAp(Procedure, CpuIndex, ProcArguments, FeaturePcdGet (PcdCpuSmmBlockStartupThisAp));
944 }
945
946 /**
947 This function sets DR6 & DR7 according to SMM save state, before running SMM C code.
948 They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.
949
950 NOTE: It might not be appreciated in runtime since it might
951 conflict with OS debugging facilities. Turn them off in RELEASE.
952
953 @param CpuIndex CPU Index
954
955 **/
956 VOID
957 EFIAPI
958 CpuSmmDebugEntry (
959 IN UINTN CpuIndex
960 )
961 {
962 SMRAM_SAVE_STATE_MAP *CpuSaveState;
963
964 if (FeaturePcdGet (PcdCpuSmmDebug)) {
965 ASSERT(CpuIndex < mMaxNumberOfCpus);
966 CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
967 if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
968 AsmWriteDr6 (CpuSaveState->x86._DR6);
969 AsmWriteDr7 (CpuSaveState->x86._DR7);
970 } else {
971 AsmWriteDr6 ((UINTN)CpuSaveState->x64._DR6);
972 AsmWriteDr7 ((UINTN)CpuSaveState->x64._DR7);
973 }
974 }
975 }
976
977 /**
978 This function restores DR6 & DR7 to SMM save state.
979
980 NOTE: It might not be appreciated in runtime since it might
981 conflict with OS debugging facilities. Turn them off in RELEASE.
982
983 @param CpuIndex CPU Index
984
985 **/
986 VOID
987 EFIAPI
988 CpuSmmDebugExit (
989 IN UINTN CpuIndex
990 )
991 {
992 SMRAM_SAVE_STATE_MAP *CpuSaveState;
993
994 if (FeaturePcdGet (PcdCpuSmmDebug)) {
995 ASSERT(CpuIndex < mMaxNumberOfCpus);
996 CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
997 if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
998 CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();
999 CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();
1000 } else {
1001 CpuSaveState->x64._DR7 = AsmReadDr7 ();
1002 CpuSaveState->x64._DR6 = AsmReadDr6 ();
1003 }
1004 }
1005 }
1006
1007 /**
1008 C function for SMI entry, each processor comes here upon SMI trigger.
1009
1010 @param CpuIndex CPU Index
1011
1012 **/
1013 VOID
1014 EFIAPI
1015 SmiRendezvous (
1016 IN UINTN CpuIndex
1017 )
1018 {
1019 EFI_STATUS Status;
1020 BOOLEAN ValidSmi;
1021 BOOLEAN IsBsp;
1022 BOOLEAN BspInProgress;
1023 UINTN Index;
1024 UINTN Cr2;
1025
1026 ASSERT(CpuIndex < mMaxNumberOfCpus);
1027
1028 //
1029 // Save Cr2 because Page Fault exception in SMM may override its value
1030 //
1031 Cr2 = AsmReadCr2 ();
1032
1033 //
1034 // Perform CPU specific entry hooks
1035 //
1036 SmmCpuFeaturesRendezvousEntry (CpuIndex);
1037
1038 //
1039 // Determine if this is a valid SMI
1040 //
1041 ValidSmi = PlatformValidSmi();
1042
1043 //
1044 // Determine if BSP has been already in progress. Note this must be checked after
1045 // ValidSmi because BSP may clear a valid SMI source after checking in.
1046 //
1047 BspInProgress = *mSmmMpSyncData->InsideSmm;
1048
1049 if (!BspInProgress && !ValidSmi) {
1050 //
1051 // If we reach here, it means when we sampled the ValidSmi flag, SMI status had not
1052 // been cleared by BSP in a new SMI run (so we have a truly invalid SMI), or SMI
1053 // status had been cleared by BSP and an existing SMI run has almost ended. (Note
1054 // we sampled ValidSmi flag BEFORE judging BSP-in-progress status.) In both cases, there
1055 // is nothing we need to do.
1056 //
1057 goto Exit;
1058 } else {
1059 //
1060 // Signal presence of this processor
1061 //
1062 if (ReleaseSemaphore (mSmmMpSyncData->Counter) == 0) {
1063 //
1064 // BSP has already ended the synchronization, so QUIT!!!
1065 //
1066
1067 //
1068 // Wait for BSP's signal to finish SMI
1069 //
1070 while (*mSmmMpSyncData->AllCpusInSync) {
1071 CpuPause ();
1072 }
1073 goto Exit;
1074 } else {
1075
1076 //
1077 // The BUSY lock is initialized to Released state.
1078 // This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.
1079 // E.g., with Relaxed AP flow, SmmStartupThisAp() may be called immediately
1080 // after AP's present flag is detected.
1081 //
1082 InitializeSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
1083 }
1084
1085 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1086 ActivateSmmProfile (CpuIndex);
1087 }
1088
1089 if (BspInProgress) {
1090 //
1091 // BSP has been elected. Follow AP path, regardless of ValidSmi flag
1092 // as BSP may have cleared the SMI status
1093 //
1094 APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);
1095 } else {
1096 //
1097 // We have a valid SMI
1098 //
1099
1100 //
1101 // Elect BSP
1102 //
1103 IsBsp = FALSE;
1104 if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) {
1105 if (!mSmmMpSyncData->SwitchBsp || mSmmMpSyncData->CandidateBsp[CpuIndex]) {
1106 //
1107 // Call platform hook to do BSP election
1108 //
1109 Status = PlatformSmmBspElection (&IsBsp);
1110 if (EFI_SUCCESS == Status) {
1111 //
1112 // Platform hook determines successfully
1113 //
1114 if (IsBsp) {
1115 mSmmMpSyncData->BspIndex = (UINT32)CpuIndex;
1116 }
1117 } else {
1118 //
1119 // Platform hook fails to determine, use default BSP election method
1120 //
1121 InterlockedCompareExchange32 (
1122 (UINT32*)&mSmmMpSyncData->BspIndex,
1123 (UINT32)-1,
1124 (UINT32)CpuIndex
1125 );
1126 }
1127 }
1128 }
1129
1130 //
1131 // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP
1132 //
1133 if (mSmmMpSyncData->BspIndex == CpuIndex) {
1134
1135 //
1136 // Clear last request for SwitchBsp.
1137 //
1138 if (mSmmMpSyncData->SwitchBsp) {
1139 mSmmMpSyncData->SwitchBsp = FALSE;
1140 for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
1141 mSmmMpSyncData->CandidateBsp[Index] = FALSE;
1142 }
1143 }
1144
1145 if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
1146 SmmProfileRecordSmiNum ();
1147 }
1148
1149 //
1150 // BSP Handler is always called with a ValidSmi == TRUE
1151 //
1152 BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);
1153 } else {
1154 APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);
1155 }
1156 }
1157
1158 ASSERT (*mSmmMpSyncData->CpuData[CpuIndex].Run == 0);
1159
1160 //
1161 // Wait for BSP's signal to exit SMI
1162 //
1163 while (*mSmmMpSyncData->AllCpusInSync) {
1164 CpuPause ();
1165 }
1166 }
1167
1168 Exit:
1169 SmmCpuFeaturesRendezvousExit (CpuIndex);
1170 //
1171 // Restore Cr2
1172 //
1173 AsmWriteCr2 (Cr2);
1174 }
1175
1176 /**
1177 Allocate buffer for all semaphores and spin locks.
1178
1179 **/
1180 VOID
1181 InitializeSmmCpuSemaphores (
1182 VOID
1183 )
1184 {
1185 UINTN ProcessorCount;
1186 UINTN TotalSize;
1187 UINTN GlobalSemaphoresSize;
1188 UINTN CpuSemaphoresSize;
1189 UINTN MsrSemahporeSize;
1190 UINTN SemaphoreSize;
1191 UINTN Pages;
1192 UINTN *SemaphoreBlock;
1193 UINTN SemaphoreAddr;
1194
1195 SemaphoreSize = GetSpinLockProperties ();
1196 ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
1197 GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize;
1198 CpuSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize;
1199 MsrSemahporeSize = MSR_SPIN_LOCK_INIT_NUM * SemaphoreSize;
1200 TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize + MsrSemahporeSize;
1201 DEBUG((EFI_D_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize));
1202 DEBUG((EFI_D_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
1203 Pages = EFI_SIZE_TO_PAGES (TotalSize);
1204 SemaphoreBlock = AllocatePages (Pages);
1205 ASSERT (SemaphoreBlock != NULL);
1206 ZeroMem (SemaphoreBlock, TotalSize);
1207
1208 SemaphoreAddr = (UINTN)SemaphoreBlock;
1209 mSmmCpuSemaphores.SemaphoreGlobal.Counter = (UINT32 *)SemaphoreAddr;
1210 SemaphoreAddr += SemaphoreSize;
1211 mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm = (BOOLEAN *)SemaphoreAddr;
1212 SemaphoreAddr += SemaphoreSize;
1213 mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync = (BOOLEAN *)SemaphoreAddr;
1214 SemaphoreAddr += SemaphoreSize;
1215 mSmmCpuSemaphores.SemaphoreGlobal.PFLock = (SPIN_LOCK *)SemaphoreAddr;
1216 SemaphoreAddr += SemaphoreSize;
1217 mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock
1218 = (SPIN_LOCK *)SemaphoreAddr;
1219 SemaphoreAddr += SemaphoreSize;
1220 mSmmCpuSemaphores.SemaphoreGlobal.MemoryMappedLock
1221 = (SPIN_LOCK *)SemaphoreAddr;
1222
1223 SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize;
1224 mSmmCpuSemaphores.SemaphoreCpu.Busy = (SPIN_LOCK *)SemaphoreAddr;
1225 SemaphoreAddr += ProcessorCount * SemaphoreSize;
1226 mSmmCpuSemaphores.SemaphoreCpu.Run = (UINT32 *)SemaphoreAddr;
1227 SemaphoreAddr += ProcessorCount * SemaphoreSize;
1228 mSmmCpuSemaphores.SemaphoreCpu.Present = (BOOLEAN *)SemaphoreAddr;
1229
1230 SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize + CpuSemaphoresSize;
1231 mSmmCpuSemaphores.SemaphoreMsr.Msr = (SPIN_LOCK *)SemaphoreAddr;
1232 mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter =
1233 ((UINTN)SemaphoreBlock + Pages * SIZE_4KB - SemaphoreAddr) / SemaphoreSize;
1234 ASSERT (mSmmCpuSemaphores.SemaphoreMsr.AvailableCounter >= MSR_SPIN_LOCK_INIT_NUM);
1235
1236 mPFLock = mSmmCpuSemaphores.SemaphoreGlobal.PFLock;
1237 mConfigSmmCodeAccessCheckLock = mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock;
1238 mMemoryMappedLock = mSmmCpuSemaphores.SemaphoreGlobal.MemoryMappedLock;
1239
1240 mSemaphoreSize = SemaphoreSize;
1241 }
1242
1243 /**
1244 Initialize un-cacheable data.
1245
1246 **/
1247 VOID
1248 EFIAPI
1249 InitializeMpSyncData (
1250 VOID
1251 )
1252 {
1253 UINTN CpuIndex;
1254
1255 if (mSmmMpSyncData != NULL) {
1256 //
1257 // mSmmMpSyncDataSize includes one structure of SMM_DISPATCHER_MP_SYNC_DATA, one
1258 // CpuData array of SMM_CPU_DATA_BLOCK and one CandidateBsp array of BOOLEAN.
1259 //
1260 ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize);
1261 mSmmMpSyncData->CpuData = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA));
1262 mSmmMpSyncData->CandidateBsp = (BOOLEAN *)(mSmmMpSyncData->CpuData + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
1263 if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) {
1264 //
1265 // Enable BSP election by setting BspIndex to -1
1266 //
1267 mSmmMpSyncData->BspIndex = (UINT32)-1;
1268 }
1269 mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode;
1270
1271 mSmmMpSyncData->Counter = mSmmCpuSemaphores.SemaphoreGlobal.Counter;
1272 mSmmMpSyncData->InsideSmm = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm;
1273 mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync;
1274 ASSERT (mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&
1275 mSmmMpSyncData->AllCpusInSync != NULL);
1276 *mSmmMpSyncData->Counter = 0;
1277 *mSmmMpSyncData->InsideSmm = FALSE;
1278 *mSmmMpSyncData->AllCpusInSync = FALSE;
1279
1280 for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex ++) {
1281 mSmmMpSyncData->CpuData[CpuIndex].Busy =
1282 (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex);
1283 mSmmMpSyncData->CpuData[CpuIndex].Run =
1284 (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreSize * CpuIndex);
1285 mSmmMpSyncData->CpuData[CpuIndex].Present =
1286 (BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemaphoreSize * CpuIndex);
1287 *(mSmmMpSyncData->CpuData[CpuIndex].Busy) = 0;
1288 *(mSmmMpSyncData->CpuData[CpuIndex].Run) = 0;
1289 *(mSmmMpSyncData->CpuData[CpuIndex].Present) = FALSE;
1290 }
1291 }
1292 }
1293
1294 /**
1295 Initialize global data for MP synchronization.
1296
1297 @param Stacks Base address of SMI stack buffer for all processors.
1298 @param StackSize Stack size for each processor in SMM.
1299
1300 **/
1301 UINT32
1302 InitializeMpServiceData (
1303 IN VOID *Stacks,
1304 IN UINTN StackSize
1305 )
1306 {
1307 UINT32 Cr3;
1308 UINTN Index;
1309 UINT8 *GdtTssTables;
1310 UINTN GdtTableStepSize;
1311
1312 //
1313 // Allocate memory for all locks and semaphores
1314 //
1315 InitializeSmmCpuSemaphores ();
1316
1317 //
1318 // Initialize mSmmMpSyncData
1319 //
1320 mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) +
1321 (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
1322 mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize));
1323 ASSERT (mSmmMpSyncData != NULL);
1324 mCpuSmmSyncMode = (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode);
1325 InitializeMpSyncData ();
1326
1327 //
1328 // Initialize physical address mask
1329 // NOTE: Physical memory above virtual address limit is not supported !!!
1330 //
1331 AsmCpuid (0x80000008, (UINT32*)&Index, NULL, NULL, NULL);
1332 gPhyMask = LShiftU64 (1, (UINT8)Index) - 1;
1333 gPhyMask &= (1ull << 48) - EFI_PAGE_SIZE;
1334
1335 //
1336 // Create page tables
1337 //
1338 Cr3 = SmmInitPageTable ();
1339
1340 GdtTssTables = InitGdt (Cr3, &GdtTableStepSize);
1341
1342 //
1343 // Install SMI handler for each CPU
1344 //
1345 for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
1346 InstallSmiHandler (
1347 Index,
1348 (UINT32)mCpuHotPlugData.SmBase[Index],
1349 (VOID*)((UINTN)Stacks + (StackSize * Index)),
1350 StackSize,
1351 (UINTN)(GdtTssTables + GdtTableStepSize * Index),
1352 gcSmiGdtr.Limit + 1,
1353 gcSmiIdtr.Base,
1354 gcSmiIdtr.Limit + 1,
1355 Cr3
1356 );
1357 }
1358
1359 //
1360 // Record current MTRR settings
1361 //
1362 ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs));
1363 MtrrGetAllMtrrs (&gSmiMtrrs);
1364
1365 return Cr3;
1366 }
1367
1368 /**
1369
1370 Register the SMM Foundation entry point.
1371
1372 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
1373 @param SmmEntryPoint SMM Foundation EntryPoint
1374
1375 @retval EFI_SUCCESS Successfully to register SMM foundation entry point
1376
1377 **/
1378 EFI_STATUS
1379 EFIAPI
1380 RegisterSmmEntry (
1381 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,
1382 IN EFI_SMM_ENTRY_POINT SmmEntryPoint
1383 )
1384 {
1385 //
1386 // Record SMM Foundation EntryPoint, later invoke it on SMI entry vector.
1387 //
1388 gSmmCpuPrivate->SmmCoreEntry = SmmEntryPoint;
1389 return EFI_SUCCESS;
1390 }
EFI Development Kit II mirror for PVE