2 SMM MP service implementation
4 Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "PiSmmCpuDxeSmm.h"
20 // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
22 MTRR_SETTINGS gSmiMtrrs
;
24 SMM_DISPATCHER_MP_SYNC_DATA
*mSmmMpSyncData
= NULL
;
25 UINTN mSmmMpSyncDataSize
;
26 SMM_CPU_SEMAPHORES mSmmCpuSemaphores
;
28 SPIN_LOCK
*mPFLock
= NULL
;
29 SMM_CPU_SYNC_MODE mCpuSmmSyncMode
;
32 Performs an atomic compare exchange operation to get semaphore.
33 The compare exchange operation must be performed using
36 @param Sem IN: 32-bit unsigned integer
37 OUT: original integer - 1
38 @return Original integer - 1
43 IN OUT
volatile UINT32
*Sem
50 } while (Value
== 0 ||
51 InterlockedCompareExchange32 (
61 Performs an atomic compare exchange operation to release semaphore.
62 The compare exchange operation must be performed using
65 @param Sem IN: 32-bit unsigned integer
66 OUT: original integer + 1
67 @return Original integer + 1
72 IN OUT
volatile UINT32
*Sem
79 } while (Value
+ 1 != 0 &&
80 InterlockedCompareExchange32 (
89 Performs an atomic compare exchange operation to lock semaphore.
90 The compare exchange operation must be performed using
93 @param Sem IN: 32-bit unsigned integer
95 @return Original integer
100 IN OUT
volatile UINT32
*Sem
107 } while (InterlockedCompareExchange32 (
115 Wait all APs to performs an atomic compare exchange operation to release semaphore.
117 @param NumberOfAPs AP number
127 BspIndex
= mSmmMpSyncData
->BspIndex
;
128 while (NumberOfAPs
-- > 0) {
129 WaitForSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
134 Performs an atomic compare exchange operation to release semaphore
146 BspIndex
= mSmmMpSyncData
->BspIndex
;
147 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
148 if (Index
!= BspIndex
&& *(mSmmMpSyncData
->CpuData
[Index
].Present
)) {
149 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[Index
].Run
);
155 Checks if all CPUs (with certain exceptions) have checked in for this SMI run
157 @param Exceptions CPU Arrival exception flags.
159 @retval TRUE if all CPUs the have checked in.
160 @retval FALSE if at least one Normal AP hasn't checked in.
164 AllCpusInSmmWithExceptions (
165 SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions
169 SMM_CPU_DATA_BLOCK
*CpuData
;
170 EFI_PROCESSOR_INFORMATION
*ProcessorInfo
;
172 ASSERT (*mSmmMpSyncData
->Counter
<= mNumberOfCpus
);
174 if (*mSmmMpSyncData
->Counter
== mNumberOfCpus
) {
178 CpuData
= mSmmMpSyncData
->CpuData
;
179 ProcessorInfo
= gSmmCpuPrivate
->ProcessorInfo
;
180 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
181 if (!(*(CpuData
[Index
].Present
)) && ProcessorInfo
[Index
].ProcessorId
!= INVALID_APIC_ID
) {
182 if (((Exceptions
& ARRIVAL_EXCEPTION_DELAYED
) != 0) && SmmCpuFeaturesGetSmmRegister (Index
, SmmRegSmmDelayed
) != 0) {
185 if (((Exceptions
& ARRIVAL_EXCEPTION_BLOCKED
) != 0) && SmmCpuFeaturesGetSmmRegister (Index
, SmmRegSmmBlocked
) != 0) {
188 if (((Exceptions
& ARRIVAL_EXCEPTION_SMI_DISABLED
) != 0) && SmmCpuFeaturesGetSmmRegister (Index
, SmmRegSmmEnable
) != 0) {
201 Given timeout constraint, wait for all APs to arrive, and insure when this function returns, no AP will execute normal mode code before
202 entering SMM, except SMI disabled APs.
206 SmmWaitForApArrival (
213 ASSERT (*mSmmMpSyncData
->Counter
<= mNumberOfCpus
);
216 // Platform implementor should choose a timeout value appropriately:
217 // - The timeout value should balance the SMM time constrains and the likelihood that delayed CPUs are excluded in the SMM run. Note
218 // the SMI Handlers must ALWAYS take into account the cases that not all APs are available in an SMI run.
219 // - The timeout value must, in the case of 2nd timeout, be at least long enough to give time for all APs to receive the SMI IPI
220 // and either enter SMM or buffer the SMI, to insure there is no CPU running normal mode code when SMI handling starts. This will
221 // be TRUE even if a blocked CPU is brought out of the blocked state by a normal mode CPU (before the normal mode CPU received the
222 // SMI IPI), because with a buffered SMI, and CPU will enter SMM immediately after it is brought out of the blocked state.
223 // - The timeout value must be longer than longest possible IO operation in the system
227 // Sync with APs 1st timeout
229 for (Timer
= StartSyncTimer ();
230 !IsSyncTimerTimeout (Timer
) &&
231 !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED
| ARRIVAL_EXCEPTION_SMI_DISABLED
);
237 // Not all APs have arrived, so we need 2nd round of timeout. IPIs should be sent to ALL none present APs,
239 // a) Delayed AP may have just come out of the delayed state. Blocked AP may have just been brought out of blocked state by some AP running
240 // normal mode code. These APs need to be guaranteed to have an SMI pending to insure that once they are out of delayed / blocked state, they
241 // enter SMI immediately without executing instructions in normal mode. Note traditional flow requires there are no APs doing normal mode
242 // work while SMI handling is on-going.
243 // b) As a consequence of SMI IPI sending, (spurious) SMI may occur after this SMM run.
244 // c) ** NOTE **: Use SMI disabling feature VERY CAREFULLY (if at all) for traditional flow, because a processor in SMI-disabled state
245 // will execute normal mode code, which breaks the traditional SMI handlers' assumption that no APs are doing normal
246 // mode work while SMI handling is on-going.
247 // d) We don't add code to check SMI disabling status to skip sending IPI to SMI disabled APs, because:
248 // - In traditional flow, SMI disabling is discouraged.
249 // - In relaxed flow, CheckApArrival() will check SMI disabling status before calling this function.
250 // In both cases, adding SMI-disabling checking code increases overhead.
252 if (*mSmmMpSyncData
->Counter
< mNumberOfCpus
) {
254 // Send SMI IPIs to bring outside processors in
256 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
257 if (!(*(mSmmMpSyncData
->CpuData
[Index
].Present
)) && gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
!= INVALID_APIC_ID
) {
258 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
263 // Sync with APs 2nd timeout.
265 for (Timer
= StartSyncTimer ();
266 !IsSyncTimerTimeout (Timer
) &&
267 !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED
| ARRIVAL_EXCEPTION_SMI_DISABLED
);
278 Replace OS MTRR's with SMI MTRR's.
280 @param CpuIndex Processor Index
288 SmmCpuFeaturesDisableSmrr ();
291 // Replace all MTRRs registers
293 MtrrSetAllMtrrs (&gSmiMtrrs
);
299 @param CpuIndex BSP processor Index
300 @param SyncMode SMM MP sync mode
306 IN SMM_CPU_SYNC_MODE SyncMode
312 BOOLEAN ClearTopLevelSmiResult
;
315 ASSERT (CpuIndex
== mSmmMpSyncData
->BspIndex
);
319 // Flag BSP's presence
321 *mSmmMpSyncData
->InsideSmm
= TRUE
;
324 // Initialize Debug Agent to start source level debug in BSP handler
326 InitializeDebugAgent (DEBUG_AGENT_INIT_ENTER_SMI
, NULL
, NULL
);
329 // Mark this processor's presence
331 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) = TRUE
;
334 // Clear platform top level SMI status bit before calling SMI handlers. If
335 // we cleared it after SMI handlers are run, we would miss the SMI that
336 // occurs after SMI handlers are done and before SMI status bit is cleared.
338 ClearTopLevelSmiResult
= ClearTopLevelSmiStatus();
339 ASSERT (ClearTopLevelSmiResult
== TRUE
);
342 // Set running processor index
344 gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
= CpuIndex
;
347 // If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
349 if (SyncMode
== SmmCpuSyncModeTradition
|| SmmCpuFeaturesNeedConfigureMtrrs()) {
352 // Wait for APs to arrive
354 SmmWaitForApArrival();
357 // Lock the counter down and retrieve the number of APs
359 *mSmmMpSyncData
->AllCpusInSync
= TRUE
;
360 ApCount
= LockdownSemaphore (mSmmMpSyncData
->Counter
) - 1;
363 // Wait for all APs to get ready for programming MTRRs
365 WaitForAllAPs (ApCount
);
367 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
369 // Signal all APs it's time for backup MTRRs
374 // WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
375 // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
376 // to a large enough value to avoid this situation.
377 // Note: For HT capable CPUs, threads within a core share the same set of MTRRs.
378 // We do the backup first and then set MTRR to avoid race condition for threads
381 MtrrGetAllMtrrs(&Mtrrs
);
384 // Wait for all APs to complete their MTRR saving
386 WaitForAllAPs (ApCount
);
389 // Let all processors program SMM MTRRs together
394 // WaitForSemaphore() may wait for ever if an AP happens to enter SMM at
395 // exactly this point. Please make sure PcdCpuSmmMaxSyncLoops has been set
396 // to a large enough value to avoid this situation.
398 ReplaceOSMtrrs (CpuIndex
);
401 // Wait for all APs to complete their MTRR programming
403 WaitForAllAPs (ApCount
);
408 // The BUSY lock is initialized to Acquired state
410 AcquireSpinLock (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
413 // Perform the pre tasks
418 // Invoke SMM Foundation EntryPoint with the processor information context.
420 gSmmCpuPrivate
->SmmCoreEntry (&gSmmCpuPrivate
->SmmCoreEntryContext
);
423 // Make sure all APs have completed their pending none-block tasks
425 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
426 if (Index
!= CpuIndex
&& *(mSmmMpSyncData
->CpuData
[Index
].Present
)) {
427 AcquireSpinLock (mSmmMpSyncData
->CpuData
[Index
].Busy
);
428 ReleaseSpinLock (mSmmMpSyncData
->CpuData
[Index
].Busy
);
433 // Perform the remaining tasks
435 PerformRemainingTasks ();
438 // If Relaxed-AP Sync Mode: gather all available APs after BSP SMM handlers are done, and
439 // make those APs to exit SMI synchronously. APs which arrive later will be excluded and
440 // will run through freely.
442 if (SyncMode
!= SmmCpuSyncModeTradition
&& !SmmCpuFeaturesNeedConfigureMtrrs()) {
445 // Lock the counter down and retrieve the number of APs
447 *mSmmMpSyncData
->AllCpusInSync
= TRUE
;
448 ApCount
= LockdownSemaphore (mSmmMpSyncData
->Counter
) - 1;
450 // Make sure all APs have their Present flag set
454 for (Index
= mMaxNumberOfCpus
; Index
-- > 0;) {
455 if (*(mSmmMpSyncData
->CpuData
[Index
].Present
)) {
459 if (PresentCount
> ApCount
) {
466 // Notify all APs to exit
468 *mSmmMpSyncData
->InsideSmm
= FALSE
;
472 // Wait for all APs to complete their pending tasks
474 WaitForAllAPs (ApCount
);
476 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
478 // Signal APs to restore MTRRs
485 SmmCpuFeaturesReenableSmrr ();
486 MtrrSetAllMtrrs(&Mtrrs
);
489 // Wait for all APs to complete MTRR programming
491 WaitForAllAPs (ApCount
);
495 // Stop source level debug in BSP handler, the code below will not be
498 InitializeDebugAgent (DEBUG_AGENT_INIT_EXIT_SMI
, NULL
, NULL
);
501 // Signal APs to Reset states/semaphore for this processor
506 // Perform pending operations for hot-plug
511 // Clear the Present flag of BSP
513 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) = FALSE
;
516 // Gather APs to exit SMM synchronously. Note the Present flag is cleared by now but
517 // WaitForAllAps does not depend on the Present flag.
519 WaitForAllAPs (ApCount
);
522 // Reset BspIndex to -1, meaning BSP has not been elected.
524 if (FeaturePcdGet (PcdCpuSmmEnableBspElection
)) {
525 mSmmMpSyncData
->BspIndex
= (UINT32
)-1;
529 // Allow APs to check in from this point on
531 *mSmmMpSyncData
->Counter
= 0;
532 *mSmmMpSyncData
->AllCpusInSync
= FALSE
;
538 @param CpuIndex AP processor Index.
539 @param ValidSmi Indicates that current SMI is a valid SMI or not.
540 @param SyncMode SMM MP sync mode.
547 IN SMM_CPU_SYNC_MODE SyncMode
557 for (Timer
= StartSyncTimer ();
558 !IsSyncTimerTimeout (Timer
) &&
559 !(*mSmmMpSyncData
->InsideSmm
);
564 if (!(*mSmmMpSyncData
->InsideSmm
)) {
566 // BSP timeout in the first round
568 if (mSmmMpSyncData
->BspIndex
!= -1) {
570 // BSP Index is known
572 BspIndex
= mSmmMpSyncData
->BspIndex
;
573 ASSERT (CpuIndex
!= BspIndex
);
576 // Send SMI IPI to bring BSP in
578 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[BspIndex
].ProcessorId
);
581 // Now clock BSP for the 2nd time
583 for (Timer
= StartSyncTimer ();
584 !IsSyncTimerTimeout (Timer
) &&
585 !(*mSmmMpSyncData
->InsideSmm
);
590 if (!(*mSmmMpSyncData
->InsideSmm
)) {
592 // Give up since BSP is unable to enter SMM
593 // and signal the completion of this AP
594 WaitForSemaphore (mSmmMpSyncData
->Counter
);
599 // Don't know BSP index. Give up without sending IPI to BSP.
601 WaitForSemaphore (mSmmMpSyncData
->Counter
);
609 BspIndex
= mSmmMpSyncData
->BspIndex
;
610 ASSERT (CpuIndex
!= BspIndex
);
613 // Mark this processor's presence
615 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) = TRUE
;
617 if (SyncMode
== SmmCpuSyncModeTradition
|| SmmCpuFeaturesNeedConfigureMtrrs()) {
619 // Notify BSP of arrival at this point
621 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
624 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
626 // Wait for the signal from BSP to backup MTRRs
628 WaitForSemaphore (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
633 MtrrGetAllMtrrs(&Mtrrs
);
636 // Signal BSP the completion of this AP
638 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
641 // Wait for BSP's signal to program MTRRs
643 WaitForSemaphore (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
646 // Replace OS MTRRs with SMI MTRRs
648 ReplaceOSMtrrs (CpuIndex
);
651 // Signal BSP the completion of this AP
653 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
658 // Wait for something to happen
660 WaitForSemaphore (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
663 // Check if BSP wants to exit SMM
665 if (!(*mSmmMpSyncData
->InsideSmm
)) {
670 // BUSY should be acquired by SmmStartupThisAp()
673 !AcquireSpinLockOrFail (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
)
677 // Invoke the scheduled procedure
679 (*mSmmMpSyncData
->CpuData
[CpuIndex
].Procedure
) (
680 (VOID
*)mSmmMpSyncData
->CpuData
[CpuIndex
].Parameter
686 ReleaseSpinLock (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
689 if (SmmCpuFeaturesNeedConfigureMtrrs()) {
691 // Notify BSP the readiness of this AP to program MTRRs
693 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
696 // Wait for the signal from BSP to program MTRRs
698 WaitForSemaphore (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
703 SmmCpuFeaturesReenableSmrr ();
704 MtrrSetAllMtrrs(&Mtrrs
);
708 // Notify BSP the readiness of this AP to Reset states/semaphore for this processor
710 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
713 // Wait for the signal from BSP to Reset states/semaphore for this processor
715 WaitForSemaphore (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
718 // Reset states/semaphore for this processor
720 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) = FALSE
;
723 // Notify BSP the readiness of this AP to exit SMM
725 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[BspIndex
].Run
);
730 Create 4G PageTable in SMRAM.
732 @param[in] Is32BitPageTable Whether the page table is 32-bit PAE
733 @return PageTable Address
738 IN BOOLEAN Is32BitPageTable
746 UINTN High2MBoundary
;
756 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
758 // Add one more page for known good stack, then find the lower 2MB aligned address.
760 Low2MBoundary
= (mSmmStackArrayBase
+ EFI_PAGE_SIZE
) & ~(SIZE_2MB
-1);
762 // Add two more pages for known good stack and stack guard page,
763 // then find the lower 2MB aligned address.
765 High2MBoundary
= (mSmmStackArrayEnd
- mSmmStackSize
+ EFI_PAGE_SIZE
* 2) & ~(SIZE_2MB
-1);
766 PagesNeeded
= ((High2MBoundary
- Low2MBoundary
) / SIZE_2MB
) + 1;
769 // Allocate the page table
771 PageTable
= AllocatePageTableMemory (5 + PagesNeeded
);
772 ASSERT (PageTable
!= NULL
);
774 PageTable
= (VOID
*)((UINTN
)PageTable
);
775 Pte
= (UINT64
*)PageTable
;
778 // Zero out all page table entries first
780 ZeroMem (Pte
, EFI_PAGES_TO_SIZE (1));
783 // Set Page Directory Pointers
785 for (Index
= 0; Index
< 4; Index
++) {
786 Pte
[Index
] = ((UINTN
)PageTable
+ EFI_PAGE_SIZE
* (Index
+ 1)) | mAddressEncMask
|
787 (Is32BitPageTable
? IA32_PAE_PDPTE_ATTRIBUTE_BITS
: PAGE_ATTRIBUTE_BITS
);
789 Pte
+= EFI_PAGE_SIZE
/ sizeof (*Pte
);
792 // Fill in Page Directory Entries
794 for (Index
= 0; Index
< EFI_PAGE_SIZE
* 4 / sizeof (*Pte
); Index
++) {
795 Pte
[Index
] = (Index
<< 21) | mAddressEncMask
| IA32_PG_PS
| PAGE_ATTRIBUTE_BITS
;
798 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
799 Pages
= (UINTN
)PageTable
+ EFI_PAGES_TO_SIZE (5);
800 GuardPage
= mSmmStackArrayBase
+ EFI_PAGE_SIZE
;
801 Pdpte
= (UINT64
*)PageTable
;
802 for (PageIndex
= Low2MBoundary
; PageIndex
<= High2MBoundary
; PageIndex
+= SIZE_2MB
) {
803 Pte
= (UINT64
*)(UINTN
)(Pdpte
[BitFieldRead32 ((UINT32
)PageIndex
, 30, 31)] & ~mAddressEncMask
& ~(EFI_PAGE_SIZE
- 1));
804 Pte
[BitFieldRead32 ((UINT32
)PageIndex
, 21, 29)] = (UINT64
)Pages
| mAddressEncMask
| PAGE_ATTRIBUTE_BITS
;
806 // Fill in Page Table Entries
808 Pte
= (UINT64
*)Pages
;
809 PageAddress
= PageIndex
;
810 for (Index
= 0; Index
< EFI_PAGE_SIZE
/ sizeof (*Pte
); Index
++) {
811 if (PageAddress
== GuardPage
) {
813 // Mark the guard page as non-present
815 Pte
[Index
] = PageAddress
| mAddressEncMask
;
816 GuardPage
+= mSmmStackSize
;
817 if (GuardPage
> mSmmStackArrayEnd
) {
821 Pte
[Index
] = PageAddress
| mAddressEncMask
| PAGE_ATTRIBUTE_BITS
;
823 PageAddress
+= EFI_PAGE_SIZE
;
825 Pages
+= EFI_PAGE_SIZE
;
829 return (UINT32
)(UINTN
)PageTable
;
833 Schedule a procedure to run on the specified CPU.
835 @param[in] Procedure The address of the procedure to run
836 @param[in] CpuIndex Target CPU Index
837 @param[in, out] ProcArguments The parameter to pass to the procedure
838 @param[in] BlockingMode Startup AP in blocking mode or not
840 @retval EFI_INVALID_PARAMETER CpuNumber not valid
841 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
842 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
843 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
844 @retval EFI_SUCCESS The procedure has been successfully scheduled
848 InternalSmmStartupThisAp (
849 IN EFI_AP_PROCEDURE Procedure
,
851 IN OUT VOID
*ProcArguments OPTIONAL
,
852 IN BOOLEAN BlockingMode
855 if (CpuIndex
>= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
) {
856 DEBUG((DEBUG_ERROR
, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex
, gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
));
857 return EFI_INVALID_PARAMETER
;
859 if (CpuIndex
== gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
860 DEBUG((DEBUG_ERROR
, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex
));
861 return EFI_INVALID_PARAMETER
;
863 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
864 if (mSmmMpSyncData
->EffectiveSyncMode
== SmmCpuSyncModeTradition
) {
865 DEBUG((DEBUG_ERROR
, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex
));
867 return EFI_INVALID_PARAMETER
;
869 if (gSmmCpuPrivate
->Operation
[CpuIndex
] == SmmCpuRemove
) {
870 if (!FeaturePcdGet (PcdCpuHotPlugSupport
)) {
871 DEBUG((DEBUG_ERROR
, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex
));
873 return EFI_INVALID_PARAMETER
;
877 AcquireSpinLock (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
879 if (!AcquireSpinLockOrFail (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
)) {
880 DEBUG((DEBUG_ERROR
, "mSmmMpSyncData->CpuData[%d].Busy\n", CpuIndex
));
881 return EFI_INVALID_PARAMETER
;
885 mSmmMpSyncData
->CpuData
[CpuIndex
].Procedure
= Procedure
;
886 mSmmMpSyncData
->CpuData
[CpuIndex
].Parameter
= ProcArguments
;
887 ReleaseSemaphore (mSmmMpSyncData
->CpuData
[CpuIndex
].Run
);
890 AcquireSpinLock (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
891 ReleaseSpinLock (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
897 Schedule a procedure to run on the specified CPU in blocking mode.
899 @param[in] Procedure The address of the procedure to run
900 @param[in] CpuIndex Target CPU Index
901 @param[in, out] ProcArguments The parameter to pass to the procedure
903 @retval EFI_INVALID_PARAMETER CpuNumber not valid
904 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
905 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
906 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
907 @retval EFI_SUCCESS The procedure has been successfully scheduled
912 SmmBlockingStartupThisAp (
913 IN EFI_AP_PROCEDURE Procedure
,
915 IN OUT VOID
*ProcArguments OPTIONAL
918 return InternalSmmStartupThisAp(Procedure
, CpuIndex
, ProcArguments
, TRUE
);
922 Schedule a procedure to run on the specified CPU.
924 @param Procedure The address of the procedure to run
925 @param CpuIndex Target CPU Index
926 @param ProcArguments The parameter to pass to the procedure
928 @retval EFI_INVALID_PARAMETER CpuNumber not valid
929 @retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
930 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
931 @retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
932 @retval EFI_SUCCESS The procedure has been successfully scheduled
938 IN EFI_AP_PROCEDURE Procedure
,
940 IN OUT VOID
*ProcArguments OPTIONAL
943 return InternalSmmStartupThisAp(Procedure
, CpuIndex
, ProcArguments
, FeaturePcdGet (PcdCpuSmmBlockStartupThisAp
));
947 This function sets DR6 & DR7 according to SMM save state, before running SMM C code.
948 They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.
950 NOTE: It might not be appreciated in runtime since it might
951 conflict with OS debugging facilities. Turn them off in RELEASE.
953 @param CpuIndex CPU Index
962 SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
964 if (FeaturePcdGet (PcdCpuSmmDebug
)) {
965 ASSERT(CpuIndex
< mMaxNumberOfCpus
);
966 CpuSaveState
= (SMRAM_SAVE_STATE_MAP
*)gSmmCpuPrivate
->CpuSaveState
[CpuIndex
];
967 if (mSmmSaveStateRegisterLma
== EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
) {
968 AsmWriteDr6 (CpuSaveState
->x86
._DR6
);
969 AsmWriteDr7 (CpuSaveState
->x86
._DR7
);
971 AsmWriteDr6 ((UINTN
)CpuSaveState
->x64
._DR6
);
972 AsmWriteDr7 ((UINTN
)CpuSaveState
->x64
._DR7
);
978 This function restores DR6 & DR7 to SMM save state.
980 NOTE: It might not be appreciated in runtime since it might
981 conflict with OS debugging facilities. Turn them off in RELEASE.
983 @param CpuIndex CPU Index
992 SMRAM_SAVE_STATE_MAP
*CpuSaveState
;
994 if (FeaturePcdGet (PcdCpuSmmDebug
)) {
995 ASSERT(CpuIndex
< mMaxNumberOfCpus
);
996 CpuSaveState
= (SMRAM_SAVE_STATE_MAP
*)gSmmCpuPrivate
->CpuSaveState
[CpuIndex
];
997 if (mSmmSaveStateRegisterLma
== EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
) {
998 CpuSaveState
->x86
._DR7
= (UINT32
)AsmReadDr7 ();
999 CpuSaveState
->x86
._DR6
= (UINT32
)AsmReadDr6 ();
1001 CpuSaveState
->x64
._DR7
= AsmReadDr7 ();
1002 CpuSaveState
->x64
._DR6
= AsmReadDr6 ();
1008 C function for SMI entry, each processor comes here upon SMI trigger.
1010 @param CpuIndex CPU Index
1022 BOOLEAN BspInProgress
;
1026 ASSERT(CpuIndex
< mMaxNumberOfCpus
);
1029 // Save Cr2 because Page Fault exception in SMM may override its value
1031 Cr2
= AsmReadCr2 ();
1034 // Perform CPU specific entry hooks
1036 SmmCpuFeaturesRendezvousEntry (CpuIndex
);
1039 // Determine if this is a valid SMI
1041 ValidSmi
= PlatformValidSmi();
1044 // Determine if BSP has been already in progress. Note this must be checked after
1045 // ValidSmi because BSP may clear a valid SMI source after checking in.
1047 BspInProgress
= *mSmmMpSyncData
->InsideSmm
;
1049 if (!BspInProgress
&& !ValidSmi
) {
1051 // If we reach here, it means when we sampled the ValidSmi flag, SMI status had not
1052 // been cleared by BSP in a new SMI run (so we have a truly invalid SMI), or SMI
1053 // status had been cleared by BSP and an existing SMI run has almost ended. (Note
1054 // we sampled ValidSmi flag BEFORE judging BSP-in-progress status.) In both cases, there
1055 // is nothing we need to do.
1060 // Signal presence of this processor
1062 if (ReleaseSemaphore (mSmmMpSyncData
->Counter
) == 0) {
1064 // BSP has already ended the synchronization, so QUIT!!!
1068 // Wait for BSP's signal to finish SMI
1070 while (*mSmmMpSyncData
->AllCpusInSync
) {
1077 // The BUSY lock is initialized to Released state.
1078 // This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.
1079 // E.g., with Relaxed AP flow, SmmStartupThisAp() may be called immediately
1080 // after AP's present flag is detected.
1082 InitializeSpinLock (mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
);
1085 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1086 ActivateSmmProfile (CpuIndex
);
1089 if (BspInProgress
) {
1091 // BSP has been elected. Follow AP path, regardless of ValidSmi flag
1092 // as BSP may have cleared the SMI status
1094 APHandler (CpuIndex
, ValidSmi
, mSmmMpSyncData
->EffectiveSyncMode
);
1097 // We have a valid SMI
1104 if (FeaturePcdGet (PcdCpuSmmEnableBspElection
)) {
1105 if (!mSmmMpSyncData
->SwitchBsp
|| mSmmMpSyncData
->CandidateBsp
[CpuIndex
]) {
1107 // Call platform hook to do BSP election
1109 Status
= PlatformSmmBspElection (&IsBsp
);
1110 if (EFI_SUCCESS
== Status
) {
1112 // Platform hook determines successfully
1115 mSmmMpSyncData
->BspIndex
= (UINT32
)CpuIndex
;
1119 // Platform hook fails to determine, use default BSP election method
1121 InterlockedCompareExchange32 (
1122 (UINT32
*)&mSmmMpSyncData
->BspIndex
,
1131 // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP
1133 if (mSmmMpSyncData
->BspIndex
== CpuIndex
) {
1136 // Clear last request for SwitchBsp.
1138 if (mSmmMpSyncData
->SwitchBsp
) {
1139 mSmmMpSyncData
->SwitchBsp
= FALSE
;
1140 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1141 mSmmMpSyncData
->CandidateBsp
[Index
] = FALSE
;
1145 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1146 SmmProfileRecordSmiNum ();
1150 // BSP Handler is always called with a ValidSmi == TRUE
1152 BSPHandler (CpuIndex
, mSmmMpSyncData
->EffectiveSyncMode
);
1154 APHandler (CpuIndex
, ValidSmi
, mSmmMpSyncData
->EffectiveSyncMode
);
1158 ASSERT (*mSmmMpSyncData
->CpuData
[CpuIndex
].Run
== 0);
1161 // Wait for BSP's signal to exit SMI
1163 while (*mSmmMpSyncData
->AllCpusInSync
) {
1169 SmmCpuFeaturesRendezvousExit (CpuIndex
);
1177 Allocate buffer for all semaphores and spin locks.
1181 InitializeSmmCpuSemaphores (
1185 UINTN ProcessorCount
;
1187 UINTN GlobalSemaphoresSize
;
1188 UINTN CpuSemaphoresSize
;
1189 UINTN MsrSemahporeSize
;
1190 UINTN SemaphoreSize
;
1192 UINTN
*SemaphoreBlock
;
1193 UINTN SemaphoreAddr
;
1195 SemaphoreSize
= GetSpinLockProperties ();
1196 ProcessorCount
= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
1197 GlobalSemaphoresSize
= (sizeof (SMM_CPU_SEMAPHORE_GLOBAL
) / sizeof (VOID
*)) * SemaphoreSize
;
1198 CpuSemaphoresSize
= (sizeof (SMM_CPU_SEMAPHORE_CPU
) / sizeof (VOID
*)) * ProcessorCount
* SemaphoreSize
;
1199 MsrSemahporeSize
= MSR_SPIN_LOCK_INIT_NUM
* SemaphoreSize
;
1200 TotalSize
= GlobalSemaphoresSize
+ CpuSemaphoresSize
+ MsrSemahporeSize
;
1201 DEBUG((EFI_D_INFO
, "One Semaphore Size = 0x%x\n", SemaphoreSize
));
1202 DEBUG((EFI_D_INFO
, "Total Semaphores Size = 0x%x\n", TotalSize
));
1203 Pages
= EFI_SIZE_TO_PAGES (TotalSize
);
1204 SemaphoreBlock
= AllocatePages (Pages
);
1205 ASSERT (SemaphoreBlock
!= NULL
);
1206 ZeroMem (SemaphoreBlock
, TotalSize
);
1208 SemaphoreAddr
= (UINTN
)SemaphoreBlock
;
1209 mSmmCpuSemaphores
.SemaphoreGlobal
.Counter
= (UINT32
*)SemaphoreAddr
;
1210 SemaphoreAddr
+= SemaphoreSize
;
1211 mSmmCpuSemaphores
.SemaphoreGlobal
.InsideSmm
= (BOOLEAN
*)SemaphoreAddr
;
1212 SemaphoreAddr
+= SemaphoreSize
;
1213 mSmmCpuSemaphores
.SemaphoreGlobal
.AllCpusInSync
= (BOOLEAN
*)SemaphoreAddr
;
1214 SemaphoreAddr
+= SemaphoreSize
;
1215 mSmmCpuSemaphores
.SemaphoreGlobal
.PFLock
= (SPIN_LOCK
*)SemaphoreAddr
;
1216 SemaphoreAddr
+= SemaphoreSize
;
1217 mSmmCpuSemaphores
.SemaphoreGlobal
.CodeAccessCheckLock
1218 = (SPIN_LOCK
*)SemaphoreAddr
;
1219 SemaphoreAddr
+= SemaphoreSize
;
1220 mSmmCpuSemaphores
.SemaphoreGlobal
.MemoryMappedLock
1221 = (SPIN_LOCK
*)SemaphoreAddr
;
1223 SemaphoreAddr
= (UINTN
)SemaphoreBlock
+ GlobalSemaphoresSize
;
1224 mSmmCpuSemaphores
.SemaphoreCpu
.Busy
= (SPIN_LOCK
*)SemaphoreAddr
;
1225 SemaphoreAddr
+= ProcessorCount
* SemaphoreSize
;
1226 mSmmCpuSemaphores
.SemaphoreCpu
.Run
= (UINT32
*)SemaphoreAddr
;
1227 SemaphoreAddr
+= ProcessorCount
* SemaphoreSize
;
1228 mSmmCpuSemaphores
.SemaphoreCpu
.Present
= (BOOLEAN
*)SemaphoreAddr
;
1230 SemaphoreAddr
= (UINTN
)SemaphoreBlock
+ GlobalSemaphoresSize
+ CpuSemaphoresSize
;
1231 mSmmCpuSemaphores
.SemaphoreMsr
.Msr
= (SPIN_LOCK
*)SemaphoreAddr
;
1232 mSmmCpuSemaphores
.SemaphoreMsr
.AvailableCounter
=
1233 ((UINTN
)SemaphoreBlock
+ Pages
* SIZE_4KB
- SemaphoreAddr
) / SemaphoreSize
;
1234 ASSERT (mSmmCpuSemaphores
.SemaphoreMsr
.AvailableCounter
>= MSR_SPIN_LOCK_INIT_NUM
);
1236 mPFLock
= mSmmCpuSemaphores
.SemaphoreGlobal
.PFLock
;
1237 mConfigSmmCodeAccessCheckLock
= mSmmCpuSemaphores
.SemaphoreGlobal
.CodeAccessCheckLock
;
1238 mMemoryMappedLock
= mSmmCpuSemaphores
.SemaphoreGlobal
.MemoryMappedLock
;
1240 mSemaphoreSize
= SemaphoreSize
;
1244 Initialize un-cacheable data.
1249 InitializeMpSyncData (
1255 if (mSmmMpSyncData
!= NULL
) {
1257 // mSmmMpSyncDataSize includes one structure of SMM_DISPATCHER_MP_SYNC_DATA, one
1258 // CpuData array of SMM_CPU_DATA_BLOCK and one CandidateBsp array of BOOLEAN.
1260 ZeroMem (mSmmMpSyncData
, mSmmMpSyncDataSize
);
1261 mSmmMpSyncData
->CpuData
= (SMM_CPU_DATA_BLOCK
*)((UINT8
*)mSmmMpSyncData
+ sizeof (SMM_DISPATCHER_MP_SYNC_DATA
));
1262 mSmmMpSyncData
->CandidateBsp
= (BOOLEAN
*)(mSmmMpSyncData
->CpuData
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
);
1263 if (FeaturePcdGet (PcdCpuSmmEnableBspElection
)) {
1265 // Enable BSP election by setting BspIndex to -1
1267 mSmmMpSyncData
->BspIndex
= (UINT32
)-1;
1269 mSmmMpSyncData
->EffectiveSyncMode
= mCpuSmmSyncMode
;
1271 mSmmMpSyncData
->Counter
= mSmmCpuSemaphores
.SemaphoreGlobal
.Counter
;
1272 mSmmMpSyncData
->InsideSmm
= mSmmCpuSemaphores
.SemaphoreGlobal
.InsideSmm
;
1273 mSmmMpSyncData
->AllCpusInSync
= mSmmCpuSemaphores
.SemaphoreGlobal
.AllCpusInSync
;
1274 ASSERT (mSmmMpSyncData
->Counter
!= NULL
&& mSmmMpSyncData
->InsideSmm
!= NULL
&&
1275 mSmmMpSyncData
->AllCpusInSync
!= NULL
);
1276 *mSmmMpSyncData
->Counter
= 0;
1277 *mSmmMpSyncData
->InsideSmm
= FALSE
;
1278 *mSmmMpSyncData
->AllCpusInSync
= FALSE
;
1280 for (CpuIndex
= 0; CpuIndex
< gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
; CpuIndex
++) {
1281 mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
=
1282 (SPIN_LOCK
*)((UINTN
)mSmmCpuSemaphores
.SemaphoreCpu
.Busy
+ mSemaphoreSize
* CpuIndex
);
1283 mSmmMpSyncData
->CpuData
[CpuIndex
].Run
=
1284 (UINT32
*)((UINTN
)mSmmCpuSemaphores
.SemaphoreCpu
.Run
+ mSemaphoreSize
* CpuIndex
);
1285 mSmmMpSyncData
->CpuData
[CpuIndex
].Present
=
1286 (BOOLEAN
*)((UINTN
)mSmmCpuSemaphores
.SemaphoreCpu
.Present
+ mSemaphoreSize
* CpuIndex
);
1287 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Busy
) = 0;
1288 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Run
) = 0;
1289 *(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) = FALSE
;
1295 Initialize global data for MP synchronization.
1297 @param Stacks Base address of SMI stack buffer for all processors.
1298 @param StackSize Stack size for each processor in SMM.
1302 InitializeMpServiceData (
1309 UINT8
*GdtTssTables
;
1310 UINTN GdtTableStepSize
;
1313 // Allocate memory for all locks and semaphores
1315 InitializeSmmCpuSemaphores ();
1318 // Initialize mSmmMpSyncData
1320 mSmmMpSyncDataSize
= sizeof (SMM_DISPATCHER_MP_SYNC_DATA
) +
1321 (sizeof (SMM_CPU_DATA_BLOCK
) + sizeof (BOOLEAN
)) * gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
1322 mSmmMpSyncData
= (SMM_DISPATCHER_MP_SYNC_DATA
*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize
));
1323 ASSERT (mSmmMpSyncData
!= NULL
);
1324 mCpuSmmSyncMode
= (SMM_CPU_SYNC_MODE
)PcdGet8 (PcdCpuSmmSyncMode
);
1325 InitializeMpSyncData ();
1328 // Initialize physical address mask
1329 // NOTE: Physical memory above virtual address limit is not supported !!!
1331 AsmCpuid (0x80000008, (UINT32
*)&Index
, NULL
, NULL
, NULL
);
1332 gPhyMask
= LShiftU64 (1, (UINT8
)Index
) - 1;
1333 gPhyMask
&= (1ull << 48) - EFI_PAGE_SIZE
;
1336 // Create page tables
1338 Cr3
= SmmInitPageTable ();
1340 GdtTssTables
= InitGdt (Cr3
, &GdtTableStepSize
);
1343 // Install SMI handler for each CPU
1345 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1348 (UINT32
)mCpuHotPlugData
.SmBase
[Index
],
1349 (VOID
*)((UINTN
)Stacks
+ (StackSize
* Index
)),
1351 (UINTN
)(GdtTssTables
+ GdtTableStepSize
* Index
),
1352 gcSmiGdtr
.Limit
+ 1,
1354 gcSmiIdtr
.Limit
+ 1,
1360 // Record current MTRR settings
1362 ZeroMem (&gSmiMtrrs
, sizeof (gSmiMtrrs
));
1363 MtrrGetAllMtrrs (&gSmiMtrrs
);
1370 Register the SMM Foundation entry point.
1372 @param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
1373 @param SmmEntryPoint SMM Foundation EntryPoint
1375 @retval EFI_SUCCESS Successfully to register SMM foundation entry point
1381 IN CONST EFI_SMM_CONFIGURATION_PROTOCOL
*This
,
1382 IN EFI_SMM_ENTRY_POINT SmmEntryPoint
1386 // Record SMM Foundation EntryPoint, later invoke it on SMI entry vector.
1388 gSmmCpuPrivate
->SmmCoreEntry
= SmmEntryPoint
;