2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
24 NULL
, // Pointer to ProcessorInfo array
25 NULL
, // Pointer to Operation array
26 NULL
, // Pointer to CpuSaveStateSize array
27 NULL
, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
30 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL
// SmmCoreEntryContext.CpuSaveState
38 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
80 // SMM stack information
82 UINTN mSmmStackArrayBase
;
83 UINTN mSmmStackArrayEnd
;
87 // Pointer to structure used during S3 Resume
89 SMM_S3_RESUME_STATE
*mSmmS3ResumeState
= NULL
;
91 UINTN mMaxNumberOfCpus
= 1;
92 UINTN mNumberOfCpus
= 1;
95 // SMM ready to lock flag
97 BOOLEAN mSmmReadyToLock
= FALSE
;
100 // Global used to cache PCD for SMM Code Access Check enable
102 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
105 // Spin lock used to serialize setting of SMM Code Access Check feature
107 SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
= NULL
;
110 Initialize IDT to setup exception handlers for SMM.
119 BOOLEAN InterruptState
;
120 IA32_DESCRIPTOR DxeIdtr
;
122 // Disable Interrupt and save DXE IDT table
124 InterruptState
= SaveAndDisableInterrupts ();
125 AsmReadIdtr (&DxeIdtr
);
127 // Load SMM temporary IDT table
129 AsmWriteIdtr (&gcSmiIdtr
);
131 // Setup SMM default exception handlers, SMM IDT table
132 // will be updated and saved in gcSmiIdtr
134 Status
= InitializeCpuExceptionHandlers (NULL
);
135 ASSERT_EFI_ERROR (Status
);
137 // Restore DXE IDT table and CPU interrupt
139 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
140 SetInterruptState (InterruptState
);
144 Search module name by input IP address and output it.
146 @param CallerIpAddress Caller instruction pointer.
151 IN UINTN CallerIpAddress
155 EFI_IMAGE_DOS_HEADER
*DosHdr
;
156 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
;
158 UINT64 DumpIpAddress
;
163 Pe32Data
= CallerIpAddress
& ~(SIZE_4KB
- 1);
164 while (Pe32Data
!= 0) {
165 DosHdr
= (EFI_IMAGE_DOS_HEADER
*) Pe32Data
;
166 if (DosHdr
->e_magic
== EFI_IMAGE_DOS_SIGNATURE
) {
168 // DOS image header is present, so read the PE header after the DOS image header.
170 Hdr
.Pe32
= (EFI_IMAGE_NT_HEADERS32
*)(Pe32Data
+ (UINTN
) ((DosHdr
->e_lfanew
) & 0x0ffff));
172 // Make sure PE header address does not overflow and is less than the initial address.
174 if (((UINTN
)Hdr
.Pe32
> Pe32Data
) && ((UINTN
)Hdr
.Pe32
< CallerIpAddress
)) {
175 if (Hdr
.Pe32
->Signature
== EFI_IMAGE_NT_SIGNATURE
) {
185 // Not found the image base, check the previous aligned address
187 Pe32Data
-= SIZE_4KB
;
190 DumpIpAddress
= CallerIpAddress
;
191 DEBUG ((EFI_D_ERROR
, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress
));
194 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
195 if (PdbPointer
!= NULL
) {
196 DEBUG ((EFI_D_ERROR
, " in module (%a)", PdbPointer
));
202 Read information from the CPU save state.
204 @param This EFI_SMM_CPU_PROTOCOL instance
205 @param Width The number of bytes to read from the CPU save state.
206 @param Register Specifies the CPU register to read form the save state.
207 @param CpuIndex Specifies the zero-based index of the CPU save state.
208 @param Buffer Upon return, this holds the CPU register value read from the save state.
210 @retval EFI_SUCCESS The register was read from Save State
211 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
212 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
218 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
220 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
228 // Retrieve pointer to the specified CPU's SMM Save State buffer
230 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
231 return EFI_INVALID_PARAMETER
;
235 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
237 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
239 // The pseudo-register only supports the 64-bit size specified by Width.
241 if (Width
!= sizeof (UINT64
)) {
242 return EFI_INVALID_PARAMETER
;
245 // If the processor is in SMM at the time the SMI occurred,
246 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
247 // Otherwise, EFI_NOT_FOUND is returned.
249 if (*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
)) {
250 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
253 return EFI_NOT_FOUND
;
257 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
258 return EFI_INVALID_PARAMETER
;
261 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
262 if (Status
== EFI_UNSUPPORTED
) {
263 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
269 Write data to the CPU save state.
271 @param This EFI_SMM_CPU_PROTOCOL instance
272 @param Width The number of bytes to read from the CPU save state.
273 @param Register Specifies the CPU register to write to the save state.
274 @param CpuIndex Specifies the zero-based index of the CPU save state
275 @param Buffer Upon entry, this holds the new CPU register value.
277 @retval EFI_SUCCESS The register was written from Save State
278 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
279 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
285 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
287 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
289 IN CONST VOID
*Buffer
295 // Retrieve pointer to the specified CPU's SMM Save State buffer
297 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
298 return EFI_INVALID_PARAMETER
;
302 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
304 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
308 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
309 return EFI_INVALID_PARAMETER
;
312 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
313 if (Status
== EFI_UNSUPPORTED
) {
314 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
321 C function for SMI handler. To change all processor's SMMBase Register.
334 // Update SMM IDT entries' code segment and load IDT
336 AsmWriteIdtr (&gcSmiIdtr
);
337 ApicId
= GetApicId ();
339 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
341 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
342 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
344 // Initialize SMM specific features on the currently executing CPU
346 SmmCpuFeaturesInitializeProcessor (
349 gSmmCpuPrivate
->ProcessorInfo
,
355 // BSP rebase is already done above.
356 // Initialize private data during S3 resume
358 InitializeMpSyncData ();
362 // Hook return after RSM to set SMM re-based flag
364 SemaphoreHook (Index
, &mRebased
[Index
]);
373 Relocate SmmBases for each processor.
375 Execute on first boot and all S3 resumes
384 UINT8 BakBuf
[BACK_BUF_SIZE
];
385 SMRAM_SAVE_STATE_MAP BakBuf2
;
386 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
393 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
395 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
398 // Patch ASM code template with current CR0, CR3, and CR4 values
400 gSmmCr0
= (UINT32
)AsmReadCr0 ();
401 gSmmCr3
= (UINT32
)AsmReadCr3 ();
402 gSmmCr4
= (UINT32
)AsmReadCr4 ();
405 // Patch GDTR for SMM base relocation
407 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
408 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
410 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
411 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
414 // Backup original contents at address 0x38000
416 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
417 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
420 // Load image for relocation
422 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
425 // Retrieve the local APIC ID of current processor
427 ApicId
= GetApicId ();
430 // Relocate SM bases for all APs
431 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
434 BspIndex
= (UINTN
)-1;
435 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
436 mRebased
[Index
] = FALSE
;
437 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
438 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
440 // Wait for this AP to finish its 1st SMI
442 while (!mRebased
[Index
]);
445 // BSP will be Relocated later
452 // Relocate BSP's SMM base
454 ASSERT (BspIndex
!= (UINTN
)-1);
458 // Wait for the BSP to finish its 1st SMI
460 while (!mRebased
[BspIndex
]);
463 // Restore contents at address 0x38000
465 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
466 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
470 Perform SMM initialization for all processors in the S3 boot path.
472 For a native platform, MP initialization in the S3 boot path is also performed in this function.
480 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
481 IA32_DESCRIPTOR Ia32Idtr
;
482 IA32_DESCRIPTOR X64Idtr
;
483 IA32_IDT_GATE_DESCRIPTOR IdtEntryTable
[EXCEPTION_VECTOR_NUMBER
];
486 DEBUG ((EFI_D_INFO
, "SmmRestoreCpu()\n"));
488 InitializeSpinLock (mMemoryMappedLock
);
491 // See if there is enough context to resume PEI Phase
493 if (mSmmS3ResumeState
== NULL
) {
494 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
498 SmmS3ResumeState
= mSmmS3ResumeState
;
499 ASSERT (SmmS3ResumeState
!= NULL
);
501 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
503 // Save the IA32 IDT Descriptor
505 AsmReadIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
508 // Setup X64 IDT table
510 ZeroMem (IdtEntryTable
, sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32);
511 X64Idtr
.Base
= (UINTN
) IdtEntryTable
;
512 X64Idtr
.Limit
= (UINT16
) (sizeof (IA32_IDT_GATE_DESCRIPTOR
) * 32 - 1);
513 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &X64Idtr
);
516 // Setup the default exception handler
518 Status
= InitializeCpuExceptionHandlers (NULL
);
519 ASSERT_EFI_ERROR (Status
);
522 // Initialize Debug Agent to support source level debug
524 InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64
, (VOID
*)&Ia32Idtr
, NULL
);
528 // Skip initialization if mAcpiCpuData is not valid
530 if (mAcpiCpuData
.NumberOfCpus
> 0) {
532 // First time microcode load and restore MTRRs
534 EarlyInitializeCpu ();
538 // Restore SMBASE for BSP and all APs
543 // Skip initialization if mAcpiCpuData is not valid
545 if (mAcpiCpuData
.NumberOfCpus
> 0) {
547 // Restore MSRs for BSP and all APs
553 // Set a flag to restore SMM configuration in S3 path.
555 mRestoreSmmConfigurationInS3
= TRUE
;
557 DEBUG (( EFI_D_INFO
, "SMM S3 Return CS = %x\n", SmmS3ResumeState
->ReturnCs
));
558 DEBUG (( EFI_D_INFO
, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState
->ReturnEntryPoint
));
559 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState
->ReturnContext1
));
560 DEBUG (( EFI_D_INFO
, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState
->ReturnContext2
));
561 DEBUG (( EFI_D_INFO
, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState
->ReturnStackPointer
));
564 // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
566 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_32
) {
567 DEBUG ((EFI_D_INFO
, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));
570 (SWITCH_STACK_ENTRY_POINT
)(UINTN
)SmmS3ResumeState
->ReturnEntryPoint
,
571 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext1
,
572 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnContext2
,
573 (VOID
*)(UINTN
)SmmS3ResumeState
->ReturnStackPointer
578 // If SMM is in 64-bit mode, then use AsmDisablePaging64() to resume PEI Phase
580 if (SmmS3ResumeState
->Signature
== SMM_S3_RESUME_SMM_64
) {
581 DEBUG ((EFI_D_INFO
, "Call AsmDisablePaging64() to return to S3 Resume in PEI Phase\n"));
583 // Disable interrupt of Debug timer, since new IDT table is for IA32 and will not work in long mode.
585 SaveAndSetDebugTimerInterrupt (FALSE
);
587 // Restore IA32 IDT table
589 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &Ia32Idtr
);
591 SmmS3ResumeState
->ReturnCs
,
592 (UINT32
)SmmS3ResumeState
->ReturnEntryPoint
,
593 (UINT32
)SmmS3ResumeState
->ReturnContext1
,
594 (UINT32
)SmmS3ResumeState
->ReturnContext2
,
595 (UINT32
)SmmS3ResumeState
->ReturnStackPointer
600 // Can not resume PEI Phase
602 DEBUG ((EFI_D_ERROR
, "No context to return to PEI Phase\n"));
607 Copy register table from ACPI NVS memory into SMRAM.
609 @param[in] DestinationRegisterTableList Points to destination register table.
610 @param[in] SourceRegisterTableList Points to source register table.
611 @param[in] NumberOfCpus Number of CPUs.
616 IN CPU_REGISTER_TABLE
*DestinationRegisterTableList
,
617 IN CPU_REGISTER_TABLE
*SourceRegisterTableList
,
618 IN UINT32 NumberOfCpus
623 CPU_REGISTER_TABLE_ENTRY
*RegisterTableEntry
;
625 CopyMem (DestinationRegisterTableList
, SourceRegisterTableList
, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
626 for (Index
= 0; Index
< NumberOfCpus
; Index
++) {
627 DestinationRegisterTableList
[Index
].RegisterTableEntry
= AllocatePool (DestinationRegisterTableList
[Index
].AllocatedSize
);
628 ASSERT (DestinationRegisterTableList
[Index
].RegisterTableEntry
!= NULL
);
629 CopyMem (DestinationRegisterTableList
[Index
].RegisterTableEntry
, SourceRegisterTableList
[Index
].RegisterTableEntry
, DestinationRegisterTableList
[Index
].AllocatedSize
);
631 // Go though all MSRs in register table to initialize MSR spin lock
633 RegisterTableEntry
= DestinationRegisterTableList
[Index
].RegisterTableEntry
;
634 for (Index1
= 0; Index1
< DestinationRegisterTableList
[Index
].TableLength
; Index1
++, RegisterTableEntry
++) {
635 if ((RegisterTableEntry
->RegisterType
== Msr
) && (RegisterTableEntry
->ValidBitLength
< 64)) {
637 // Initialize MSR spin lock only for those MSRs need bit field writing
639 InitMsrSpinLockByIndex (RegisterTableEntry
->Index
);
646 SMM Ready To Lock event notification handler.
648 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
649 perform additional lock actions that must be performed from SMM on the next SMI.
651 @param[in] Protocol Points to the protocol's unique identifier.
652 @param[in] Interface Points to the interface instance.
653 @param[in] Handle The handle on which the interface was installed.
655 @retval EFI_SUCCESS Notification handler runs successfully.
659 SmmReadyToLockEventNotify (
660 IN CONST EFI_GUID
*Protocol
,
665 ACPI_CPU_DATA
*AcpiCpuData
;
666 IA32_DESCRIPTOR
*Gdtr
;
667 IA32_DESCRIPTOR
*Idtr
;
670 // Prevent use of mAcpiCpuData by initialize NumberOfCpus to 0
672 mAcpiCpuData
.NumberOfCpus
= 0;
675 // If PcdCpuS3DataAddress was never set, then do not copy CPU S3 Data into SMRAM
677 AcpiCpuData
= (ACPI_CPU_DATA
*)(UINTN
)PcdGet64 (PcdCpuS3DataAddress
);
678 if (AcpiCpuData
== 0) {
683 // For a native platform, copy the CPU S3 data into SMRAM for use on CPU S3 Resume.
685 CopyMem (&mAcpiCpuData
, AcpiCpuData
, sizeof (mAcpiCpuData
));
687 mAcpiCpuData
.MtrrTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (MTRR_SETTINGS
));
688 ASSERT (mAcpiCpuData
.MtrrTable
!= 0);
690 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.MtrrTable
, (VOID
*)(UINTN
)AcpiCpuData
->MtrrTable
, sizeof (MTRR_SETTINGS
));
692 mAcpiCpuData
.GdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
693 ASSERT (mAcpiCpuData
.GdtrProfile
!= 0);
695 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.GdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->GdtrProfile
, sizeof (IA32_DESCRIPTOR
));
697 mAcpiCpuData
.IdtrProfile
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (sizeof (IA32_DESCRIPTOR
));
698 ASSERT (mAcpiCpuData
.IdtrProfile
!= 0);
700 CopyMem ((VOID
*)(UINTN
)mAcpiCpuData
.IdtrProfile
, (VOID
*)(UINTN
)AcpiCpuData
->IdtrProfile
, sizeof (IA32_DESCRIPTOR
));
702 mAcpiCpuData
.PreSmmInitRegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
703 ASSERT (mAcpiCpuData
.PreSmmInitRegisterTable
!= 0);
706 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.PreSmmInitRegisterTable
,
707 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->PreSmmInitRegisterTable
,
708 mAcpiCpuData
.NumberOfCpus
711 mAcpiCpuData
.RegisterTable
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePool (mAcpiCpuData
.NumberOfCpus
* sizeof (CPU_REGISTER_TABLE
));
712 ASSERT (mAcpiCpuData
.RegisterTable
!= 0);
715 (CPU_REGISTER_TABLE
*)(UINTN
)mAcpiCpuData
.RegisterTable
,
716 (CPU_REGISTER_TABLE
*)(UINTN
)AcpiCpuData
->RegisterTable
,
717 mAcpiCpuData
.NumberOfCpus
721 // Copy AP's GDT, IDT and Machine Check handler into SMRAM.
723 Gdtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.GdtrProfile
;
724 Idtr
= (IA32_DESCRIPTOR
*)(UINTN
)mAcpiCpuData
.IdtrProfile
;
726 mGdtForAp
= AllocatePool ((Gdtr
->Limit
+ 1) + (Idtr
->Limit
+ 1) + mAcpiCpuData
.ApMachineCheckHandlerSize
);
727 ASSERT (mGdtForAp
!= NULL
);
728 mIdtForAp
= (VOID
*) ((UINTN
)mGdtForAp
+ (Gdtr
->Limit
+ 1));
729 mMachineCheckHandlerForAp
= (VOID
*) ((UINTN
)mIdtForAp
+ (Idtr
->Limit
+ 1));
731 CopyMem (mGdtForAp
, (VOID
*)Gdtr
->Base
, Gdtr
->Limit
+ 1);
732 CopyMem (mIdtForAp
, (VOID
*)Idtr
->Base
, Idtr
->Limit
+ 1);
733 CopyMem (mMachineCheckHandlerForAp
, (VOID
*)(UINTN
)mAcpiCpuData
.ApMachineCheckHandlerBase
, mAcpiCpuData
.ApMachineCheckHandlerSize
);
737 // Set SMM ready to lock flag and return
739 mSmmReadyToLock
= TRUE
;
744 The module Entry Point of the CPU SMM driver.
746 @param ImageHandle The firmware allocated handle for the EFI image.
747 @param SystemTable A pointer to the EFI System Table.
749 @retval EFI_SUCCESS The entry point is executed successfully.
750 @retval Other Some error occurs when executing this entry point.
756 IN EFI_HANDLE ImageHandle
,
757 IN EFI_SYSTEM_TABLE
*SystemTable
761 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
762 UINTN NumberOfEnabledProcessors
;
770 EFI_SMRAM_DESCRIPTOR
*SmramDescriptor
;
771 SMM_S3_RESUME_STATE
*SmmS3ResumeState
;
781 // Initialize Debug Agent to support source level debug in SMM code
783 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
786 // Report the start of CPU SMM initialization.
790 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
794 // Fix segment address of the long-mode-switch jump
796 if (sizeof (UINTN
) == sizeof (UINT64
)) {
797 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
801 // Find out SMRR Base and SMRR Size
803 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
806 // Get MP Services Protocol
808 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
809 ASSERT_EFI_ERROR (Status
);
812 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
814 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
815 ASSERT_EFI_ERROR (Status
);
816 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
819 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
820 // A constant BSP index makes no sense because it may be hot removed.
823 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
825 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
830 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
832 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
833 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
836 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
838 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
839 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
841 mMaxNumberOfCpus
= mNumberOfCpus
;
843 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
846 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
847 // allocated buffer. The minimum size of this buffer for a uniprocessor system
848 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
849 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
850 // then the SMI entry point and the CPU save state areas can be tiles to minimize
851 // the total amount SMRAM required for all the CPUs. The tile size can be computed
852 // by adding the // CPU save state size, any extra CPU specific context, and
853 // the size of code that must be placed at the SMI entry point to transfer
854 // control to a C function in the native SMM execution mode. This size is
855 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
856 // The total amount of memory required is the maximum number of CPUs that
857 // platform supports times the tile size. The picture below shows the tiling,
858 // where m is the number of tiles that fit in 32KB.
860 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
861 // | CPU m+1 Save State |
862 // +-----------------------------+
863 // | CPU m+1 Extra Data |
864 // +-----------------------------+
866 // +-----------------------------+
867 // | CPU 2m SMI Entry |
868 // +#############################+ <-- Base of allocated buffer + 64 KB
869 // | CPU m-1 Save State |
870 // +-----------------------------+
871 // | CPU m-1 Extra Data |
872 // +-----------------------------+
874 // +-----------------------------+
875 // | CPU 2m-1 SMI Entry |
876 // +=============================+ <-- 2^n offset from Base of allocated buffer
877 // | . . . . . . . . . . . . |
878 // +=============================+ <-- 2^n offset from Base of allocated buffer
879 // | CPU 2 Save State |
880 // +-----------------------------+
881 // | CPU 2 Extra Data |
882 // +-----------------------------+
884 // +-----------------------------+
885 // | CPU m+1 SMI Entry |
886 // +=============================+ <-- Base of allocated buffer + 32 KB
887 // | CPU 1 Save State |
888 // +-----------------------------+
889 // | CPU 1 Extra Data |
890 // +-----------------------------+
892 // +-----------------------------+
893 // | CPU m SMI Entry |
894 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
895 // | CPU 0 Save State |
896 // +-----------------------------+
897 // | CPU 0 Extra Data |
898 // +-----------------------------+
900 // +-----------------------------+
901 // | CPU m-1 SMI Entry |
902 // +=============================+ <-- 2^n offset from Base of allocated buffer
903 // | . . . . . . . . . . . . |
904 // +=============================+ <-- 2^n offset from Base of allocated buffer
906 // +-----------------------------+
907 // | CPU 1 SMI Entry |
908 // +=============================+ <-- 2^n offset from Base of allocated buffer
910 // +-----------------------------+
911 // | CPU 0 SMI Entry |
912 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
916 // Retrieve CPU Family
918 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
919 FamilyId
= (RegEax
>> 8) & 0xf;
920 ModelId
= (RegEax
>> 4) & 0xf;
921 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
922 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
926 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
927 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
928 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
931 // Determine the mode of the CPU at the time an SMI occurs
932 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
933 // Volume 3C, Section 34.4.1.1
935 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
936 if ((RegEdx
& BIT29
) != 0) {
937 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
939 if (FamilyId
== 0x06) {
940 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
941 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
946 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
947 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
948 // is rounded up to nearest power of 2.
950 TileCodeSize
= GetSmiHandlerSize ();
951 TileCodeSize
= ALIGN_VALUE(TileCodeSize
, SIZE_4KB
);
952 TileDataSize
= sizeof (SMRAM_SAVE_STATE_MAP
) + sizeof (PROCESSOR_SMM_DESCRIPTOR
);
953 TileDataSize
= ALIGN_VALUE(TileDataSize
, SIZE_4KB
);
954 TileSize
= TileDataSize
+ TileCodeSize
- 1;
955 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
956 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
959 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
960 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
961 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
964 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
967 // Allocate buffer for all of the tiles.
969 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
970 // Volume 3C, Section 34.11 SMBASE Relocation
971 // For Pentium and Intel486 processors, the SMBASE values must be
972 // aligned on a 32-KByte boundary or the processor will enter shutdown
973 // state during the execution of a RSM instruction.
975 // Intel486 processors: FamilyId is 4
976 // Pentium processors : FamilyId is 5
978 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
979 if ((FamilyId
== 4) || (FamilyId
== 5)) {
980 Buffer
= AllocateAlignedPages (BufferPages
, SIZE_32KB
);
982 Buffer
= AllocateAlignedPages (BufferPages
, SIZE_4KB
);
984 ASSERT (Buffer
!= NULL
);
985 DEBUG ((EFI_D_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE(BufferPages
)));
988 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
990 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
991 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
993 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
994 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
996 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
997 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
999 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
1000 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
1002 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
1003 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
1006 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
1008 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
1009 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
1010 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
1011 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
1012 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
1015 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
1016 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
1017 // size for each CPU in the platform
1019 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
1020 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
1021 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
1022 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
1023 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
1025 if (Index
< mNumberOfCpus
) {
1026 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
1027 ASSERT_EFI_ERROR (Status
);
1028 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
1030 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
1032 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
1033 mCpuHotPlugData
.SmBase
[Index
],
1034 gSmmCpuPrivate
->CpuSaveState
[Index
],
1035 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
1038 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
1039 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
1044 // Allocate SMI stacks for all processors.
1046 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
1048 // 2 more pages is allocated for each processor.
1049 // one is guard page and the other is known good stack.
1051 // +-------------------------------------------+-----+-------------------------------------------+
1052 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
1053 // +-------------------------------------------+-----+-------------------------------------------+
1055 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
1057 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
1058 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
1059 ASSERT (Stacks
!= NULL
);
1060 mSmmStackArrayBase
= (UINTN
)Stacks
;
1061 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
1063 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
1064 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
1065 ASSERT (Stacks
!= NULL
);
1069 // Set SMI stack for SMM base relocation
1071 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
1076 InitializeSmmIdt ();
1079 // Relocate SMM Base addresses to the ones allocated from SMRAM
1081 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
1082 ASSERT (mRebased
!= NULL
);
1083 SmmRelocateBases ();
1086 // Call hook for BSP to perform extra actions in normal mode after all
1087 // SMM base addresses have been relocated on all CPUs
1089 SmmCpuFeaturesSmmRelocationComplete ();
1092 // SMM Time initialization
1094 InitializeSmmTimer ();
1097 // Initialize MP globals
1099 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
1102 // Fill in SMM Reserved Regions
1104 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
1105 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
1108 // Install the SMM Configuration Protocol onto a new handle on the handle database.
1109 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
1110 // to an SMRAM address will be present in the handle database
1112 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
1113 &gSmmCpuPrivate
->SmmCpuHandle
,
1114 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
1117 ASSERT_EFI_ERROR (Status
);
1120 // Install the SMM CPU Protocol into SMM protocol database
1122 Status
= gSmst
->SmmInstallProtocolInterface (
1124 &gEfiSmmCpuProtocolGuid
,
1125 EFI_NATIVE_INTERFACE
,
1128 ASSERT_EFI_ERROR (Status
);
1131 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
1133 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
1134 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
1135 ASSERT_EFI_ERROR (Status
);
1139 // Initialize SMM CPU Services Support
1141 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
1142 ASSERT_EFI_ERROR (Status
);
1145 // register SMM Ready To Lock Protocol notification
1147 Status
= gSmst
->SmmRegisterProtocolNotify (
1148 &gEfiSmmReadyToLockProtocolGuid
,
1149 SmmReadyToLockEventNotify
,
1152 ASSERT_EFI_ERROR (Status
);
1154 GuidHob
= GetFirstGuidHob (&gEfiAcpiVariableGuid
);
1155 if (GuidHob
!= NULL
) {
1156 SmramDescriptor
= (EFI_SMRAM_DESCRIPTOR
*) GET_GUID_HOB_DATA (GuidHob
);
1158 DEBUG ((EFI_D_INFO
, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor
));
1159 DEBUG ((EFI_D_INFO
, "SMM S3 Structure = %x\n", SmramDescriptor
->CpuStart
));
1161 SmmS3ResumeState
= (SMM_S3_RESUME_STATE
*)(UINTN
)SmramDescriptor
->CpuStart
;
1162 ZeroMem (SmmS3ResumeState
, sizeof (SMM_S3_RESUME_STATE
));
1164 mSmmS3ResumeState
= SmmS3ResumeState
;
1165 SmmS3ResumeState
->Smst
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)gSmst
;
1167 SmmS3ResumeState
->SmmS3ResumeEntryPoint
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)SmmRestoreCpu
;
1169 SmmS3ResumeState
->SmmS3StackSize
= SIZE_32KB
;
1170 SmmS3ResumeState
->SmmS3StackBase
= (EFI_PHYSICAL_ADDRESS
)(UINTN
)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN
)SmmS3ResumeState
->SmmS3StackSize
));
1171 if (SmmS3ResumeState
->SmmS3StackBase
== 0) {
1172 SmmS3ResumeState
->SmmS3StackSize
= 0;
1175 SmmS3ResumeState
->SmmS3Cr0
= gSmmCr0
;
1176 SmmS3ResumeState
->SmmS3Cr3
= Cr3
;
1177 SmmS3ResumeState
->SmmS3Cr4
= gSmmCr4
;
1179 if (sizeof (UINTN
) == sizeof (UINT64
)) {
1180 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_64
;
1182 if (sizeof (UINTN
) == sizeof (UINT32
)) {
1183 SmmS3ResumeState
->Signature
= SMM_S3_RESUME_SMM_32
;
1188 // Check XD and BTS features
1190 CheckProcessorFeature ();
1193 // Initialize SMM Profile feature
1195 InitSmmProfile (Cr3
);
1198 // Patch SmmS3ResumeState->SmmS3Cr3
1202 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
1209 Find out SMRAM information including SMRR base and SMRR size.
1211 @param SmrrBase SMRR base
1212 @param SmrrSize SMRR size
1217 OUT UINT32
*SmrrBase
,
1218 OUT UINT32
*SmrrSize
1223 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
1224 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
1225 EFI_SMRAM_DESCRIPTOR
*SmramRanges
;
1226 UINTN SmramRangeCount
;
1232 // Get SMM Access Protocol
1234 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
1235 ASSERT_EFI_ERROR (Status
);
1238 // Get SMRAM information
1241 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
1242 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
1244 SmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
1245 ASSERT (SmramRanges
!= NULL
);
1247 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, SmramRanges
);
1248 ASSERT_EFI_ERROR (Status
);
1250 SmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
1253 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
1255 CurrentSmramRange
= NULL
;
1256 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< SmramRangeCount
; Index
++) {
1258 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
1260 if ((SmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
1264 if (SmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
1265 if ((SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
) <= BASE_4GB
) {
1266 if (SmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
1267 MaxSize
= SmramRanges
[Index
].PhysicalSize
;
1268 CurrentSmramRange
= &SmramRanges
[Index
];
1274 ASSERT (CurrentSmramRange
!= NULL
);
1276 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
1277 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
1281 for (Index
= 0; Index
< SmramRangeCount
; Index
++) {
1282 if (SmramRanges
[Index
].CpuStart
< *SmrrBase
&& *SmrrBase
== (SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
)) {
1283 *SmrrBase
= (UINT32
)SmramRanges
[Index
].CpuStart
;
1284 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1286 } else if ((*SmrrBase
+ *SmrrSize
) == SmramRanges
[Index
].CpuStart
&& SmramRanges
[Index
].PhysicalSize
> 0) {
1287 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1293 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1297 Configure SMM Code Access Check feature on an AP.
1298 SMM Feature Control MSR will be locked after configuration.
1300 @param[in,out] Buffer Pointer to private data buffer.
1304 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1309 UINT64 SmmFeatureControlMsr
;
1310 UINT64 NewSmmFeatureControlMsr
;
1313 // Retrieve the CPU Index from the context passed in
1315 CpuIndex
= *(UINTN
*)Buffer
;
1318 // Get the current SMM Feature Control MSR value
1320 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1323 // Compute the new SMM Feature Control MSR value
1325 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1326 if (mSmmCodeAccessCheckEnable
) {
1327 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1328 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1329 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1334 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1336 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1337 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1341 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1343 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1347 Configure SMM Code Access Check feature for all processors.
1348 SMM Feature Control MSR will be locked after configuration.
1351 ConfigSmmCodeAccessCheck (
1359 // Check to see if the Feature Control MSR is supported on this CPU
1361 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1362 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1363 mSmmCodeAccessCheckEnable
= FALSE
;
1368 // Check to see if the CPU supports the SMM Code Access Check feature
1369 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1371 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1372 mSmmCodeAccessCheckEnable
= FALSE
;
1377 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1379 InitializeSpinLock (mConfigSmmCodeAccessCheckLock
);
1382 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1383 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1385 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1388 // Enable SMM Code Access Check feature on the BSP.
1390 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1393 // Enable SMM Code Access Check feature for the APs.
1395 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1396 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1399 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1400 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1402 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1405 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1407 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1408 ASSERT_EFI_ERROR (Status
);
1411 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1413 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock
)) {
1418 // Release the Config SMM Code Access Check spin lock.
1420 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1426 This API provides a way to allocate memory for page table.
1428 This API can be called more once to allocate memory for page tables.
1430 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1431 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1432 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1435 @param Pages The number of 4 KB pages to allocate.
1437 @return A pointer to the allocated buffer or NULL if allocation fails.
1441 AllocatePageTableMemory (
1447 Buffer
= SmmCpuFeaturesAllocatePageTableMemory (Pages
);
1448 if (Buffer
!= NULL
) {
1451 return AllocatePages (Pages
);
1455 Perform the remaining tasks.
1459 PerformRemainingTasks (
1463 if (mSmmReadyToLock
) {
1465 // Start SMM Profile feature
1467 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1471 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1475 // Configure SMM Code Access Check feature if available.
1477 ConfigSmmCodeAccessCheck ();
1479 SmmCpuFeaturesCompleteSmmReadyToLock ();
1482 // Clean SMM ready to lock flag
1484 mSmmReadyToLock
= FALSE
;
1489 Perform the pre tasks.
1498 // Restore SMM Configuration in S3 boot path.
1500 if (mRestoreSmmConfigurationInS3
) {
1502 // Need make sure gSmst is correct because below function may use them.
1504 gSmst
->SmmStartupThisAp
= gSmmCpuPrivate
->SmmCoreEntryContext
.SmmStartupThisAp
;
1505 gSmst
->CurrentlyExecutingCpu
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1506 gSmst
->NumberOfCpus
= gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
;
1507 gSmst
->CpuSaveStateSize
= gSmmCpuPrivate
->SmmCoreEntryContext
.CpuSaveStateSize
;
1508 gSmst
->CpuSaveState
= gSmmCpuPrivate
->SmmCoreEntryContext
.CpuSaveState
;
1511 // Configure SMM Code Access Check feature if available.
1513 ConfigSmmCodeAccessCheck ();
1515 SmmCpuFeaturesCompleteSmmReadyToLock ();
1517 mRestoreSmmConfigurationInS3
= FALSE
;