UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28
  29 #include <Library/BaseLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32 #include <Library/SynchronizationLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/PcdLib.h>
  36 #include <Library/CacheMaintenanceLib.h>
  37 #include <Library/MtrrLib.h>
  38 #include <Library/SmmCpuPlatformHookLib.h>
  39 #include <Library/SmmServicesTableLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/UefiRuntimeServicesTableLib.h>
  43 #include <Library/DebugAgentLib.h>
  44 #include <Library/HobLib.h>
  45 #include <Library/LocalApicLib.h>
  46 #include <Library/UefiCpuLib.h>
  47 #include <Library/CpuExceptionHandlerLib.h>
  48 #include <Library/ReportStatusCodeLib.h>
  49 #include <Library/SmmCpuFeaturesLib.h>
  50 #include <Library/PeCoffGetEntryPointLib.h>
  51
  52 #include <AcpiCpuData.h>
  53 #include <CpuHotPlugData.h>
  54
  55 #include <Register/Cpuid.h>
  56
  57 #include "CpuService.h"
  58 #include "SmmProfile.h"
  59
  60 //
  61 // MSRs required for configuration of SMM Code Access Check
  62 //
  63 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  64 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  65
  66 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  67 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  68
  69 ///
  70 /// Page Table Entry
  71 ///
  72 #define IA32_PG_P                   BIT0
  73 #define IA32_PG_RW                  BIT1
  74 #define IA32_PG_U                   BIT2
  75 #define IA32_PG_WT                  BIT3
  76 #define IA32_PG_CD                  BIT4
  77 #define IA32_PG_A                   BIT5
  78 #define IA32_PG_D                   BIT6
  79 #define IA32_PG_PS                  BIT7
  80 #define IA32_PG_PAT_2M              BIT12
  81 #define IA32_PG_PAT_4K              IA32_PG_PS
  82 #define IA32_PG_PMNT                BIT62
  83 #define IA32_PG_NX                  BIT63
  84
  85 #define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)
  86
  87 //
  88 // Size of Task-State Segment defined in IA32 Manual
  89 //
  90 #define TSS_SIZE              104
  91 #define TSS_X64_IST1_OFFSET   36
  92 #define TSS_IA32_CR3_OFFSET   28
  93 #define TSS_IA32_ESP_OFFSET   56
  94
  95 //
  96 // Code select value
  97 //
  98 #define PROTECT_MODE_CODE_SEGMENT          0x08
  99 #define LONG_MODE_CODE_SEGMENT             0x38
 100
 101 //
 102 // The size 0x20 must be bigger than
 103 // the size of template code of SmmInit. Currently,
 104 // the size of SmmInit requires the 0x16 Bytes buffer
 105 // at least.
 106 //
 107 #define BACK_BUF_SIZE  0x20
 108
 109 #define EXCEPTION_VECTOR_NUMBER     0x20
 110
 111 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 112
 113 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 114 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 115 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 116 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 117
 118 //
 119 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 120 // Contains the SMM Configuration Protocols that is produced.
 121 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 122 //
 123 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 124
 125 typedef struct {
 126   UINTN                           Signature;
 127
 128   EFI_HANDLE                      SmmCpuHandle;
 129
 130   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 131   SMM_CPU_OPERATION               *Operation;
 132   UINTN                           *CpuSaveStateSize;
 133   VOID                            **CpuSaveState;
 134
 135   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 136   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 137   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 138
 139   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 140 } SMM_CPU_PRIVATE_DATA;
 141
 142 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 143 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 144 extern UINTN                  mMaxNumberOfCpus;
 145 extern UINTN                  mNumberOfCpus;
 146 extern BOOLEAN                mRestoreSmmConfigurationInS3;
 147 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 148
 149 ///
 150 /// The mode of the CPU at the time an SMI occurs
 151 ///
 152 extern UINT8  mSmmSaveStateRegisterLma;
 153
 154
 155 //
 156 // SMM CPU Protocol function prototypes.
 157 //
 158
 159 /**
 160   Read information from the CPU save state.
 161
 162   @param  This      EFI_SMM_CPU_PROTOCOL instance
 163   @param  Width     The number of bytes to read from the CPU save state.
 164   @param  Register  Specifies the CPU register to read form the save state.
 165   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 166   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 167
 168   @retval EFI_SUCCESS   The register was read from Save State
 169   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 170   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 171
 172 **/
 173 EFI_STATUS
 174 EFIAPI
 175 SmmReadSaveState (
 176   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 177   IN UINTN                              Width,
 178   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 179   IN UINTN                              CpuIndex,
 180   OUT VOID                              *Buffer
 181   );
 182
 183 /**
 184   Write data to the CPU save state.
 185
 186   @param  This      EFI_SMM_CPU_PROTOCOL instance
 187   @param  Width     The number of bytes to read from the CPU save state.
 188   @param  Register  Specifies the CPU register to write to the save state.
 189   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 190   @param  Buffer    Upon entry, this holds the new CPU register value.
 191
 192   @retval EFI_SUCCESS   The register was written from Save State
 193   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 194   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 195
 196 **/
 197 EFI_STATUS
 198 EFIAPI
 199 SmmWriteSaveState (
 200   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 201   IN UINTN                              Width,
 202   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 203   IN UINTN                              CpuIndex,
 204   IN CONST VOID                         *Buffer
 205   );
 206
 207 /**
 208 Read a CPU Save State register on the target processor.
 209
 210 This function abstracts the differences that whether the CPU Save State register is in the
 211 IA32 CPU Save State Map or X64 CPU Save State Map.
 212
 213 This function supports reading a CPU Save State register in SMBase relocation handler.
 214
 215 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 216 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 217 @param[in]  Width          The number of bytes to read from the CPU save state.
 218 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 219
 220 @retval EFI_SUCCESS           The register was read from Save State.
 221 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 222 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 223
 224 **/
 225 EFI_STATUS
 226 EFIAPI
 227 ReadSaveStateRegister (
 228   IN UINTN                        CpuIndex,
 229   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 230   IN UINTN                        Width,
 231   OUT VOID                        *Buffer
 232   );
 233
 234 /**
 235 Write value to a CPU Save State register on the target processor.
 236
 237 This function abstracts the differences that whether the CPU Save State register is in the
 238 IA32 CPU Save State Map or X64 CPU Save State Map.
 239
 240 This function supports writing a CPU Save State register in SMBase relocation handler.
 241
 242 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 243 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 244 @param[in] Width          The number of bytes to read from the CPU save state.
 245 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 246
 247 @retval EFI_SUCCESS           The register was written to Save State.
 248 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 249 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 250
 251 **/
 252 EFI_STATUS
 253 EFIAPI
 254 WriteSaveStateRegister (
 255   IN UINTN                        CpuIndex,
 256   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 257   IN UINTN                        Width,
 258   IN CONST VOID                   *Buffer
 259   );
 260
 261 //
 262 //
 263 //
 264 typedef struct {
 265   UINT32                            Offset;
 266   UINT16                            Segment;
 267   UINT16                            Reserved;
 268 } IA32_FAR_ADDRESS;
 269
 270 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 271
 272 extern CONST UINT8                  gcSmmInitTemplate[];
 273 extern CONST UINT16                 gcSmmInitSize;
 274 extern UINT32                       gSmmCr0;
 275 extern UINT32                       gSmmCr3;
 276 extern UINT32                       gSmmCr4;
 277 extern UINTN                        gSmmInitStack;
 278
 279 /**
 280   Semaphore operation for all processor relocate SMMBase.
 281 **/
 282 VOID
 283 EFIAPI
 284 SmmRelocationSemaphoreComplete (
 285   VOID
 286   );
 287
 288 ///
 289 /// The type of SMM CPU Information
 290 ///
 291 typedef struct {
 292   SPIN_LOCK                         Busy;
 293   volatile EFI_AP_PROCEDURE         Procedure;
 294   volatile VOID                     *Parameter;
 295   volatile UINT32                   Run;
 296   volatile BOOLEAN                  Present;
 297 } SMM_CPU_DATA_BLOCK;
 298
 299 typedef enum {
 300   SmmCpuSyncModeTradition,
 301   SmmCpuSyncModeRelaxedAp,
 302   SmmCpuSyncModeMax
 303 } SMM_CPU_SYNC_MODE;
 304
 305 typedef struct {
 306   //
 307   // Pointer to an array. The array should be located immediately after this structure
 308   // so that UC cache-ability can be set together.
 309   //
 310   SMM_CPU_DATA_BLOCK            *CpuData;
 311   volatile UINT32               Counter;
 312   volatile UINT32               BspIndex;
 313   volatile BOOLEAN              InsideSmm;
 314   volatile BOOLEAN              AllCpusInSync;
 315   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 316   volatile BOOLEAN              SwitchBsp;
 317   volatile BOOLEAN              *CandidateBsp;
 318 } SMM_DISPATCHER_MP_SYNC_DATA;
 319
 320 typedef struct {
 321   SPIN_LOCK    SpinLock;
 322   UINT32       MsrIndex;
 323 } MP_MSR_LOCK;
 324
 325 #define SMM_PSD_OFFSET              0xfb00
 326
 327 typedef struct {
 328   UINT64                            Signature;              // Offset 0x00
 329   UINT16                            Reserved1;              // Offset 0x08
 330   UINT16                            Reserved2;              // Offset 0x0A
 331   UINT16                            Reserved3;              // Offset 0x0C
 332   UINT16                            SmmCs;                  // Offset 0x0E
 333   UINT16                            SmmDs;                  // Offset 0x10
 334   UINT16                            SmmSs;                  // Offset 0x12
 335   UINT16                            SmmOtherSegment;        // Offset 0x14
 336   UINT16                            Reserved4;              // Offset 0x16
 337   UINT64                            Reserved5;              // Offset 0x18
 338   UINT64                            Reserved6;              // Offset 0x20
 339   UINT64                            Reserved7;              // Offset 0x28
 340   UINT64                            SmmGdtPtr;              // Offset 0x30
 341   UINT32                            SmmGdtSize;             // Offset 0x38
 342   UINT32                            Reserved8;              // Offset 0x3C
 343   UINT64                            Reserved9;              // Offset 0x40
 344   UINT64                            Reserved10;             // Offset 0x48
 345   UINT16                            Reserved11;             // Offset 0x50
 346   UINT16                            Reserved12;             // Offset 0x52
 347   UINT32                            Reserved13;             // Offset 0x54
 348   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 349 } PROCESSOR_SMM_DESCRIPTOR;
 350
 351 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 352 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 353 extern VOID                                *gcSmiIdtrPtr;
 354 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 355 extern UINT64                              gPhyMask;
 356 extern ACPI_CPU_DATA                       mAcpiCpuData;
 357 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 358 extern VOID                                *mGdtForAp;
 359 extern VOID                                *mIdtForAp;
 360 extern VOID                                *mMachineCheckHandlerForAp;
 361 extern UINTN                               mSmmStackArrayBase;
 362 extern UINTN                               mSmmStackArrayEnd;
 363 extern UINTN                               mSmmStackSize;
 364 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 365 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 366
 367 /**
 368   Create 4G PageTable in SMRAM.
 369
 370   @param          ExtraPages       Additional page numbers besides for 4G memory
 371   @return         PageTable Address
 372
 373 **/
 374 UINT32
 375 Gen4GPageTable (
 376   IN      UINTN                     ExtraPages
 377   );
 378
 379
 380 /**
 381   Initialize global data for MP synchronization.
 382
 383   @param Stacks       Base address of SMI stack buffer for all processors.
 384   @param StackSize    Stack size for each processor in SMM.
 385
 386 **/
 387 UINT32
 388 InitializeMpServiceData (
 389   IN VOID        *Stacks,
 390   IN UINTN       StackSize
 391   );
 392
 393 /**
 394   Initialize Timer for SMM AP Sync.
 395
 396 **/
 397 VOID
 398 InitializeSmmTimer (
 399   VOID
 400   );
 401
 402 /**
 403   Start Timer for SMM AP Sync.
 404
 405 **/
 406 UINT64
 407 EFIAPI
 408 StartSyncTimer (
 409   VOID
 410   );
 411
 412 /**
 413   Check if the SMM AP Sync timer is timeout.
 414
 415   @param Timer  The start timer from the begin.
 416
 417 **/
 418 BOOLEAN
 419 EFIAPI
 420 IsSyncTimerTimeout (
 421   IN      UINT64                    Timer
 422   );
 423
 424 /**
 425   Initialize IDT for SMM Stack Guard.
 426
 427 **/
 428 VOID
 429 EFIAPI
 430 InitializeIDTSmmStackGuard (
 431   VOID
 432   );
 433
 434 /**
 435   Initialize Gdt for all processors.
 436
 437   @param[in]   Cr3          CR3 value.
 438   @param[out]  GdtStepSize  The step size for GDT table.
 439
 440   @return GdtBase for processor 0.
 441           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 442 **/
 443 VOID *
 444 InitGdt (
 445   IN  UINTN  Cr3,
 446   OUT UINTN  *GdtStepSize
 447   );
 448
 449 /**
 450
 451   Register the SMM Foundation entry point.
 452
 453   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 454   @param          SmmEntryPoint     SMM Foundation EntryPoint
 455
 456   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 457
 458 **/
 459 EFI_STATUS
 460 EFIAPI
 461 RegisterSmmEntry (
 462   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 463   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 464   );
 465
 466 /**
 467   Create PageTable for SMM use.
 468
 469   @return     PageTable Address
 470
 471 **/
 472 UINT32
 473 SmmInitPageTable (
 474   VOID
 475   );
 476
 477 /**
 478   Schedule a procedure to run on the specified CPU.
 479
 480   @param   Procedure        The address of the procedure to run
 481   @param   CpuIndex         Target CPU number
 482   @param   ProcArguments    The parameter to pass to the procedure
 483
 484   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 485   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 486   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 487   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 488   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 489
 490 **/
 491 EFI_STATUS
 492 EFIAPI
 493 SmmStartupThisAp (
 494   IN      EFI_AP_PROCEDURE          Procedure,
 495   IN      UINTN                     CpuIndex,
 496   IN OUT  VOID                      *ProcArguments OPTIONAL
 497   );
 498
 499 /**
 500   Schedule a procedure to run on the specified CPU in a blocking fashion.
 501
 502   @param  Procedure                The address of the procedure to run
 503   @param  CpuIndex                 Target CPU Index
 504   @param  ProcArguments            The parameter to pass to the procedure
 505
 506   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 507   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 508   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 509   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 510   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 511
 512 **/
 513 EFI_STATUS
 514 EFIAPI
 515 SmmBlockingStartupThisAp (
 516   IN      EFI_AP_PROCEDURE          Procedure,
 517   IN      UINTN                     CpuIndex,
 518   IN OUT  VOID                      *ProcArguments OPTIONAL
 519   );
 520
 521 /**
 522   Initialize MP synchronization data.
 523
 524 **/
 525 VOID
 526 EFIAPI
 527 InitializeMpSyncData (
 528   VOID
 529   );
 530
 531 /**
 532
 533   Find out SMRAM information including SMRR base and SMRR size.
 534
 535   @param          SmrrBase          SMRR base
 536   @param          SmrrSize          SMRR size
 537
 538 **/
 539 VOID
 540 FindSmramInfo (
 541   OUT UINT32   *SmrrBase,
 542   OUT UINT32   *SmrrSize
 543   );
 544
 545 /**
 546   The function is invoked before SMBASE relocation in S3 path to restores CPU status.
 547
 548   The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
 549   and restores MTRRs for both BSP and APs.
 550
 551 **/
 552 VOID
 553 EarlyInitializeCpu (
 554   VOID
 555   );
 556
 557 /**
 558   The function is invoked after SMBASE relocation in S3 path to restores CPU status.
 559
 560   The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
 561   data saved by normal boot path for both BSP and APs.
 562
 563 **/
 564 VOID
 565 InitializeCpu (
 566   VOID
 567   );
 568
 569 /**
 570   Page Fault handler for SMM use.
 571
 572   @param  InterruptType    Defines the type of interrupt or exception that
 573                            occurred on the processor.This parameter is processor architecture specific.
 574   @param  SystemContext    A pointer to the processor context when
 575                            the interrupt occurred on the processor.
 576 **/
 577 VOID
 578 EFIAPI
 579 SmiPFHandler (
 580     IN EFI_EXCEPTION_TYPE   InterruptType,
 581     IN EFI_SYSTEM_CONTEXT   SystemContext
 582   );
 583
 584 /**
 585   Perform the remaining tasks.
 586
 587 **/
 588 VOID
 589 PerformRemainingTasks (
 590   VOID
 591   );
 592
 593 /**
 594   Perform the pre tasks.
 595
 596 **/
 597 VOID
 598 PerformPreTasks (
 599   VOID
 600   );
 601
 602 /**
 603   Initialize MSR spin lock by MSR index.
 604
 605   @param  MsrIndex       MSR index value.
 606
 607 **/
 608 VOID
 609 InitMsrSpinLockByIndex (
 610   IN UINT32      MsrIndex
 611   );
 612
 613 /**
 614   Hook return address of SMM Save State so that semaphore code
 615   can be executed immediately after AP exits SMM to indicate to
 616   the BSP that an AP has exited SMM after SMBASE relocation.
 617
 618   @param[in] CpuIndex     The processor index.
 619   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 620                           immediately after AP exits SMM.
 621
 622 **/
 623 VOID
 624 SemaphoreHook (
 625   IN UINTN             CpuIndex,
 626   IN volatile BOOLEAN  *RebasedFlag
 627   );
 628
 629 /**
 630 Configure SMM Code Access Check feature for all processors.
 631 SMM Feature Control MSR will be locked after configuration.
 632 **/
 633 VOID
 634 ConfigSmmCodeAccessCheck (
 635   VOID
 636   );
 637
 638 /**
 639   Hook the code executed immediately after an RSM instruction on the currently
 640   executing CPU.  The mode of code executed immediately after RSM must be
 641   detected, and the appropriate hook must be selected.  Always clear the auto
 642   HALT restart flag if it is set.
 643
 644   @param[in] CpuIndex                 The processor index for the currently
 645                                       executing CPU.
 646   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 647                                       currently executing CPU.
 648   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 649                                       32-bit mode from 64-bit SMM.
 650   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 651                                       same mode as SMM.
 652
 653   @retval The value of the original instruction pointer before it was hooked.
 654
 655 **/
 656 UINT64
 657 EFIAPI
 658 HookReturnFromSmm (
 659   IN UINTN              CpuIndex,
 660   SMRAM_SAVE_STATE_MAP  *CpuState,
 661   UINT64                NewInstructionPointer32,
 662   UINT64                NewInstructionPointer
 663   );
 664
 665 /**
 666   Get the size of the SMI Handler in bytes.
 667
 668   @retval The size, in bytes, of the SMI Handler.
 669
 670 **/
 671 UINTN
 672 EFIAPI
 673 GetSmiHandlerSize (
 674   VOID
 675   );
 676
 677 /**
 678   Install the SMI handler for the CPU specified by CpuIndex.  This function
 679   is called by the CPU that was elected as monarch during System Management
 680   Mode initialization.
 681
 682   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 683                         The value must be between 0 and the NumberOfCpus field
 684                         in the System Management System Table (SMST).
 685   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 686   @param[in] SmiStack   The stack to use when an SMI is processed by the
 687                         the CPU specified by CpuIndex.
 688   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 689                         processed by the CPU specified by CpuIndex.
 690   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 691                         processed by the CPU specified by CpuIndex.
 692   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 693                         processed by the CPU specified by CpuIndex.
 694   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 695                         processed by the CPU specified by CpuIndex.
 696   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 697                         processed by the CPU specified by CpuIndex.
 698   @param[in] Cr3        The base address of the page tables to use when an SMI
 699                         is processed by the CPU specified by CpuIndex.
 700 **/
 701 VOID
 702 EFIAPI
 703 InstallSmiHandler (
 704   IN UINTN   CpuIndex,
 705   IN UINT32  SmBase,
 706   IN VOID    *SmiStack,
 707   IN UINTN   StackSize,
 708   IN UINTN   GdtBase,
 709   IN UINTN   GdtSize,
 710   IN UINTN   IdtBase,
 711   IN UINTN   IdtSize,
 712   IN UINT32  Cr3
 713   );
 714
 715 /**
 716   Search module name by input IP address and output it.
 717
 718   @param CallerIpAddress   Caller instruction pointer.
 719
 720 **/
 721 VOID
 722 DumpModuleInfoByIp (
 723   IN  UINTN              CallerIpAddress
 724   );
 725
 726 /**
 727   This API provides a way to allocate memory for page table.
 728
 729   This API can be called more once to allocate memory for page tables.
 730
 731   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 732   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 733   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 734   returned.
 735
 736   @param  Pages                 The number of 4 KB pages to allocate.
 737
 738   @return A pointer to the allocated buffer or NULL if allocation fails.
 739
 740 **/
 741 VOID *
 742 AllocatePageTableMemory (
 743   IN UINTN           Pages
 744   );
 745
 746 #endif