UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28
  29 #include <Library/BaseLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32 #include <Library/SynchronizationLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/PcdLib.h>
  36 #include <Library/CacheMaintenanceLib.h>
  37 #include <Library/MtrrLib.h>
  38 #include <Library/SmmCpuPlatformHookLib.h>
  39 #include <Library/SmmServicesTableLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/UefiRuntimeServicesTableLib.h>
  43 #include <Library/DebugAgentLib.h>
  44 #include <Library/HobLib.h>
  45 #include <Library/LocalApicLib.h>
  46 #include <Library/UefiCpuLib.h>
  47 #include <Library/CpuExceptionHandlerLib.h>
  48 #include <Library/ReportStatusCodeLib.h>
  49 #include <Library/SmmCpuFeaturesLib.h>
  50 #include <Library/PeCoffGetEntryPointLib.h>
  51
  52 #include <AcpiCpuData.h>
  53 #include <CpuHotPlugData.h>
  54
  55 #include <Register/Cpuid.h>
  56 #include <Register/Msr.h>
  57
  58 #include "CpuService.h"
  59 #include "SmmProfile.h"
  60
  61 //
  62 // MSRs required for configuration of SMM Code Access Check
  63 //
  64 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  65 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  66
  67 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  68 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  69
  70 ///
  71 /// Page Table Entry
  72 ///
  73 #define IA32_PG_P                   BIT0
  74 #define IA32_PG_RW                  BIT1
  75 #define IA32_PG_U                   BIT2
  76 #define IA32_PG_WT                  BIT3
  77 #define IA32_PG_CD                  BIT4
  78 #define IA32_PG_A                   BIT5
  79 #define IA32_PG_D                   BIT6
  80 #define IA32_PG_PS                  BIT7
  81 #define IA32_PG_PAT_2M              BIT12
  82 #define IA32_PG_PAT_4K              IA32_PG_PS
  83 #define IA32_PG_PMNT                BIT62
  84 #define IA32_PG_NX                  BIT63
  85
  86 #define PAGE_ATTRIBUTE_BITS         (IA32_PG_RW | IA32_PG_P)
  87 //
  88 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
  89 // X64 PAE PDPTE does not have such restriction
  90 //
  91 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)
  92
  93 //
  94 // Size of Task-State Segment defined in IA32 Manual
  95 //
  96 #define TSS_SIZE              104
  97 #define TSS_X64_IST1_OFFSET   36
  98 #define TSS_IA32_CR3_OFFSET   28
  99 #define TSS_IA32_ESP_OFFSET   56
 100
 101 //
 102 // Code select value
 103 //
 104 #define PROTECT_MODE_CODE_SEGMENT          0x08
 105 #define LONG_MODE_CODE_SEGMENT             0x38
 106
 107 //
 108 // The size 0x20 must be bigger than
 109 // the size of template code of SmmInit. Currently,
 110 // the size of SmmInit requires the 0x16 Bytes buffer
 111 // at least.
 112 //
 113 #define BACK_BUF_SIZE  0x20
 114
 115 #define EXCEPTION_VECTOR_NUMBER     0x20
 116
 117 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 118
 119 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 120 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 121 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 122 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 123
 124 //
 125 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 126 // Contains the SMM Configuration Protocols that is produced.
 127 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 128 //
 129 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 130
 131 typedef struct {
 132   UINTN                           Signature;
 133
 134   EFI_HANDLE                      SmmCpuHandle;
 135
 136   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 137   SMM_CPU_OPERATION               *Operation;
 138   UINTN                           *CpuSaveStateSize;
 139   VOID                            **CpuSaveState;
 140
 141   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 142   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 143   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 144
 145   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 146 } SMM_CPU_PRIVATE_DATA;
 147
 148 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 149 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 150 extern UINTN                  mMaxNumberOfCpus;
 151 extern UINTN                  mNumberOfCpus;
 152 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 153
 154 ///
 155 /// The mode of the CPU at the time an SMI occurs
 156 ///
 157 extern UINT8  mSmmSaveStateRegisterLma;
 158
 159
 160 //
 161 // SMM CPU Protocol function prototypes.
 162 //
 163
 164 /**
 165   Read information from the CPU save state.
 166
 167   @param  This      EFI_SMM_CPU_PROTOCOL instance
 168   @param  Width     The number of bytes to read from the CPU save state.
 169   @param  Register  Specifies the CPU register to read form the save state.
 170   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 171   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 172
 173   @retval EFI_SUCCESS   The register was read from Save State
 174   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 175   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 176
 177 **/
 178 EFI_STATUS
 179 EFIAPI
 180 SmmReadSaveState (
 181   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 182   IN UINTN                              Width,
 183   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 184   IN UINTN                              CpuIndex,
 185   OUT VOID                              *Buffer
 186   );
 187
 188 /**
 189   Write data to the CPU save state.
 190
 191   @param  This      EFI_SMM_CPU_PROTOCOL instance
 192   @param  Width     The number of bytes to read from the CPU save state.
 193   @param  Register  Specifies the CPU register to write to the save state.
 194   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 195   @param  Buffer    Upon entry, this holds the new CPU register value.
 196
 197   @retval EFI_SUCCESS   The register was written from Save State
 198   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 199   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 200
 201 **/
 202 EFI_STATUS
 203 EFIAPI
 204 SmmWriteSaveState (
 205   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 206   IN UINTN                              Width,
 207   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 208   IN UINTN                              CpuIndex,
 209   IN CONST VOID                         *Buffer
 210   );
 211
 212 /**
 213 Read a CPU Save State register on the target processor.
 214
 215 This function abstracts the differences that whether the CPU Save State register is in the
 216 IA32 CPU Save State Map or X64 CPU Save State Map.
 217
 218 This function supports reading a CPU Save State register in SMBase relocation handler.
 219
 220 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 221 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 222 @param[in]  Width          The number of bytes to read from the CPU save state.
 223 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 224
 225 @retval EFI_SUCCESS           The register was read from Save State.
 226 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 227 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 228
 229 **/
 230 EFI_STATUS
 231 EFIAPI
 232 ReadSaveStateRegister (
 233   IN UINTN                        CpuIndex,
 234   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 235   IN UINTN                        Width,
 236   OUT VOID                        *Buffer
 237   );
 238
 239 /**
 240 Write value to a CPU Save State register on the target processor.
 241
 242 This function abstracts the differences that whether the CPU Save State register is in the
 243 IA32 CPU Save State Map or X64 CPU Save State Map.
 244
 245 This function supports writing a CPU Save State register in SMBase relocation handler.
 246
 247 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 248 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 249 @param[in] Width          The number of bytes to read from the CPU save state.
 250 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 251
 252 @retval EFI_SUCCESS           The register was written to Save State.
 253 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 254 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 255
 256 **/
 257 EFI_STATUS
 258 EFIAPI
 259 WriteSaveStateRegister (
 260   IN UINTN                        CpuIndex,
 261   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 262   IN UINTN                        Width,
 263   IN CONST VOID                   *Buffer
 264   );
 265
 266 //
 267 //
 268 //
 269 typedef struct {
 270   UINT32                            Offset;
 271   UINT16                            Segment;
 272   UINT16                            Reserved;
 273 } IA32_FAR_ADDRESS;
 274
 275 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 276
 277 extern CONST UINT8                  gcSmmInitTemplate[];
 278 extern CONST UINT16                 gcSmmInitSize;
 279 extern UINT32                       gSmmCr0;
 280 extern UINT32                       gSmmCr3;
 281 extern UINT32                       gSmmCr4;
 282 extern UINTN                        gSmmInitStack;
 283
 284 /**
 285   Semaphore operation for all processor relocate SMMBase.
 286 **/
 287 VOID
 288 EFIAPI
 289 SmmRelocationSemaphoreComplete (
 290   VOID
 291   );
 292
 293 ///
 294 /// The type of SMM CPU Information
 295 ///
 296 typedef struct {
 297   SPIN_LOCK                         *Busy;
 298   volatile EFI_AP_PROCEDURE         Procedure;
 299   volatile VOID                     *Parameter;
 300   volatile UINT32                   *Run;
 301   volatile BOOLEAN                  *Present;
 302 } SMM_CPU_DATA_BLOCK;
 303
 304 typedef enum {
 305   SmmCpuSyncModeTradition,
 306   SmmCpuSyncModeRelaxedAp,
 307   SmmCpuSyncModeMax
 308 } SMM_CPU_SYNC_MODE;
 309
 310 typedef struct {
 311   //
 312   // Pointer to an array. The array should be located immediately after this structure
 313   // so that UC cache-ability can be set together.
 314   //
 315   SMM_CPU_DATA_BLOCK            *CpuData;
 316   volatile UINT32               *Counter;
 317   volatile UINT32               BspIndex;
 318   volatile BOOLEAN              *InsideSmm;
 319   volatile BOOLEAN              *AllCpusInSync;
 320   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 321   volatile BOOLEAN              SwitchBsp;
 322   volatile BOOLEAN              *CandidateBsp;
 323 } SMM_DISPATCHER_MP_SYNC_DATA;
 324
 325 #define MSR_SPIN_LOCK_INIT_NUM 15
 326
 327 typedef struct {
 328   SPIN_LOCK    *SpinLock;
 329   UINT32       MsrIndex;
 330 } MP_MSR_LOCK;
 331
 332 #define SMM_PSD_OFFSET              0xfb00
 333
 334 typedef struct {
 335   UINT64                            Signature;              // Offset 0x00
 336   UINT16                            Reserved1;              // Offset 0x08
 337   UINT16                            Reserved2;              // Offset 0x0A
 338   UINT16                            Reserved3;              // Offset 0x0C
 339   UINT16                            SmmCs;                  // Offset 0x0E
 340   UINT16                            SmmDs;                  // Offset 0x10
 341   UINT16                            SmmSs;                  // Offset 0x12
 342   UINT16                            SmmOtherSegment;        // Offset 0x14
 343   UINT16                            Reserved4;              // Offset 0x16
 344   UINT64                            Reserved5;              // Offset 0x18
 345   UINT64                            Reserved6;              // Offset 0x20
 346   UINT64                            Reserved7;              // Offset 0x28
 347   UINT64                            SmmGdtPtr;              // Offset 0x30
 348   UINT32                            SmmGdtSize;             // Offset 0x38
 349   UINT32                            Reserved8;              // Offset 0x3C
 350   UINT64                            Reserved9;              // Offset 0x40
 351   UINT64                            Reserved10;             // Offset 0x48
 352   UINT16                            Reserved11;             // Offset 0x50
 353   UINT16                            Reserved12;             // Offset 0x52
 354   UINT32                            Reserved13;             // Offset 0x54
 355   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 356 } PROCESSOR_SMM_DESCRIPTOR;
 357
 358
 359 ///
 360 /// All global semaphores' pointer
 361 ///
 362 typedef struct {
 363   volatile UINT32      *Counter;
 364   volatile BOOLEAN     *InsideSmm;
 365   volatile BOOLEAN     *AllCpusInSync;
 366   SPIN_LOCK            *PFLock;
 367   SPIN_LOCK            *CodeAccessCheckLock;
 368   SPIN_LOCK            *MemoryMappedLock;
 369 } SMM_CPU_SEMAPHORE_GLOBAL;
 370
 371 ///
 372 /// All semaphores for each processor
 373 ///
 374 typedef struct {
 375   SPIN_LOCK                         *Busy;
 376   volatile UINT32                   *Run;
 377   volatile BOOLEAN                  *Present;
 378 } SMM_CPU_SEMAPHORE_CPU;
 379
 380 ///
 381 /// All MSRs semaphores' pointer and counter
 382 ///
 383 typedef struct {
 384   SPIN_LOCK            *Msr;
 385   UINTN                AvailableCounter;
 386 } SMM_CPU_SEMAPHORE_MSR;
 387
 388 ///
 389 /// All semaphores' information
 390 ///
 391 typedef struct {
 392   SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;
 393   SMM_CPU_SEMAPHORE_CPU             SemaphoreCpu;
 394   SMM_CPU_SEMAPHORE_MSR             SemaphoreMsr;
 395 } SMM_CPU_SEMAPHORES;
 396
 397 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 398 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 399 extern VOID                                *gcSmiIdtrPtr;
 400 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 401 extern UINT64                              gPhyMask;
 402 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 403 extern UINTN                               mSmmStackArrayBase;
 404 extern UINTN                               mSmmStackArrayEnd;
 405 extern UINTN                               mSmmStackSize;
 406 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 407 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 408 extern SMM_CPU_SEMAPHORES                  mSmmCpuSemaphores;
 409 extern UINTN                               mSemaphoreSize;
 410 extern SPIN_LOCK                           *mPFLock;
 411 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;
 412 extern SPIN_LOCK                           *mMemoryMappedLock;
 413
 414 /**
 415   Create 4G PageTable in SMRAM.
 416
 417   @param          ExtraPages       Additional page numbers besides for 4G memory
 418   @param          Is32BitPageTable Whether the page table is 32-bit PAE
 419   @return         PageTable Address
 420
 421 **/
 422 UINT32
 423 Gen4GPageTable (
 424   IN      UINTN                     ExtraPages,
 425   IN      BOOLEAN                   Is32BitPageTable
 426   );
 427
 428
 429 /**
 430   Initialize global data for MP synchronization.
 431
 432   @param Stacks       Base address of SMI stack buffer for all processors.
 433   @param StackSize    Stack size for each processor in SMM.
 434
 435 **/
 436 UINT32
 437 InitializeMpServiceData (
 438   IN VOID        *Stacks,
 439   IN UINTN       StackSize
 440   );
 441
 442 /**
 443   Initialize Timer for SMM AP Sync.
 444
 445 **/
 446 VOID
 447 InitializeSmmTimer (
 448   VOID
 449   );
 450
 451 /**
 452   Start Timer for SMM AP Sync.
 453
 454 **/
 455 UINT64
 456 EFIAPI
 457 StartSyncTimer (
 458   VOID
 459   );
 460
 461 /**
 462   Check if the SMM AP Sync timer is timeout.
 463
 464   @param Timer  The start timer from the begin.
 465
 466 **/
 467 BOOLEAN
 468 EFIAPI
 469 IsSyncTimerTimeout (
 470   IN      UINT64                    Timer
 471   );
 472
 473 /**
 474   Initialize IDT for SMM Stack Guard.
 475
 476 **/
 477 VOID
 478 EFIAPI
 479 InitializeIDTSmmStackGuard (
 480   VOID
 481   );
 482
 483 /**
 484   Initialize Gdt for all processors.
 485
 486   @param[in]   Cr3          CR3 value.
 487   @param[out]  GdtStepSize  The step size for GDT table.
 488
 489   @return GdtBase for processor 0.
 490           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 491 **/
 492 VOID *
 493 InitGdt (
 494   IN  UINTN  Cr3,
 495   OUT UINTN  *GdtStepSize
 496   );
 497
 498 /**
 499
 500   Register the SMM Foundation entry point.
 501
 502   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 503   @param          SmmEntryPoint     SMM Foundation EntryPoint
 504
 505   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 506
 507 **/
 508 EFI_STATUS
 509 EFIAPI
 510 RegisterSmmEntry (
 511   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 512   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 513   );
 514
 515 /**
 516   Create PageTable for SMM use.
 517
 518   @return     PageTable Address
 519
 520 **/
 521 UINT32
 522 SmmInitPageTable (
 523   VOID
 524   );
 525
 526 /**
 527   Schedule a procedure to run on the specified CPU.
 528
 529   @param   Procedure        The address of the procedure to run
 530   @param   CpuIndex         Target CPU number
 531   @param   ProcArguments    The parameter to pass to the procedure
 532
 533   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 534   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 535   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 536   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 537   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 538
 539 **/
 540 EFI_STATUS
 541 EFIAPI
 542 SmmStartupThisAp (
 543   IN      EFI_AP_PROCEDURE          Procedure,
 544   IN      UINTN                     CpuIndex,
 545   IN OUT  VOID                      *ProcArguments OPTIONAL
 546   );
 547
 548 /**
 549   Schedule a procedure to run on the specified CPU in a blocking fashion.
 550
 551   @param  Procedure                The address of the procedure to run
 552   @param  CpuIndex                 Target CPU Index
 553   @param  ProcArguments            The parameter to pass to the procedure
 554
 555   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 556   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 557   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 558   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 559   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 560
 561 **/
 562 EFI_STATUS
 563 EFIAPI
 564 SmmBlockingStartupThisAp (
 565   IN      EFI_AP_PROCEDURE          Procedure,
 566   IN      UINTN                     CpuIndex,
 567   IN OUT  VOID                      *ProcArguments OPTIONAL
 568   );
 569
 570 /**
 571   Initialize MP synchronization data.
 572
 573 **/
 574 VOID
 575 EFIAPI
 576 InitializeMpSyncData (
 577   VOID
 578   );
 579
 580 /**
 581
 582   Find out SMRAM information including SMRR base and SMRR size.
 583
 584   @param          SmrrBase          SMRR base
 585   @param          SmrrSize          SMRR size
 586
 587 **/
 588 VOID
 589 FindSmramInfo (
 590   OUT UINT32   *SmrrBase,
 591   OUT UINT32   *SmrrSize
 592   );
 593
 594 /**
 595   Relocate SmmBases for each processor.
 596
 597   Execute on first boot and all S3 resumes
 598
 599 **/
 600 VOID
 601 EFIAPI
 602 SmmRelocateBases (
 603   VOID
 604   );
 605
 606 /**
 607   Page Fault handler for SMM use.
 608
 609   @param  InterruptType    Defines the type of interrupt or exception that
 610                            occurred on the processor.This parameter is processor architecture specific.
 611   @param  SystemContext    A pointer to the processor context when
 612                            the interrupt occurred on the processor.
 613 **/
 614 VOID
 615 EFIAPI
 616 SmiPFHandler (
 617     IN EFI_EXCEPTION_TYPE   InterruptType,
 618     IN EFI_SYSTEM_CONTEXT   SystemContext
 619   );
 620
 621 /**
 622   Perform the remaining tasks.
 623
 624 **/
 625 VOID
 626 PerformRemainingTasks (
 627   VOID
 628   );
 629
 630 /**
 631   Perform the pre tasks.
 632
 633 **/
 634 VOID
 635 PerformPreTasks (
 636   VOID
 637   );
 638
 639 /**
 640   Initialize MSR spin lock by MSR index.
 641
 642   @param  MsrIndex       MSR index value.
 643
 644 **/
 645 VOID
 646 InitMsrSpinLockByIndex (
 647   IN UINT32      MsrIndex
 648   );
 649
 650 /**
 651   Hook return address of SMM Save State so that semaphore code
 652   can be executed immediately after AP exits SMM to indicate to
 653   the BSP that an AP has exited SMM after SMBASE relocation.
 654
 655   @param[in] CpuIndex     The processor index.
 656   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 657                           immediately after AP exits SMM.
 658
 659 **/
 660 VOID
 661 SemaphoreHook (
 662   IN UINTN             CpuIndex,
 663   IN volatile BOOLEAN  *RebasedFlag
 664   );
 665
 666 /**
 667 Configure SMM Code Access Check feature for all processors.
 668 SMM Feature Control MSR will be locked after configuration.
 669 **/
 670 VOID
 671 ConfigSmmCodeAccessCheck (
 672   VOID
 673   );
 674
 675 /**
 676   Hook the code executed immediately after an RSM instruction on the currently
 677   executing CPU.  The mode of code executed immediately after RSM must be
 678   detected, and the appropriate hook must be selected.  Always clear the auto
 679   HALT restart flag if it is set.
 680
 681   @param[in] CpuIndex                 The processor index for the currently
 682                                       executing CPU.
 683   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 684                                       currently executing CPU.
 685   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 686                                       32-bit mode from 64-bit SMM.
 687   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 688                                       same mode as SMM.
 689
 690   @retval The value of the original instruction pointer before it was hooked.
 691
 692 **/
 693 UINT64
 694 EFIAPI
 695 HookReturnFromSmm (
 696   IN UINTN              CpuIndex,
 697   SMRAM_SAVE_STATE_MAP  *CpuState,
 698   UINT64                NewInstructionPointer32,
 699   UINT64                NewInstructionPointer
 700   );
 701
 702 /**
 703   Get the size of the SMI Handler in bytes.
 704
 705   @retval The size, in bytes, of the SMI Handler.
 706
 707 **/
 708 UINTN
 709 EFIAPI
 710 GetSmiHandlerSize (
 711   VOID
 712   );
 713
 714 /**
 715   Install the SMI handler for the CPU specified by CpuIndex.  This function
 716   is called by the CPU that was elected as monarch during System Management
 717   Mode initialization.
 718
 719   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 720                         The value must be between 0 and the NumberOfCpus field
 721                         in the System Management System Table (SMST).
 722   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 723   @param[in] SmiStack   The stack to use when an SMI is processed by the
 724                         the CPU specified by CpuIndex.
 725   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 726                         processed by the CPU specified by CpuIndex.
 727   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 728                         processed by the CPU specified by CpuIndex.
 729   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 730                         processed by the CPU specified by CpuIndex.
 731   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 732                         processed by the CPU specified by CpuIndex.
 733   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 734                         processed by the CPU specified by CpuIndex.
 735   @param[in] Cr3        The base address of the page tables to use when an SMI
 736                         is processed by the CPU specified by CpuIndex.
 737 **/
 738 VOID
 739 EFIAPI
 740 InstallSmiHandler (
 741   IN UINTN   CpuIndex,
 742   IN UINT32  SmBase,
 743   IN VOID    *SmiStack,
 744   IN UINTN   StackSize,
 745   IN UINTN   GdtBase,
 746   IN UINTN   GdtSize,
 747   IN UINTN   IdtBase,
 748   IN UINTN   IdtSize,
 749   IN UINT32  Cr3
 750   );
 751
 752 /**
 753   Search module name by input IP address and output it.
 754
 755   @param CallerIpAddress   Caller instruction pointer.
 756
 757 **/
 758 VOID
 759 DumpModuleInfoByIp (
 760   IN  UINTN              CallerIpAddress
 761   );
 762
 763 /**
 764   This API provides a way to allocate memory for page table.
 765
 766   This API can be called more once to allocate memory for page tables.
 767
 768   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 769   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 770   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 771   returned.
 772
 773   @param  Pages                 The number of 4 KB pages to allocate.
 774
 775   @return A pointer to the allocated buffer or NULL if allocation fails.
 776
 777 **/
 778 VOID *
 779 AllocatePageTableMemory (
 780   IN UINTN           Pages
 781   );
 782
 783
 784 //
 785 // S3 related global variable and function prototype.
 786 //
 787
 788 extern BOOLEAN                mSmmS3Flag;
 789
 790 /**
 791   Initialize SMM S3 resume state structure used during S3 Resume.
 792
 793   @param[in] Cr3    The base address of the page tables to use in SMM.
 794
 795 **/
 796 VOID
 797 InitSmmS3ResumeState (
 798   IN UINT32  Cr3
 799   );
 800
 801 /**
 802   Get ACPI CPU data.
 803
 804 **/
 805 VOID
 806 GetAcpiCpuData (
 807   VOID
 808   );
 809
 810 /**
 811   Restore SMM Configuration in S3 boot path.
 812
 813 **/
 814 VOID
 815 RestoreSmmConfigurationInS3 (
 816   VOID
 817   );
 818
 819 #endif