UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28 #include <Guid/PiSmmMemoryAttributesTable.h>
  29
  30 #include <Library/BaseLib.h>
  31 #include <Library/IoLib.h>
  32 #include <Library/TimerLib.h>
  33 #include <Library/SynchronizationLib.h>
  34 #include <Library/DebugLib.h>
  35 #include <Library/BaseMemoryLib.h>
  36 #include <Library/PcdLib.h>
  37 #include <Library/CacheMaintenanceLib.h>
  38 #include <Library/MtrrLib.h>
  39 #include <Library/SmmCpuPlatformHookLib.h>
  40 #include <Library/SmmServicesTableLib.h>
  41 #include <Library/MemoryAllocationLib.h>
  42 #include <Library/UefiBootServicesTableLib.h>
  43 #include <Library/UefiRuntimeServicesTableLib.h>
  44 #include <Library/DebugAgentLib.h>
  45 #include <Library/HobLib.h>
  46 #include <Library/LocalApicLib.h>
  47 #include <Library/UefiCpuLib.h>
  48 #include <Library/CpuExceptionHandlerLib.h>
  49 #include <Library/ReportStatusCodeLib.h>
  50 #include <Library/SmmCpuFeaturesLib.h>
  51 #include <Library/PeCoffGetEntryPointLib.h>
  52
  53 #include <AcpiCpuData.h>
  54 #include <CpuHotPlugData.h>
  55
  56 #include <Register/Cpuid.h>
  57 #include <Register/Msr.h>
  58
  59 #include "CpuService.h"
  60 #include "SmmProfile.h"
  61
  62 //
  63 // MSRs required for configuration of SMM Code Access Check
  64 //
  65 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  66 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  67
  68 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  69 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  70
  71 ///
  72 /// Page Table Entry
  73 ///
  74 #define IA32_PG_P                   BIT0
  75 #define IA32_PG_RW                  BIT1
  76 #define IA32_PG_U                   BIT2
  77 #define IA32_PG_WT                  BIT3
  78 #define IA32_PG_CD                  BIT4
  79 #define IA32_PG_A                   BIT5
  80 #define IA32_PG_D                   BIT6
  81 #define IA32_PG_PS                  BIT7
  82 #define IA32_PG_PAT_2M              BIT12
  83 #define IA32_PG_PAT_4K              IA32_PG_PS
  84 #define IA32_PG_PMNT                BIT62
  85 #define IA32_PG_NX                  BIT63
  86
  87 #define PAGE_ATTRIBUTE_BITS         (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)
  88 //
  89 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
  90 // X64 PAE PDPTE does not have such restriction
  91 //
  92 #define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)
  93
  94 #define PAGE_PROGATE_BITS           (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)
  95
  96 #define PAGING_4K_MASK  0xFFF
  97 #define PAGING_2M_MASK  0x1FFFFF
  98 #define PAGING_1G_MASK  0x3FFFFFFF
  99
 100 #define PAGING_PAE_INDEX_MASK  0x1FF
 101
 102 #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
 103 #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
 104 #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
 105
 106 typedef enum {
 107   PageNone,
 108   Page4K,
 109   Page2M,
 110   Page1G,
 111 } PAGE_ATTRIBUTE;
 112
 113 typedef struct {
 114   PAGE_ATTRIBUTE   Attribute;
 115   UINT64           Length;
 116   UINT64           AddressMask;
 117 } PAGE_ATTRIBUTE_TABLE;
 118
 119 //
 120 // Size of Task-State Segment defined in IA32 Manual
 121 //
 122 #define TSS_SIZE              104
 123 #define TSS_X64_IST1_OFFSET   36
 124 #define TSS_IA32_CR3_OFFSET   28
 125 #define TSS_IA32_ESP_OFFSET   56
 126
 127 #define CR0_WP                BIT16
 128
 129 //
 130 // Code select value
 131 //
 132 #define PROTECT_MODE_CODE_SEGMENT          0x08
 133 #define LONG_MODE_CODE_SEGMENT             0x38
 134
 135 //
 136 // The size 0x20 must be bigger than
 137 // the size of template code of SmmInit. Currently,
 138 // the size of SmmInit requires the 0x16 Bytes buffer
 139 // at least.
 140 //
 141 #define BACK_BUF_SIZE  0x20
 142
 143 #define EXCEPTION_VECTOR_NUMBER     0x20
 144
 145 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 146
 147 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 148 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 149 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 150 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 151
 152 //
 153 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 154 // Contains the SMM Configuration Protocols that is produced.
 155 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 156 //
 157 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 158
 159 typedef struct {
 160   UINTN                           Signature;
 161
 162   EFI_HANDLE                      SmmCpuHandle;
 163
 164   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 165   SMM_CPU_OPERATION               *Operation;
 166   UINTN                           *CpuSaveStateSize;
 167   VOID                            **CpuSaveState;
 168
 169   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 170   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 171   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 172
 173   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 174 } SMM_CPU_PRIVATE_DATA;
 175
 176 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 177 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 178 extern UINTN                  mMaxNumberOfCpus;
 179 extern UINTN                  mNumberOfCpus;
 180 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 181
 182 ///
 183 /// The mode of the CPU at the time an SMI occurs
 184 ///
 185 extern UINT8  mSmmSaveStateRegisterLma;
 186
 187
 188 //
 189 // SMM CPU Protocol function prototypes.
 190 //
 191
 192 /**
 193   Read information from the CPU save state.
 194
 195   @param  This      EFI_SMM_CPU_PROTOCOL instance
 196   @param  Width     The number of bytes to read from the CPU save state.
 197   @param  Register  Specifies the CPU register to read form the save state.
 198   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 199   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 200
 201   @retval EFI_SUCCESS   The register was read from Save State
 202   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 203   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 204
 205 **/
 206 EFI_STATUS
 207 EFIAPI
 208 SmmReadSaveState (
 209   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 210   IN UINTN                              Width,
 211   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 212   IN UINTN                              CpuIndex,
 213   OUT VOID                              *Buffer
 214   );
 215
 216 /**
 217   Write data to the CPU save state.
 218
 219   @param  This      EFI_SMM_CPU_PROTOCOL instance
 220   @param  Width     The number of bytes to read from the CPU save state.
 221   @param  Register  Specifies the CPU register to write to the save state.
 222   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 223   @param  Buffer    Upon entry, this holds the new CPU register value.
 224
 225   @retval EFI_SUCCESS   The register was written from Save State
 226   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 227   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 228
 229 **/
 230 EFI_STATUS
 231 EFIAPI
 232 SmmWriteSaveState (
 233   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 234   IN UINTN                              Width,
 235   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 236   IN UINTN                              CpuIndex,
 237   IN CONST VOID                         *Buffer
 238   );
 239
 240 /**
 241 Read a CPU Save State register on the target processor.
 242
 243 This function abstracts the differences that whether the CPU Save State register is in the
 244 IA32 CPU Save State Map or X64 CPU Save State Map.
 245
 246 This function supports reading a CPU Save State register in SMBase relocation handler.
 247
 248 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 249 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 250 @param[in]  Width          The number of bytes to read from the CPU save state.
 251 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 252
 253 @retval EFI_SUCCESS           The register was read from Save State.
 254 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 255 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 256
 257 **/
 258 EFI_STATUS
 259 EFIAPI
 260 ReadSaveStateRegister (
 261   IN UINTN                        CpuIndex,
 262   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 263   IN UINTN                        Width,
 264   OUT VOID                        *Buffer
 265   );
 266
 267 /**
 268 Write value to a CPU Save State register on the target processor.
 269
 270 This function abstracts the differences that whether the CPU Save State register is in the
 271 IA32 CPU Save State Map or X64 CPU Save State Map.
 272
 273 This function supports writing a CPU Save State register in SMBase relocation handler.
 274
 275 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 276 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 277 @param[in] Width          The number of bytes to read from the CPU save state.
 278 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 279
 280 @retval EFI_SUCCESS           The register was written to Save State.
 281 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 282 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 283
 284 **/
 285 EFI_STATUS
 286 EFIAPI
 287 WriteSaveStateRegister (
 288   IN UINTN                        CpuIndex,
 289   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 290   IN UINTN                        Width,
 291   IN CONST VOID                   *Buffer
 292   );
 293
 294 //
 295 //
 296 //
 297 typedef struct {
 298   UINT32                            Offset;
 299   UINT16                            Segment;
 300   UINT16                            Reserved;
 301 } IA32_FAR_ADDRESS;
 302
 303 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 304
 305 extern CONST UINT8                  gcSmmInitTemplate[];
 306 extern CONST UINT16                 gcSmmInitSize;
 307 extern UINT32                       gSmmCr0;
 308 extern UINT32                       gSmmCr3;
 309 extern UINT32                       gSmmCr4;
 310 extern UINTN                        gSmmInitStack;
 311
 312 /**
 313   Semaphore operation for all processor relocate SMMBase.
 314 **/
 315 VOID
 316 EFIAPI
 317 SmmRelocationSemaphoreComplete (
 318   VOID
 319   );
 320
 321 ///
 322 /// The type of SMM CPU Information
 323 ///
 324 typedef struct {
 325   SPIN_LOCK                         *Busy;
 326   volatile EFI_AP_PROCEDURE         Procedure;
 327   volatile VOID                     *Parameter;
 328   volatile UINT32                   *Run;
 329   volatile BOOLEAN                  *Present;
 330 } SMM_CPU_DATA_BLOCK;
 331
 332 typedef enum {
 333   SmmCpuSyncModeTradition,
 334   SmmCpuSyncModeRelaxedAp,
 335   SmmCpuSyncModeMax
 336 } SMM_CPU_SYNC_MODE;
 337
 338 typedef struct {
 339   //
 340   // Pointer to an array. The array should be located immediately after this structure
 341   // so that UC cache-ability can be set together.
 342   //
 343   SMM_CPU_DATA_BLOCK            *CpuData;
 344   volatile UINT32               *Counter;
 345   volatile UINT32               BspIndex;
 346   volatile BOOLEAN              *InsideSmm;
 347   volatile BOOLEAN              *AllCpusInSync;
 348   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 349   volatile BOOLEAN              SwitchBsp;
 350   volatile BOOLEAN              *CandidateBsp;
 351 } SMM_DISPATCHER_MP_SYNC_DATA;
 352
 353 #define MSR_SPIN_LOCK_INIT_NUM 15
 354
 355 typedef struct {
 356   SPIN_LOCK    *SpinLock;
 357   UINT32       MsrIndex;
 358 } MP_MSR_LOCK;
 359
 360 #define SMM_PSD_OFFSET              0xfb00
 361
 362 typedef struct {
 363   UINT64                            Signature;              // Offset 0x00
 364   UINT16                            Reserved1;              // Offset 0x08
 365   UINT16                            Reserved2;              // Offset 0x0A
 366   UINT16                            Reserved3;              // Offset 0x0C
 367   UINT16                            SmmCs;                  // Offset 0x0E
 368   UINT16                            SmmDs;                  // Offset 0x10
 369   UINT16                            SmmSs;                  // Offset 0x12
 370   UINT16                            SmmOtherSegment;        // Offset 0x14
 371   UINT16                            Reserved4;              // Offset 0x16
 372   UINT64                            Reserved5;              // Offset 0x18
 373   UINT64                            Reserved6;              // Offset 0x20
 374   UINT64                            Reserved7;              // Offset 0x28
 375   UINT64                            SmmGdtPtr;              // Offset 0x30
 376   UINT32                            SmmGdtSize;             // Offset 0x38
 377   UINT32                            Reserved8;              // Offset 0x3C
 378   UINT64                            Reserved9;              // Offset 0x40
 379   UINT64                            Reserved10;             // Offset 0x48
 380   UINT16                            Reserved11;             // Offset 0x50
 381   UINT16                            Reserved12;             // Offset 0x52
 382   UINT32                            Reserved13;             // Offset 0x54
 383   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 384 } PROCESSOR_SMM_DESCRIPTOR;
 385
 386
 387 ///
 388 /// All global semaphores' pointer
 389 ///
 390 typedef struct {
 391   volatile UINT32      *Counter;
 392   volatile BOOLEAN     *InsideSmm;
 393   volatile BOOLEAN     *AllCpusInSync;
 394   SPIN_LOCK            *PFLock;
 395   SPIN_LOCK            *CodeAccessCheckLock;
 396   SPIN_LOCK            *MemoryMappedLock;
 397 } SMM_CPU_SEMAPHORE_GLOBAL;
 398
 399 ///
 400 /// All semaphores for each processor
 401 ///
 402 typedef struct {
 403   SPIN_LOCK                         *Busy;
 404   volatile UINT32                   *Run;
 405   volatile BOOLEAN                  *Present;
 406 } SMM_CPU_SEMAPHORE_CPU;
 407
 408 ///
 409 /// All MSRs semaphores' pointer and counter
 410 ///
 411 typedef struct {
 412   SPIN_LOCK            *Msr;
 413   UINTN                AvailableCounter;
 414 } SMM_CPU_SEMAPHORE_MSR;
 415
 416 ///
 417 /// All semaphores' information
 418 ///
 419 typedef struct {
 420   SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;
 421   SMM_CPU_SEMAPHORE_CPU             SemaphoreCpu;
 422   SMM_CPU_SEMAPHORE_MSR             SemaphoreMsr;
 423 } SMM_CPU_SEMAPHORES;
 424
 425 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 426 extern EFI_PHYSICAL_ADDRESS                mGdtBuffer;
 427 extern UINTN                               mGdtBufferSize;
 428 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 429 extern VOID                                *gcSmiIdtrPtr;
 430 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 431 extern UINT64                              gPhyMask;
 432 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 433 extern UINTN                               mSmmStackArrayBase;
 434 extern UINTN                               mSmmStackArrayEnd;
 435 extern UINTN                               mSmmStackSize;
 436 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 437 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 438 extern SMM_CPU_SEMAPHORES                  mSmmCpuSemaphores;
 439 extern UINTN                               mSemaphoreSize;
 440 extern SPIN_LOCK                           *mPFLock;
 441 extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;
 442 extern SPIN_LOCK                           *mMemoryMappedLock;
 443
 444 /**
 445   Create 4G PageTable in SMRAM.
 446
 447   @param[in]      Is32BitPageTable Whether the page table is 32-bit PAE
 448   @return         PageTable Address
 449
 450 **/
 451 UINT32
 452 Gen4GPageTable (
 453   IN      BOOLEAN                   Is32BitPageTable
 454   );
 455
 456
 457 /**
 458   Initialize global data for MP synchronization.
 459
 460   @param Stacks       Base address of SMI stack buffer for all processors.
 461   @param StackSize    Stack size for each processor in SMM.
 462
 463 **/
 464 UINT32
 465 InitializeMpServiceData (
 466   IN VOID        *Stacks,
 467   IN UINTN       StackSize
 468   );
 469
 470 /**
 471   Initialize Timer for SMM AP Sync.
 472
 473 **/
 474 VOID
 475 InitializeSmmTimer (
 476   VOID
 477   );
 478
 479 /**
 480   Start Timer for SMM AP Sync.
 481
 482 **/
 483 UINT64
 484 EFIAPI
 485 StartSyncTimer (
 486   VOID
 487   );
 488
 489 /**
 490   Check if the SMM AP Sync timer is timeout.
 491
 492   @param Timer  The start timer from the begin.
 493
 494 **/
 495 BOOLEAN
 496 EFIAPI
 497 IsSyncTimerTimeout (
 498   IN      UINT64                    Timer
 499   );
 500
 501 /**
 502   Initialize IDT for SMM Stack Guard.
 503
 504 **/
 505 VOID
 506 EFIAPI
 507 InitializeIDTSmmStackGuard (
 508   VOID
 509   );
 510
 511 /**
 512   Initialize Gdt for all processors.
 513
 514   @param[in]   Cr3          CR3 value.
 515   @param[out]  GdtStepSize  The step size for GDT table.
 516
 517   @return GdtBase for processor 0.
 518           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 519 **/
 520 VOID *
 521 InitGdt (
 522   IN  UINTN  Cr3,
 523   OUT UINTN  *GdtStepSize
 524   );
 525
 526 /**
 527
 528   Register the SMM Foundation entry point.
 529
 530   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 531   @param          SmmEntryPoint     SMM Foundation EntryPoint
 532
 533   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 534
 535 **/
 536 EFI_STATUS
 537 EFIAPI
 538 RegisterSmmEntry (
 539   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 540   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 541   );
 542
 543 /**
 544   Create PageTable for SMM use.
 545
 546   @return     PageTable Address
 547
 548 **/
 549 UINT32
 550 SmmInitPageTable (
 551   VOID
 552   );
 553
 554 /**
 555   Schedule a procedure to run on the specified CPU.
 556
 557   @param   Procedure        The address of the procedure to run
 558   @param   CpuIndex         Target CPU number
 559   @param   ProcArguments    The parameter to pass to the procedure
 560
 561   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 562   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 563   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 564   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 565   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 566
 567 **/
 568 EFI_STATUS
 569 EFIAPI
 570 SmmStartupThisAp (
 571   IN      EFI_AP_PROCEDURE          Procedure,
 572   IN      UINTN                     CpuIndex,
 573   IN OUT  VOID                      *ProcArguments OPTIONAL
 574   );
 575
 576 /**
 577   Schedule a procedure to run on the specified CPU in a blocking fashion.
 578
 579   @param  Procedure                The address of the procedure to run
 580   @param  CpuIndex                 Target CPU Index
 581   @param  ProcArguments            The parameter to pass to the procedure
 582
 583   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 584   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 585   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 586   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 587   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 588
 589 **/
 590 EFI_STATUS
 591 EFIAPI
 592 SmmBlockingStartupThisAp (
 593   IN      EFI_AP_PROCEDURE          Procedure,
 594   IN      UINTN                     CpuIndex,
 595   IN OUT  VOID                      *ProcArguments OPTIONAL
 596   );
 597
 598 /**
 599   Initialize MP synchronization data.
 600
 601 **/
 602 VOID
 603 EFIAPI
 604 InitializeMpSyncData (
 605   VOID
 606   );
 607
 608 /**
 609
 610   Find out SMRAM information including SMRR base and SMRR size.
 611
 612   @param          SmrrBase          SMRR base
 613   @param          SmrrSize          SMRR size
 614
 615 **/
 616 VOID
 617 FindSmramInfo (
 618   OUT UINT32   *SmrrBase,
 619   OUT UINT32   *SmrrSize
 620   );
 621
 622 /**
 623   Relocate SmmBases for each processor.
 624
 625   Execute on first boot and all S3 resumes
 626
 627 **/
 628 VOID
 629 EFIAPI
 630 SmmRelocateBases (
 631   VOID
 632   );
 633
 634 /**
 635   Page Fault handler for SMM use.
 636
 637   @param  InterruptType    Defines the type of interrupt or exception that
 638                            occurred on the processor.This parameter is processor architecture specific.
 639   @param  SystemContext    A pointer to the processor context when
 640                            the interrupt occurred on the processor.
 641 **/
 642 VOID
 643 EFIAPI
 644 SmiPFHandler (
 645     IN EFI_EXCEPTION_TYPE   InterruptType,
 646     IN EFI_SYSTEM_CONTEXT   SystemContext
 647   );
 648
 649 /**
 650   Perform the remaining tasks.
 651
 652 **/
 653 VOID
 654 PerformRemainingTasks (
 655   VOID
 656   );
 657
 658 /**
 659   Perform the pre tasks.
 660
 661 **/
 662 VOID
 663 PerformPreTasks (
 664   VOID
 665   );
 666
 667 /**
 668   Initialize MSR spin lock by MSR index.
 669
 670   @param  MsrIndex       MSR index value.
 671
 672 **/
 673 VOID
 674 InitMsrSpinLockByIndex (
 675   IN UINT32      MsrIndex
 676   );
 677
 678 /**
 679   Hook return address of SMM Save State so that semaphore code
 680   can be executed immediately after AP exits SMM to indicate to
 681   the BSP that an AP has exited SMM after SMBASE relocation.
 682
 683   @param[in] CpuIndex     The processor index.
 684   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 685                           immediately after AP exits SMM.
 686
 687 **/
 688 VOID
 689 SemaphoreHook (
 690   IN UINTN             CpuIndex,
 691   IN volatile BOOLEAN  *RebasedFlag
 692   );
 693
 694 /**
 695 Configure SMM Code Access Check feature for all processors.
 696 SMM Feature Control MSR will be locked after configuration.
 697 **/
 698 VOID
 699 ConfigSmmCodeAccessCheck (
 700   VOID
 701   );
 702
 703 /**
 704   Hook the code executed immediately after an RSM instruction on the currently
 705   executing CPU.  The mode of code executed immediately after RSM must be
 706   detected, and the appropriate hook must be selected.  Always clear the auto
 707   HALT restart flag if it is set.
 708
 709   @param[in] CpuIndex                 The processor index for the currently
 710                                       executing CPU.
 711   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 712                                       currently executing CPU.
 713   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 714                                       32-bit mode from 64-bit SMM.
 715   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 716                                       same mode as SMM.
 717
 718   @retval The value of the original instruction pointer before it was hooked.
 719
 720 **/
 721 UINT64
 722 EFIAPI
 723 HookReturnFromSmm (
 724   IN UINTN              CpuIndex,
 725   SMRAM_SAVE_STATE_MAP  *CpuState,
 726   UINT64                NewInstructionPointer32,
 727   UINT64                NewInstructionPointer
 728   );
 729
 730 /**
 731   Get the size of the SMI Handler in bytes.
 732
 733   @retval The size, in bytes, of the SMI Handler.
 734
 735 **/
 736 UINTN
 737 EFIAPI
 738 GetSmiHandlerSize (
 739   VOID
 740   );
 741
 742 /**
 743   Install the SMI handler for the CPU specified by CpuIndex.  This function
 744   is called by the CPU that was elected as monarch during System Management
 745   Mode initialization.
 746
 747   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 748                         The value must be between 0 and the NumberOfCpus field
 749                         in the System Management System Table (SMST).
 750   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 751   @param[in] SmiStack   The stack to use when an SMI is processed by the
 752                         the CPU specified by CpuIndex.
 753   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 754                         processed by the CPU specified by CpuIndex.
 755   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 756                         processed by the CPU specified by CpuIndex.
 757   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 758                         processed by the CPU specified by CpuIndex.
 759   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 760                         processed by the CPU specified by CpuIndex.
 761   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 762                         processed by the CPU specified by CpuIndex.
 763   @param[in] Cr3        The base address of the page tables to use when an SMI
 764                         is processed by the CPU specified by CpuIndex.
 765 **/
 766 VOID
 767 EFIAPI
 768 InstallSmiHandler (
 769   IN UINTN   CpuIndex,
 770   IN UINT32  SmBase,
 771   IN VOID    *SmiStack,
 772   IN UINTN   StackSize,
 773   IN UINTN   GdtBase,
 774   IN UINTN   GdtSize,
 775   IN UINTN   IdtBase,
 776   IN UINTN   IdtSize,
 777   IN UINT32  Cr3
 778   );
 779
 780 /**
 781   Search module name by input IP address and output it.
 782
 783   @param CallerIpAddress   Caller instruction pointer.
 784
 785 **/
 786 VOID
 787 DumpModuleInfoByIp (
 788   IN  UINTN              CallerIpAddress
 789   );
 790
 791 /**
 792   This function sets memory attribute according to MemoryAttributesTable.
 793 **/
 794 VOID
 795 SetMemMapAttributes (
 796   VOID
 797   );
 798
 799 /**
 800   This function sets memory attribute for page table.
 801 **/
 802 VOID
 803 SetPageTableAttributes (
 804   VOID
 805   );
 806
 807 /**
 808   Return page table base.
 809
 810   @return page table base.
 811 **/
 812 UINTN
 813 GetPageTableBase (
 814   VOID
 815   );
 816
 817 /**
 818   This function sets the attributes for the memory region specified by BaseAddress and
 819   Length from their current attributes to the attributes specified by Attributes.
 820
 821   @param[in]   BaseAddress      The physical address that is the start address of a memory region.
 822   @param[in]   Length           The size in bytes of the memory region.
 823   @param[in]   Attributes       The bit mask of attributes to set for the memory region.
 824   @param[out]  IsSplitted       TRUE means page table splitted. FALSE means page table not splitted.
 825
 826   @retval EFI_SUCCESS           The attributes were set for the memory region.
 827   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 828                                 BaseAddress and Length cannot be modified.
 829   @retval EFI_INVALID_PARAMETER Length is zero.
 830                                 Attributes specified an illegal combination of attributes that
 831                                 cannot be set together.
 832   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 833                                 the memory resource range.
 834   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 835                                 resource range specified by BaseAddress and Length.
 836                                 The bit mask of attributes is not support for the memory resource
 837                                 range specified by BaseAddress and Length.
 838
 839 **/
 840 EFI_STATUS
 841 EFIAPI
 842 SmmSetMemoryAttributesEx (
 843   IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,
 844   IN  UINT64                                     Length,
 845   IN  UINT64                                     Attributes,
 846   OUT BOOLEAN                                    *IsSplitted  OPTIONAL
 847   );
 848
 849 /**
 850   This function clears the attributes for the memory region specified by BaseAddress and
 851   Length from their current attributes to the attributes specified by Attributes.
 852
 853   @param[in]   BaseAddress      The physical address that is the start address of a memory region.
 854   @param[in]   Length           The size in bytes of the memory region.
 855   @param[in]   Attributes       The bit mask of attributes to clear for the memory region.
 856   @param[out]  IsSplitted       TRUE means page table splitted. FALSE means page table not splitted.
 857
 858   @retval EFI_SUCCESS           The attributes were cleared for the memory region.
 859   @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by
 860                                 BaseAddress and Length cannot be modified.
 861   @retval EFI_INVALID_PARAMETER Length is zero.
 862                                 Attributes specified an illegal combination of attributes that
 863                                 cannot be set together.
 864   @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of
 865                                 the memory resource range.
 866   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
 867                                 resource range specified by BaseAddress and Length.
 868                                 The bit mask of attributes is not support for the memory resource
 869                                 range specified by BaseAddress and Length.
 870
 871 **/
 872 EFI_STATUS
 873 EFIAPI
 874 SmmClearMemoryAttributesEx (
 875   IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,
 876   IN  UINT64                                     Length,
 877   IN  UINT64                                     Attributes,
 878   OUT BOOLEAN                                    *IsSplitted  OPTIONAL
 879   );
 880
 881 /**
 882   This API provides a way to allocate memory for page table.
 883
 884   This API can be called more once to allocate memory for page tables.
 885
 886   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 887   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 888   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 889   returned.
 890
 891   @param  Pages                 The number of 4 KB pages to allocate.
 892
 893   @return A pointer to the allocated buffer or NULL if allocation fails.
 894
 895 **/
 896 VOID *
 897 AllocatePageTableMemory (
 898   IN UINTN           Pages
 899   );
 900
 901 /**
 902   Allocate pages for code.
 903
 904   @param[in]  Pages Number of pages to be allocated.
 905
 906   @return Allocated memory.
 907 **/
 908 VOID *
 909 AllocateCodePages (
 910   IN UINTN           Pages
 911   );
 912
 913 /**
 914   Allocate aligned pages for code.
 915
 916   @param[in]  Pages                 Number of pages to be allocated.
 917   @param[in]  Alignment             The requested alignment of the allocation.
 918                                     Must be a power of two.
 919                                     If Alignment is zero, then byte alignment is used.
 920
 921   @return Allocated memory.
 922 **/
 923 VOID *
 924 AllocateAlignedCodePages (
 925   IN UINTN            Pages,
 926   IN UINTN            Alignment
 927   );
 928
 929
 930 //
 931 // S3 related global variable and function prototype.
 932 //
 933
 934 extern BOOLEAN                mSmmS3Flag;
 935
 936 /**
 937   Initialize SMM S3 resume state structure used during S3 Resume.
 938
 939   @param[in] Cr3    The base address of the page tables to use in SMM.
 940
 941 **/
 942 VOID
 943 InitSmmS3ResumeState (
 944   IN UINT32  Cr3
 945   );
 946
 947 /**
 948   Get ACPI CPU data.
 949
 950 **/
 951 VOID
 952 GetAcpiCpuData (
 953   VOID
 954   );
 955
 956 /**
 957   Restore SMM Configuration in S3 boot path.
 958
 959 **/
 960 VOID
 961 RestoreSmmConfigurationInS3 (
 962   VOID
 963   );
 964
 965 /**
 966   Get ACPI S3 enable flag.
 967
 968 **/
 969 VOID
 970 GetAcpiS3EnableFlag (
 971   VOID
 972   );
 973
 974 /**
 975   Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.
 976
 977   @param[in] ApHltLoopCode          The address of the safe hlt-loop function.
 978   @param[in] TopOfStack             A pointer to the new stack to use for the ApHltLoopCode.
 979   @param[in] NumberToFinishAddress  Address of Semaphore of APs finish count.
 980
 981 **/
 982 VOID
 983 TransferApToSafeState (
 984   IN UINTN  ApHltLoopCode,
 985   IN UINTN  TopOfStack,
 986   IN UINTN  NumberToFinishAddress
 987   );
 988
 989 #endif